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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -fast-isel -fast-isel-abort=1 -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s3 4define zeroext i16 @asr_zext_i1_i16(i1 %b) {5; CHECK-LABEL: asr_zext_i1_i16:6; CHECK: ; %bb.0:7; CHECK-NEXT: uxth w0, wzr8; CHECK-NEXT: ret9 %1 = zext i1 %b to i1610 %2 = ashr i16 %1, 111 ret i16 %212}13 14define signext i16 @asr_sext_i1_i16(i1 %b) {15; CHECK-LABEL: asr_sext_i1_i16:16; CHECK: ; %bb.0:17; CHECK-NEXT: sbfx w8, w0, #0, #118; CHECK-NEXT: sxth w0, w819; CHECK-NEXT: ret20 %1 = sext i1 %b to i1621 %2 = ashr i16 %1, 122 ret i16 %223}24 25define i32 @asr_zext_i1_i32(i1 %b) {26; CHECK-LABEL: asr_zext_i1_i32:27; CHECK: ; %bb.0:28; CHECK-NEXT: mov w0, wzr29; CHECK-NEXT: ret30 %1 = zext i1 %b to i3231 %2 = ashr i32 %1, 132 ret i32 %233}34 35define i32 @asr_sext_i1_i32(i1 %b) {36; CHECK-LABEL: asr_sext_i1_i32:37; CHECK: ; %bb.0:38; CHECK-NEXT: sbfx w0, w0, #0, #139; CHECK-NEXT: ret40 %1 = sext i1 %b to i3241 %2 = ashr i32 %1, 142 ret i32 %243}44 45define i64 @asr_zext_i1_i64(i1 %b) {46; CHECK-LABEL: asr_zext_i1_i64:47; CHECK: ; %bb.0:48; CHECK-NEXT: mov x0, xzr49; CHECK-NEXT: ret50 %1 = zext i1 %b to i6451 %2 = ashr i64 %1, 152 ret i64 %253}54 55define i64 @asr_sext_i1_i64(i1 %b) {56; CHECK-LABEL: asr_sext_i1_i64:57; CHECK: ; %bb.0:58; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x059; CHECK-NEXT: sbfx x0, x0, #0, #160; CHECK-NEXT: ret61 %1 = sext i1 %b to i6462 %2 = ashr i64 %1, 163 ret i64 %264}65 66define zeroext i16 @lsr_zext_i1_i16(i1 %b) {67; CHECK-LABEL: lsr_zext_i1_i16:68; CHECK: ; %bb.0:69; CHECK-NEXT: uxth w0, wzr70; CHECK-NEXT: ret71 %1 = zext i1 %b to i1672 %2 = lshr i16 %1, 173 ret i16 %274}75 76define signext i16 @lsr_sext_i1_i16(i1 %b) {77; CHECK-LABEL: lsr_sext_i1_i16:78; CHECK: ; %bb.0:79; CHECK-NEXT: sbfx w8, w0, #0, #180; CHECK-NEXT: ubfx w8, w8, #1, #1581; CHECK-NEXT: sxth w0, w882; CHECK-NEXT: ret83 %1 = sext i1 %b to i1684 %2 = lshr i16 %1, 185 ret i16 %286}87 88define i32 @lsr_zext_i1_i32(i1 %b) {89; CHECK-LABEL: lsr_zext_i1_i32:90; CHECK: ; %bb.0:91; CHECK-NEXT: mov w0, wzr92; CHECK-NEXT: ret93 %1 = zext i1 %b to i3294 %2 = lshr i32 %1, 195 ret i32 %296}97 98define i32 @lsr_sext_i1_i32(i1 %b) {99; CHECK-LABEL: lsr_sext_i1_i32:100; CHECK: ; %bb.0:101; CHECK-NEXT: sbfx w8, w0, #0, #1102; CHECK-NEXT: lsr w0, w8, #1103; CHECK-NEXT: ret104 %1 = sext i1 %b to i32105 %2 = lshr i32 %1, 1106 ret i32 %2107}108 109define i64 @lsr_zext_i1_i64(i1 %b) {110; CHECK-LABEL: lsr_zext_i1_i64:111; CHECK: ; %bb.0:112; CHECK-NEXT: mov x0, xzr113; CHECK-NEXT: ret114 %1 = zext i1 %b to i64115 %2 = lshr i64 %1, 1116 ret i64 %2117}118 119define zeroext i16 @lsl_zext_i1_i16(i1 %b) {120; CHECK-LABEL: lsl_zext_i1_i16:121; CHECK: ; %bb.0:122; CHECK-NEXT: ubfiz w8, w0, #4, #1123; CHECK-NEXT: uxth w0, w8124; CHECK-NEXT: ret125 %1 = zext i1 %b to i16126 %2 = shl i16 %1, 4127 ret i16 %2128}129 130define signext i16 @lsl_sext_i1_i16(i1 %b) {131; CHECK-LABEL: lsl_sext_i1_i16:132; CHECK: ; %bb.0:133; CHECK-NEXT: sbfiz w8, w0, #4, #1134; CHECK-NEXT: sxth w0, w8135; CHECK-NEXT: ret136 %1 = sext i1 %b to i16137 %2 = shl i16 %1, 4138 ret i16 %2139}140 141define i32 @lsl_zext_i1_i32(i1 %b) {142; CHECK-LABEL: lsl_zext_i1_i32:143; CHECK: ; %bb.0:144; CHECK-NEXT: ubfiz w0, w0, #4, #1145; CHECK-NEXT: ret146 %1 = zext i1 %b to i32147 %2 = shl i32 %1, 4148 ret i32 %2149}150 151define i32 @lsl_sext_i1_i32(i1 %b) {152; CHECK-LABEL: lsl_sext_i1_i32:153; CHECK: ; %bb.0:154; CHECK-NEXT: sbfiz w0, w0, #4, #1155; CHECK-NEXT: ret156 %1 = sext i1 %b to i32157 %2 = shl i32 %1, 4158 ret i32 %2159}160 161define i64 @lsl_zext_i1_i64(i1 %b) {162; CHECK-LABEL: lsl_zext_i1_i64:163; CHECK: ; %bb.0:164; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0165; CHECK-NEXT: ubfiz x0, x0, #4, #1166; CHECK-NEXT: ret167 %1 = zext i1 %b to i64168 %2 = shl i64 %1, 4169 ret i64 %2170}171 172define i64 @lsl_sext_i1_i64(i1 %b) {173; CHECK-LABEL: lsl_sext_i1_i64:174; CHECK: ; %bb.0:175; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0176; CHECK-NEXT: sbfiz x0, x0, #4, #1177; CHECK-NEXT: ret178 %1 = sext i1 %b to i64179 %2 = shl i64 %1, 4180 ret i64 %2181}182 183define zeroext i8 @lslv_i8(i8 %a, i8 %b) {184; CHECK-LABEL: lslv_i8:185; CHECK: ; %bb.0:186; CHECK-NEXT: and w8, w1, #0xff187; CHECK-NEXT: lsl w8, w0, w8188; CHECK-NEXT: and w8, w8, #0xff189; CHECK-NEXT: uxtb w0, w8190; CHECK-NEXT: ret191 %1 = shl i8 %a, %b192 ret i8 %1193}194 195define zeroext i8 @lsl_i8(i8 %a) {196; CHECK-LABEL: lsl_i8:197; CHECK: ; %bb.0:198; CHECK-NEXT: ubfiz w8, w0, #4, #4199; CHECK-NEXT: uxtb w0, w8200; CHECK-NEXT: ret201 %1 = shl i8 %a, 4202 ret i8 %1203}204 205define zeroext i16 @lsl_zext_i8_i16(i8 %b) {206; CHECK-LABEL: lsl_zext_i8_i16:207; CHECK: ; %bb.0:208; CHECK-NEXT: ubfiz w8, w0, #4, #8209; CHECK-NEXT: uxth w0, w8210; CHECK-NEXT: ret211 %1 = zext i8 %b to i16212 %2 = shl i16 %1, 4213 ret i16 %2214}215 216define signext i16 @lsl_sext_i8_i16(i8 %b) {217; CHECK-LABEL: lsl_sext_i8_i16:218; CHECK: ; %bb.0:219; CHECK-NEXT: sbfiz w8, w0, #4, #8220; CHECK-NEXT: sxth w0, w8221; CHECK-NEXT: ret222 %1 = sext i8 %b to i16223 %2 = shl i16 %1, 4224 ret i16 %2225}226 227define i32 @lsl_zext_i8_i32(i8 %b) {228; CHECK-LABEL: lsl_zext_i8_i32:229; CHECK: ; %bb.0:230; CHECK-NEXT: ubfiz w0, w0, #4, #8231; CHECK-NEXT: ret232 %1 = zext i8 %b to i32233 %2 = shl i32 %1, 4234 ret i32 %2235}236 237define i32 @lsl_sext_i8_i32(i8 %b) {238; CHECK-LABEL: lsl_sext_i8_i32:239; CHECK: ; %bb.0:240; CHECK-NEXT: sbfiz w0, w0, #4, #8241; CHECK-NEXT: ret242 %1 = sext i8 %b to i32243 %2 = shl i32 %1, 4244 ret i32 %2245}246 247define i64 @lsl_zext_i8_i64(i8 %b) {248; CHECK-LABEL: lsl_zext_i8_i64:249; CHECK: ; %bb.0:250; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0251; CHECK-NEXT: ubfiz x0, x0, #4, #8252; CHECK-NEXT: ret253 %1 = zext i8 %b to i64254 %2 = shl i64 %1, 4255 ret i64 %2256}257 258define i64 @lsl_sext_i8_i64(i8 %b) {259; CHECK-LABEL: lsl_sext_i8_i64:260; CHECK: ; %bb.0:261; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0262; CHECK-NEXT: sbfiz x0, x0, #4, #8263; CHECK-NEXT: ret264 %1 = sext i8 %b to i64265 %2 = shl i64 %1, 4266 ret i64 %2267}268 269define zeroext i16 @lslv_i16(i16 %a, i16 %b) {270; CHECK-LABEL: lslv_i16:271; CHECK: ; %bb.0:272; CHECK-NEXT: and w8, w1, #0xffff273; CHECK-NEXT: lsl w8, w0, w8274; CHECK-NEXT: and w8, w8, #0xffff275; CHECK-NEXT: uxth w0, w8276; CHECK-NEXT: ret277 %1 = shl i16 %a, %b278 ret i16 %1279}280 281define zeroext i16 @lsl_i16(i16 %a) {282; CHECK-LABEL: lsl_i16:283; CHECK: ; %bb.0:284; CHECK-NEXT: ubfiz w8, w0, #8, #8285; CHECK-NEXT: uxth w0, w8286; CHECK-NEXT: ret287 %1 = shl i16 %a, 8288 ret i16 %1289}290 291define i32 @lsl_zext_i16_i32(i16 %b) {292; CHECK-LABEL: lsl_zext_i16_i32:293; CHECK: ; %bb.0:294; CHECK-NEXT: ubfiz w0, w0, #8, #16295; CHECK-NEXT: ret296 %1 = zext i16 %b to i32297 %2 = shl i32 %1, 8298 ret i32 %2299}300 301define i32 @lsl_sext_i16_i32(i16 %b) {302; CHECK-LABEL: lsl_sext_i16_i32:303; CHECK: ; %bb.0:304; CHECK-NEXT: sbfiz w0, w0, #8, #16305; CHECK-NEXT: ret306 %1 = sext i16 %b to i32307 %2 = shl i32 %1, 8308 ret i32 %2309}310 311define i64 @lsl_zext_i16_i64(i16 %b) {312; CHECK-LABEL: lsl_zext_i16_i64:313; CHECK: ; %bb.0:314; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0315; CHECK-NEXT: ubfiz x0, x0, #8, #16316; CHECK-NEXT: ret317 %1 = zext i16 %b to i64318 %2 = shl i64 %1, 8319 ret i64 %2320}321 322define i64 @lsl_sext_i16_i64(i16 %b) {323; CHECK-LABEL: lsl_sext_i16_i64:324; CHECK: ; %bb.0:325; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0326; CHECK-NEXT: sbfiz x0, x0, #8, #16327; CHECK-NEXT: ret328 %1 = sext i16 %b to i64329 %2 = shl i64 %1, 8330 ret i64 %2331}332 333define zeroext i32 @lslv_i32(i32 %a, i32 %b) {334; CHECK-LABEL: lslv_i32:335; CHECK: ; %bb.0:336; CHECK-NEXT: lsl w0, w0, w1337; CHECK-NEXT: ret338 %1 = shl i32 %a, %b339 ret i32 %1340}341 342define zeroext i32 @lsl_i32(i32 %a) {343; CHECK-LABEL: lsl_i32:344; CHECK: ; %bb.0:345; CHECK-NEXT: lsl w0, w0, #16346; CHECK-NEXT: ret347 %1 = shl i32 %a, 16348 ret i32 %1349}350 351define i64 @lsl_zext_i32_i64(i32 %b) {352; CHECK-LABEL: lsl_zext_i32_i64:353; CHECK: ; %bb.0:354; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0355; CHECK-NEXT: ubfiz x0, x0, #16, #32356; CHECK-NEXT: ret357 %1 = zext i32 %b to i64358 %2 = shl i64 %1, 16359 ret i64 %2360}361 362define i64 @lsl_sext_i32_i64(i32 %b) {363; CHECK-LABEL: lsl_sext_i32_i64:364; CHECK: ; %bb.0:365; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0366; CHECK-NEXT: sbfiz x0, x0, #16, #32367; CHECK-NEXT: ret368 %1 = sext i32 %b to i64369 %2 = shl i64 %1, 16370 ret i64 %2371}372 373define i64 @lslv_i64(i64 %a, i64 %b) {374; CHECK-LABEL: lslv_i64:375; CHECK: ; %bb.0:376; CHECK-NEXT: lsl x0, x0, x1377; CHECK-NEXT: ret378 %1 = shl i64 %a, %b379 ret i64 %1380}381 382define i64 @lsl_i64(i64 %a) {383; CHECK-LABEL: lsl_i64:384; CHECK: ; %bb.0:385; CHECK-NEXT: lsl x0, x0, #32386; CHECK-NEXT: ret387 %1 = shl i64 %a, 32388 ret i64 %1389}390 391define zeroext i8 @lsrv_i8(i8 %a, i8 %b) {392; CHECK-LABEL: lsrv_i8:393; CHECK: ; %bb.0:394; CHECK-NEXT: and w8, w0, #0xff395; CHECK-NEXT: and w9, w1, #0xff396; CHECK-NEXT: lsr w8, w8, w9397; CHECK-NEXT: and w8, w8, #0xff398; CHECK-NEXT: uxtb w0, w8399; CHECK-NEXT: ret400 %1 = lshr i8 %a, %b401 ret i8 %1402}403 404define zeroext i8 @lsr_i8(i8 %a) {405; CHECK-LABEL: lsr_i8:406; CHECK: ; %bb.0:407; CHECK-NEXT: ubfx w8, w0, #4, #4408; CHECK-NEXT: uxtb w0, w8409; CHECK-NEXT: ret410 %1 = lshr i8 %a, 4411 ret i8 %1412}413 414define zeroext i16 @lsr_zext_i8_i16(i8 %b) {415; CHECK-LABEL: lsr_zext_i8_i16:416; CHECK: ; %bb.0:417; CHECK-NEXT: ubfx w8, w0, #4, #4418; CHECK-NEXT: uxth w0, w8419; CHECK-NEXT: ret420 %1 = zext i8 %b to i16421 %2 = lshr i16 %1, 4422 ret i16 %2423}424 425define signext i16 @lsr_sext_i8_i16(i8 %b) {426; CHECK-LABEL: lsr_sext_i8_i16:427; CHECK: ; %bb.0:428; CHECK-NEXT: sxtb w8, w0429; CHECK-NEXT: ubfx w8, w8, #4, #12430; CHECK-NEXT: sxth w0, w8431; CHECK-NEXT: ret432 %1 = sext i8 %b to i16433 %2 = lshr i16 %1, 4434 ret i16 %2435}436 437define i32 @lsr_zext_i8_i32(i8 %b) {438; CHECK-LABEL: lsr_zext_i8_i32:439; CHECK: ; %bb.0:440; CHECK-NEXT: ubfx w0, w0, #4, #4441; CHECK-NEXT: ret442 %1 = zext i8 %b to i32443 %2 = lshr i32 %1, 4444 ret i32 %2445}446 447define i32 @lsr_sext_i8_i32(i8 %b) {448; CHECK-LABEL: lsr_sext_i8_i32:449; CHECK: ; %bb.0:450; CHECK-NEXT: sxtb w8, w0451; CHECK-NEXT: lsr w0, w8, #4452; CHECK-NEXT: ret453 %1 = sext i8 %b to i32454 %2 = lshr i32 %1, 4455 ret i32 %2456}457 458define zeroext i16 @lsrv_i16(i16 %a, i16 %b) {459; CHECK-LABEL: lsrv_i16:460; CHECK: ; %bb.0:461; CHECK-NEXT: and w8, w0, #0xffff462; CHECK-NEXT: and w9, w1, #0xffff463; CHECK-NEXT: lsr w8, w8, w9464; CHECK-NEXT: and w8, w8, #0xffff465; CHECK-NEXT: uxth w0, w8466; CHECK-NEXT: ret467 %1 = lshr i16 %a, %b468 ret i16 %1469}470 471define zeroext i16 @lsr_i16(i16 %a) {472; CHECK-LABEL: lsr_i16:473; CHECK: ; %bb.0:474; CHECK-NEXT: ubfx w8, w0, #8, #8475; CHECK-NEXT: uxth w0, w8476; CHECK-NEXT: ret477 %1 = lshr i16 %a, 8478 ret i16 %1479}480 481define zeroext i32 @lsrv_i32(i32 %a, i32 %b) {482; CHECK-LABEL: lsrv_i32:483; CHECK: ; %bb.0:484; CHECK-NEXT: lsr w0, w0, w1485; CHECK-NEXT: ret486 %1 = lshr i32 %a, %b487 ret i32 %1488}489 490define zeroext i32 @lsr_i32(i32 %a) {491; CHECK-LABEL: lsr_i32:492; CHECK: ; %bb.0:493; CHECK-NEXT: lsr w0, w0, #16494; CHECK-NEXT: ret495 %1 = lshr i32 %a, 16496 ret i32 %1497}498 499define i64 @lsrv_i64(i64 %a, i64 %b) {500; CHECK-LABEL: lsrv_i64:501; CHECK: ; %bb.0:502; CHECK-NEXT: lsr x0, x0, x1503; CHECK-NEXT: ret504 %1 = lshr i64 %a, %b505 ret i64 %1506}507 508define i64 @lsr_i64(i64 %a) {509; CHECK-LABEL: lsr_i64:510; CHECK: ; %bb.0:511; CHECK-NEXT: lsr x0, x0, #32512; CHECK-NEXT: ret513 %1 = lshr i64 %a, 32514 ret i64 %1515}516 517define zeroext i8 @asrv_i8(i8 %a, i8 %b) {518; CHECK-LABEL: asrv_i8:519; CHECK: ; %bb.0:520; CHECK-NEXT: sxtb w8, w0521; CHECK-NEXT: and w9, w1, #0xff522; CHECK-NEXT: asr w8, w8, w9523; CHECK-NEXT: and w8, w8, #0xff524; CHECK-NEXT: uxtb w0, w8525; CHECK-NEXT: ret526 %1 = ashr i8 %a, %b527 ret i8 %1528}529 530define zeroext i8 @asr_i8(i8 %a) {531; CHECK-LABEL: asr_i8:532; CHECK: ; %bb.0:533; CHECK-NEXT: sbfx w8, w0, #4, #4534; CHECK-NEXT: uxtb w0, w8535; CHECK-NEXT: ret536 %1 = ashr i8 %a, 4537 ret i8 %1538}539 540define zeroext i16 @asr_zext_i8_i16(i8 %b) {541; CHECK-LABEL: asr_zext_i8_i16:542; CHECK: ; %bb.0:543; CHECK-NEXT: ubfx w8, w0, #4, #4544; CHECK-NEXT: uxth w0, w8545; CHECK-NEXT: ret546 %1 = zext i8 %b to i16547 %2 = ashr i16 %1, 4548 ret i16 %2549}550 551define signext i16 @asr_sext_i8_i16(i8 %b) {552; CHECK-LABEL: asr_sext_i8_i16:553; CHECK: ; %bb.0:554; CHECK-NEXT: sbfx w8, w0, #4, #4555; CHECK-NEXT: sxth w0, w8556; CHECK-NEXT: ret557 %1 = sext i8 %b to i16558 %2 = ashr i16 %1, 4559 ret i16 %2560}561 562define i32 @asr_zext_i8_i32(i8 %b) {563; CHECK-LABEL: asr_zext_i8_i32:564; CHECK: ; %bb.0:565; CHECK-NEXT: ubfx w0, w0, #4, #4566; CHECK-NEXT: ret567 %1 = zext i8 %b to i32568 %2 = ashr i32 %1, 4569 ret i32 %2570}571 572define i32 @asr_sext_i8_i32(i8 %b) {573; CHECK-LABEL: asr_sext_i8_i32:574; CHECK: ; %bb.0:575; CHECK-NEXT: sbfx w0, w0, #4, #4576; CHECK-NEXT: ret577 %1 = sext i8 %b to i32578 %2 = ashr i32 %1, 4579 ret i32 %2580}581 582define zeroext i16 @asrv_i16(i16 %a, i16 %b) {583; CHECK-LABEL: asrv_i16:584; CHECK: ; %bb.0:585; CHECK-NEXT: sxth w8, w0586; CHECK-NEXT: and w9, w1, #0xffff587; CHECK-NEXT: asr w8, w8, w9588; CHECK-NEXT: and w8, w8, #0xffff589; CHECK-NEXT: uxth w0, w8590; CHECK-NEXT: ret591 %1 = ashr i16 %a, %b592 ret i16 %1593}594 595define zeroext i16 @asr_i16(i16 %a) {596; CHECK-LABEL: asr_i16:597; CHECK: ; %bb.0:598; CHECK-NEXT: sbfx w8, w0, #8, #8599; CHECK-NEXT: uxth w0, w8600; CHECK-NEXT: ret601 %1 = ashr i16 %a, 8602 ret i16 %1603}604 605define zeroext i32 @asrv_i32(i32 %a, i32 %b) {606; CHECK-LABEL: asrv_i32:607; CHECK: ; %bb.0:608; CHECK-NEXT: asr w0, w0, w1609; CHECK-NEXT: ret610 %1 = ashr i32 %a, %b611 ret i32 %1612}613 614define zeroext i32 @asr_i32(i32 %a) {615; CHECK-LABEL: asr_i32:616; CHECK: ; %bb.0:617; CHECK-NEXT: asr w0, w0, #16618; CHECK-NEXT: ret619 %1 = ashr i32 %a, 16620 ret i32 %1621}622 623define i64 @asrv_i64(i64 %a, i64 %b) {624; CHECK-LABEL: asrv_i64:625; CHECK: ; %bb.0:626; CHECK-NEXT: asr x0, x0, x1627; CHECK-NEXT: ret628 %1 = ashr i64 %a, %b629 ret i64 %1630}631 632define i64 @asr_i64(i64 %a) {633; CHECK-LABEL: asr_i64:634; CHECK: ; %bb.0:635; CHECK-NEXT: asr x0, x0, #32636; CHECK-NEXT: ret637 %1 = ashr i64 %a, 32638 ret i64 %1639}640 641define i32 @shift_test1(i8 %a) {642; CHECK-LABEL: shift_test1:643; CHECK: ; %bb.0:644; CHECK-NEXT: ubfiz w8, w0, #4, #4645; CHECK-NEXT: sbfx w8, w8, #4, #4646; CHECK-NEXT: sxtb w0, w8647; CHECK-NEXT: ret648 %1 = shl i8 %a, 4649 %2 = ashr i8 %1, 4650 %3 = sext i8 %2 to i32651 ret i32 %3652}653 654; Test zero shifts655 656define i32 @shl_zero(i32 %a) {657; CHECK-LABEL: shl_zero:658; CHECK: ; %bb.0:659; CHECK-NEXT: ret660 %1 = shl i32 %a, 0661 ret i32 %1662}663 664define i32 @lshr_zero(i32 %a) {665; CHECK-LABEL: lshr_zero:666; CHECK: ; %bb.0:667; CHECK-NEXT: ret668 %1 = lshr i32 %a, 0669 ret i32 %1670}671 672define i32 @ashr_zero(i32 %a) {673; CHECK-LABEL: ashr_zero:674; CHECK: ; %bb.0:675; CHECK-NEXT: ret676 %1 = ashr i32 %a, 0677 ret i32 %1678}679 680define i64 @shl_zext_zero(i32 %a) {681; CHECK-LABEL: shl_zext_zero:682; CHECK: ; %bb.0:683; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0684; CHECK-NEXT: lsr w0, w0, #0685; CHECK-NEXT: ret686 %1 = zext i32 %a to i64687 %2 = shl i64 %1, 0688 ret i64 %2689}690 691define i64 @lshr_zext_zero(i32 %a) {692; CHECK-LABEL: lshr_zext_zero:693; CHECK: ; %bb.0:694; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0695; CHECK-NEXT: lsr w0, w0, #0696; CHECK-NEXT: ret697 %1 = zext i32 %a to i64698 %2 = lshr i64 %1, 0699 ret i64 %2700}701 702define i64 @ashr_zext_zero(i32 %a) {703; CHECK-LABEL: ashr_zext_zero:704; CHECK: ; %bb.0:705; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0706; CHECK-NEXT: lsr w0, w0, #0707; CHECK-NEXT: ret708 %1 = zext i32 %a to i64709 %2 = ashr i64 %1, 0710 ret i64 %2711}712 713