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1; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s2; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=2 -verify-machineinstrs < %s | FileCheck %s3 4; Vector Integer Add5define <8 x i8> @add_v8i8_rr(<8 x i8> %a, <8 x i8> %b) {6; CHECK: add_v8i8_rr7; CHECK: add.8b v0, v0, v18 %1 = add <8 x i8> %a, %b9 ret <8 x i8> %110}11 12define <16 x i8> @add_v16i8_rr(<16 x i8> %a, <16 x i8> %b) {13; CHECK: add_v16i8_rr14; CHECK: add.16b v0, v0, v115 %1 = add <16 x i8> %a, %b16 ret <16 x i8> %117}18 19define <4 x i16> @add_v4i16_rr(<4 x i16> %a, <4 x i16> %b) {20; CHECK: add_v4i16_rr21; CHECK: add.4h v0, v0, v122 %1 = add <4 x i16> %a, %b23 ret <4 x i16> %124}25 26define <8 x i16> @add_v8i16_rr(<8 x i16> %a, <8 x i16> %b) {27; CHECK: add_v8i16_rr28; CHECK: add.8h v0, v0, v129 %1 = add <8 x i16> %a, %b30 ret <8 x i16> %131}32 33define <2 x i32> @add_v2i32_rr(<2 x i32> %a, <2 x i32> %b) {34; CHECK: add_v2i32_rr35; CHECK: add.2s v0, v0, v136 %1 = add <2 x i32> %a, %b37 ret <2 x i32> %138}39 40define <4 x i32> @add_v4i32_rr(<4 x i32> %a, <4 x i32> %b) {41; CHECK: add_v4i32_rr42; CHECK: add.4s v0, v0, v143 %1 = add <4 x i32> %a, %b44 ret <4 x i32> %145}46 47define <2 x i64> @add_v2i64_rr(<2 x i64> %a, <2 x i64> %b) {48; CHECK: add_v2i64_rr49; CHECK: add.2d v0, v0, v150 %1 = add <2 x i64> %a, %b51 ret <2 x i64> %152}53 54; Vector Floating-point Add55define <2 x float> @add_v2f32_rr(<2 x float> %a, <2 x float> %b) {56; CHECK: add_v2f32_rr57; CHECK: fadd.2s v0, v0, v158 %1 = fadd <2 x float> %a, %b59 ret <2 x float> %160}61 62define <4 x float> @add_v4f32_rr(<4 x float> %a, <4 x float> %b) {63; CHECK: add_v4f32_rr64; CHECK: fadd.4s v0, v0, v165 %1 = fadd <4 x float> %a, %b66 ret <4 x float> %167}68 69define <2 x double> @add_v2f64_rr(<2 x double> %a, <2 x double> %b) {70; CHECK: add_v2f64_rr71; CHECK: fadd.2d v0, v0, v172 %1 = fadd <2 x double> %a, %b73 ret <2 x double> %174}75