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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-NOFP163; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-SD-FP164; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-NOFP165; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-GI-FP166 7define fp128 @f128_fp128(fp128 %a, fp128 %b, fp128 %d, fp128 %e) {8; CHECK-SD-LABEL: f128_fp128:9; CHECK-SD: // %bb.0: // %entry10; CHECK-SD-NEXT: sub sp, sp, #4811; CHECK-SD-NEXT: str x30, [sp, #32] // 8-byte Spill12; CHECK-SD-NEXT: .cfi_def_cfa_offset 4813; CHECK-SD-NEXT: .cfi_offset w30, -1614; CHECK-SD-NEXT: stp q2, q3, [sp] // 32-byte Folded Spill15; CHECK-SD-NEXT: bl __lttf216; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload17; CHECK-SD-NEXT: cmp w0, #018; CHECK-SD-NEXT: b.pl .LBB0_219; CHECK-SD-NEXT: // %bb.1: // %entry20; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload21; CHECK-SD-NEXT: .LBB0_2: // %entry22; CHECK-SD-NEXT: ldr x30, [sp, #32] // 8-byte Reload23; CHECK-SD-NEXT: add sp, sp, #4824; CHECK-SD-NEXT: ret25;26; CHECK-GI-LABEL: f128_fp128:27; CHECK-GI: // %bb.0: // %entry28; CHECK-GI-NEXT: sub sp, sp, #4829; CHECK-GI-NEXT: str x30, [sp, #32] // 8-byte Spill30; CHECK-GI-NEXT: .cfi_def_cfa_offset 4831; CHECK-GI-NEXT: .cfi_offset w30, -1632; CHECK-GI-NEXT: stp q3, q2, [sp] // 32-byte Folded Spill33; CHECK-GI-NEXT: bl __lttf234; CHECK-GI-NEXT: ldp q3, q2, [sp] // 32-byte Folded Reload35; CHECK-GI-NEXT: cmp w0, #036; CHECK-GI-NEXT: ldr x30, [sp, #32] // 8-byte Reload37; CHECK-GI-NEXT: mov d0, v2.d[1]38; CHECK-GI-NEXT: mov d1, v3.d[1]39; CHECK-GI-NEXT: fcsel d2, d2, d3, mi40; CHECK-GI-NEXT: fmov x8, d241; CHECK-GI-NEXT: fcsel d1, d0, d1, mi42; CHECK-GI-NEXT: mov v0.d[0], x843; CHECK-GI-NEXT: fmov x8, d144; CHECK-GI-NEXT: mov v0.d[1], x845; CHECK-GI-NEXT: add sp, sp, #4846; CHECK-GI-NEXT: ret47entry:48 %c = fcmp olt fp128 %a, %b49 %s = select i1 %c, fp128 %d, fp128 %e50 ret fp128 %s51}52 53define i128 @f128_i128(fp128 %a, fp128 %b, i128 %d, i128 %e) {54; CHECK-SD-LABEL: f128_i128:55; CHECK-SD: // %bb.0: // %entry56; CHECK-SD-NEXT: sub sp, sp, #8057; CHECK-SD-NEXT: str x30, [sp, #32] // 8-byte Spill58; CHECK-SD-NEXT: stp x22, x21, [sp, #48] // 16-byte Folded Spill59; CHECK-SD-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill60; CHECK-SD-NEXT: .cfi_def_cfa_offset 8061; CHECK-SD-NEXT: .cfi_offset w19, -862; CHECK-SD-NEXT: .cfi_offset w20, -1663; CHECK-SD-NEXT: .cfi_offset w21, -2464; CHECK-SD-NEXT: .cfi_offset w22, -3265; CHECK-SD-NEXT: .cfi_offset w30, -4866; CHECK-SD-NEXT: mov x19, x367; CHECK-SD-NEXT: mov x20, x268; CHECK-SD-NEXT: mov x21, x169; CHECK-SD-NEXT: mov x22, x070; CHECK-SD-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill71; CHECK-SD-NEXT: bl __lttf272; CHECK-SD-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload73; CHECK-SD-NEXT: cmp w0, #074; CHECK-SD-NEXT: csel x20, x22, x20, mi75; CHECK-SD-NEXT: bl __lttf276; CHECK-SD-NEXT: mov w8, w077; CHECK-SD-NEXT: mov x0, x2078; CHECK-SD-NEXT: ldr x30, [sp, #32] // 8-byte Reload79; CHECK-SD-NEXT: cmp w8, #080; CHECK-SD-NEXT: csel x1, x21, x19, mi81; CHECK-SD-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload82; CHECK-SD-NEXT: ldp x22, x21, [sp, #48] // 16-byte Folded Reload83; CHECK-SD-NEXT: add sp, sp, #8084; CHECK-SD-NEXT: ret85;86; CHECK-GI-LABEL: f128_i128:87; CHECK-GI: // %bb.0: // %entry88; CHECK-GI-NEXT: str x30, [sp, #-48]! // 8-byte Folded Spill89; CHECK-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill90; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill91; CHECK-GI-NEXT: .cfi_def_cfa_offset 4892; CHECK-GI-NEXT: .cfi_offset w19, -893; CHECK-GI-NEXT: .cfi_offset w20, -1694; CHECK-GI-NEXT: .cfi_offset w21, -2495; CHECK-GI-NEXT: .cfi_offset w22, -3296; CHECK-GI-NEXT: .cfi_offset w30, -4897; CHECK-GI-NEXT: mov x19, x098; CHECK-GI-NEXT: mov x20, x199; CHECK-GI-NEXT: mov x21, x2100; CHECK-GI-NEXT: mov x22, x3101; CHECK-GI-NEXT: bl __lttf2102; CHECK-GI-NEXT: cmp w0, #0103; CHECK-GI-NEXT: csel x0, x19, x21, mi104; CHECK-GI-NEXT: csel x1, x20, x22, mi105; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload106; CHECK-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload107; CHECK-GI-NEXT: ldr x30, [sp], #48 // 8-byte Folded Reload108; CHECK-GI-NEXT: ret109entry:110 %c = fcmp olt fp128 %a, %b111 %s = select i1 %c, i128 %d, i128 %e112 ret i128 %s113}114 115define double @f128_double(fp128 %a, fp128 %b, double %d, double %e) {116; CHECK-SD-LABEL: f128_double:117; CHECK-SD: // %bb.0: // %entry118; CHECK-SD-NEXT: stp d9, d8, [sp, #-32]! // 16-byte Folded Spill119; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Spill120; CHECK-SD-NEXT: .cfi_def_cfa_offset 32121; CHECK-SD-NEXT: .cfi_offset w30, -16122; CHECK-SD-NEXT: .cfi_offset b8, -24123; CHECK-SD-NEXT: .cfi_offset b9, -32124; CHECK-SD-NEXT: fmov d8, d3125; CHECK-SD-NEXT: fmov d9, d2126; CHECK-SD-NEXT: bl __lttf2127; CHECK-SD-NEXT: cmp w0, #0128; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload129; CHECK-SD-NEXT: fcsel d0, d9, d8, mi130; CHECK-SD-NEXT: ldp d9, d8, [sp], #32 // 16-byte Folded Reload131; CHECK-SD-NEXT: ret132;133; CHECK-GI-LABEL: f128_double:134; CHECK-GI: // %bb.0: // %entry135; CHECK-GI-NEXT: stp d9, d8, [sp, #-32]! // 16-byte Folded Spill136; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill137; CHECK-GI-NEXT: .cfi_def_cfa_offset 32138; CHECK-GI-NEXT: .cfi_offset w30, -16139; CHECK-GI-NEXT: .cfi_offset b8, -24140; CHECK-GI-NEXT: .cfi_offset b9, -32141; CHECK-GI-NEXT: fmov d8, d2142; CHECK-GI-NEXT: fmov d9, d3143; CHECK-GI-NEXT: bl __lttf2144; CHECK-GI-NEXT: cmp w0, #0145; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload146; CHECK-GI-NEXT: fcsel d0, d8, d9, mi147; CHECK-GI-NEXT: ldp d9, d8, [sp], #32 // 16-byte Folded Reload148; CHECK-GI-NEXT: ret149entry:150 %c = fcmp olt fp128 %a, %b151 %s = select i1 %c, double %d, double %e152 ret double %s153}154 155define float @f128_float(fp128 %a, fp128 %b, float %d, float %e) {156; CHECK-SD-LABEL: f128_float:157; CHECK-SD: // %bb.0: // %entry158; CHECK-SD-NEXT: stp d9, d8, [sp, #-32]! // 16-byte Folded Spill159; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Spill160; CHECK-SD-NEXT: .cfi_def_cfa_offset 32161; CHECK-SD-NEXT: .cfi_offset w30, -16162; CHECK-SD-NEXT: .cfi_offset b8, -24163; CHECK-SD-NEXT: .cfi_offset b9, -32164; CHECK-SD-NEXT: fmov s8, s3165; CHECK-SD-NEXT: fmov s9, s2166; CHECK-SD-NEXT: bl __lttf2167; CHECK-SD-NEXT: cmp w0, #0168; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload169; CHECK-SD-NEXT: fcsel s0, s9, s8, mi170; CHECK-SD-NEXT: ldp d9, d8, [sp], #32 // 16-byte Folded Reload171; CHECK-SD-NEXT: ret172;173; CHECK-GI-LABEL: f128_float:174; CHECK-GI: // %bb.0: // %entry175; CHECK-GI-NEXT: stp d9, d8, [sp, #-32]! // 16-byte Folded Spill176; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill177; CHECK-GI-NEXT: .cfi_def_cfa_offset 32178; CHECK-GI-NEXT: .cfi_offset w30, -16179; CHECK-GI-NEXT: .cfi_offset b8, -24180; CHECK-GI-NEXT: .cfi_offset b9, -32181; CHECK-GI-NEXT: fmov s8, s2182; CHECK-GI-NEXT: fmov s9, s3183; CHECK-GI-NEXT: bl __lttf2184; CHECK-GI-NEXT: cmp w0, #0185; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload186; CHECK-GI-NEXT: fcsel s0, s8, s9, mi187; CHECK-GI-NEXT: ldp d9, d8, [sp], #32 // 16-byte Folded Reload188; CHECK-GI-NEXT: ret189entry:190 %c = fcmp olt fp128 %a, %b191 %s = select i1 %c, float %d, float %e192 ret float %s193}194 195define i32 @f128_i32(fp128 %a, fp128 %b, i32 %d, i32 %e) {196; CHECK-SD-LABEL: f128_i32:197; CHECK-SD: // %bb.0: // %entry198; CHECK-SD-NEXT: str x30, [sp, #-32]! // 8-byte Folded Spill199; CHECK-SD-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill200; CHECK-SD-NEXT: .cfi_def_cfa_offset 32201; CHECK-SD-NEXT: .cfi_offset w19, -8202; CHECK-SD-NEXT: .cfi_offset w20, -16203; CHECK-SD-NEXT: .cfi_offset w30, -32204; CHECK-SD-NEXT: mov w19, w1205; CHECK-SD-NEXT: mov w20, w0206; CHECK-SD-NEXT: bl __lttf2207; CHECK-SD-NEXT: cmp w0, #0208; CHECK-SD-NEXT: csel w0, w20, w19, mi209; CHECK-SD-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload210; CHECK-SD-NEXT: ldr x30, [sp], #32 // 8-byte Folded Reload211; CHECK-SD-NEXT: ret212;213; CHECK-GI-LABEL: f128_i32:214; CHECK-GI: // %bb.0: // %entry215; CHECK-GI-NEXT: str x30, [sp, #-32]! // 8-byte Folded Spill216; CHECK-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill217; CHECK-GI-NEXT: .cfi_def_cfa_offset 32218; CHECK-GI-NEXT: .cfi_offset w19, -8219; CHECK-GI-NEXT: .cfi_offset w20, -16220; CHECK-GI-NEXT: .cfi_offset w30, -32221; CHECK-GI-NEXT: mov w19, w0222; CHECK-GI-NEXT: mov w20, w1223; CHECK-GI-NEXT: bl __lttf2224; CHECK-GI-NEXT: cmp w0, #0225; CHECK-GI-NEXT: csel w0, w19, w20, mi226; CHECK-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload227; CHECK-GI-NEXT: ldr x30, [sp], #32 // 8-byte Folded Reload228; CHECK-GI-NEXT: ret229entry:230 %c = fcmp olt fp128 %a, %b231 %s = select i1 %c, i32 %d, i32 %e232 ret i32 %s233}234 235define half @f128_half(fp128 %a, fp128 %b, half %d, half %e) {236; CHECK-SD-NOFP16-LABEL: f128_half:237; CHECK-SD-NOFP16: // %bb.0: // %entry238; CHECK-SD-NOFP16-NEXT: stp d9, d8, [sp, #-32]! // 16-byte Folded Spill239; CHECK-SD-NOFP16-NEXT: str x30, [sp, #16] // 8-byte Spill240; CHECK-SD-NOFP16-NEXT: .cfi_def_cfa_offset 32241; CHECK-SD-NOFP16-NEXT: .cfi_offset w30, -16242; CHECK-SD-NOFP16-NEXT: .cfi_offset b8, -24243; CHECK-SD-NOFP16-NEXT: .cfi_offset b9, -32244; CHECK-SD-NOFP16-NEXT: fmov s8, s3245; CHECK-SD-NOFP16-NEXT: fmov s9, s2246; CHECK-SD-NOFP16-NEXT: bl __lttf2247; CHECK-SD-NOFP16-NEXT: cmp w0, #0248; CHECK-SD-NOFP16-NEXT: ldr x30, [sp, #16] // 8-byte Reload249; CHECK-SD-NOFP16-NEXT: fcsel s0, s9, s8, mi250; CHECK-SD-NOFP16-NEXT: // kill: def $h0 killed $h0 killed $s0251; CHECK-SD-NOFP16-NEXT: ldp d9, d8, [sp], #32 // 16-byte Folded Reload252; CHECK-SD-NOFP16-NEXT: ret253;254; CHECK-SD-FP16-LABEL: f128_half:255; CHECK-SD-FP16: // %bb.0: // %entry256; CHECK-SD-FP16-NEXT: stp d9, d8, [sp, #-32]! // 16-byte Folded Spill257; CHECK-SD-FP16-NEXT: str x30, [sp, #16] // 8-byte Spill258; CHECK-SD-FP16-NEXT: .cfi_def_cfa_offset 32259; CHECK-SD-FP16-NEXT: .cfi_offset w30, -16260; CHECK-SD-FP16-NEXT: .cfi_offset b8, -24261; CHECK-SD-FP16-NEXT: .cfi_offset b9, -32262; CHECK-SD-FP16-NEXT: fmov s8, s3263; CHECK-SD-FP16-NEXT: fmov s9, s2264; CHECK-SD-FP16-NEXT: bl __lttf2265; CHECK-SD-FP16-NEXT: cmp w0, #0266; CHECK-SD-FP16-NEXT: ldr x30, [sp, #16] // 8-byte Reload267; CHECK-SD-FP16-NEXT: fcsel h0, h9, h8, mi268; CHECK-SD-FP16-NEXT: ldp d9, d8, [sp], #32 // 16-byte Folded Reload269; CHECK-SD-FP16-NEXT: ret270;271; CHECK-GI-LABEL: f128_half:272; CHECK-GI: // %bb.0: // %entry273; CHECK-GI-NEXT: stp d9, d8, [sp, #-32]! // 16-byte Folded Spill274; CHECK-GI-NEXT: str x30, [sp, #16] // 8-byte Spill275; CHECK-GI-NEXT: .cfi_def_cfa_offset 32276; CHECK-GI-NEXT: .cfi_offset w30, -16277; CHECK-GI-NEXT: .cfi_offset b8, -24278; CHECK-GI-NEXT: .cfi_offset b9, -32279; CHECK-GI-NEXT: fmov s8, s2280; CHECK-GI-NEXT: fmov s9, s3281; CHECK-GI-NEXT: bl __lttf2282; CHECK-GI-NEXT: fmov w8, s8283; CHECK-GI-NEXT: fmov w9, s9284; CHECK-GI-NEXT: cmp w0, #0285; CHECK-GI-NEXT: ldr x30, [sp, #16] // 8-byte Reload286; CHECK-GI-NEXT: csel w8, w8, w9, mi287; CHECK-GI-NEXT: fmov s0, w8288; CHECK-GI-NEXT: // kill: def $h0 killed $h0 killed $s0289; CHECK-GI-NEXT: ldp d9, d8, [sp], #32 // 16-byte Folded Reload290; CHECK-GI-NEXT: ret291entry:292 %c = fcmp olt fp128 %a, %b293 %s = select i1 %c, half %d, half %e294 ret half %s295}296 297define double @f64_double(double %a, double %b, double %d, double %e) {298; CHECK-LABEL: f64_double:299; CHECK: // %bb.0: // %entry300; CHECK-NEXT: fcmp d0, d1301; CHECK-NEXT: fcsel d0, d2, d3, mi302; CHECK-NEXT: ret303entry:304 %c = fcmp olt double %a, %b305 %s = select i1 %c, double %d, double %e306 ret double %s307}308 309define i32 @f64_i32(double %a, double %b, i32 %d, i32 %e) {310; CHECK-LABEL: f64_i32:311; CHECK: // %bb.0: // %entry312; CHECK-NEXT: fcmp d0, d1313; CHECK-NEXT: csel w0, w0, w1, mi314; CHECK-NEXT: ret315entry:316 %c = fcmp olt double %a, %b317 %s = select i1 %c, i32 %d, i32 %e318 ret i32 %s319}320 321define float @f32_float(float %a, float %b, float %d, float %e) {322; CHECK-LABEL: f32_float:323; CHECK: // %bb.0: // %entry324; CHECK-NEXT: fcmp s0, s1325; CHECK-NEXT: fcsel s0, s2, s3, mi326; CHECK-NEXT: ret327entry:328 %c = fcmp olt float %a, %b329 %s = select i1 %c, float %d, float %e330 ret float %s331}332 333define i32 @f32_i32(float %a, float %b, i32 %d, i32 %e) {334; CHECK-LABEL: f32_i32:335; CHECK: // %bb.0: // %entry336; CHECK-NEXT: fcmp s0, s1337; CHECK-NEXT: csel w0, w0, w1, mi338; CHECK-NEXT: ret339entry:340 %c = fcmp olt float %a, %b341 %s = select i1 %c, i32 %d, i32 %e342 ret i32 %s343}344 345define half @f16_half(half %a, half %b, half %d, half %e) {346; CHECK-SD-NOFP16-LABEL: f16_half:347; CHECK-SD-NOFP16: // %bb.0: // %entry348; CHECK-SD-NOFP16-NEXT: fcvt s1, h1349; CHECK-SD-NOFP16-NEXT: fcvt s0, h0350; CHECK-SD-NOFP16-NEXT: // kill: def $h3 killed $h3 def $s3351; CHECK-SD-NOFP16-NEXT: // kill: def $h2 killed $h2 def $s2352; CHECK-SD-NOFP16-NEXT: fcmp s0, s1353; CHECK-SD-NOFP16-NEXT: fcsel s0, s2, s3, mi354; CHECK-SD-NOFP16-NEXT: // kill: def $h0 killed $h0 killed $s0355; CHECK-SD-NOFP16-NEXT: ret356;357; CHECK-SD-FP16-LABEL: f16_half:358; CHECK-SD-FP16: // %bb.0: // %entry359; CHECK-SD-FP16-NEXT: fcmp h0, h1360; CHECK-SD-FP16-NEXT: fcsel h0, h2, h3, mi361; CHECK-SD-FP16-NEXT: ret362;363; CHECK-GI-NOFP16-LABEL: f16_half:364; CHECK-GI-NOFP16: // %bb.0: // %entry365; CHECK-GI-NOFP16-NEXT: fcvt s0, h0366; CHECK-GI-NOFP16-NEXT: fcvt s1, h1367; CHECK-GI-NOFP16-NEXT: // kill: def $h2 killed $h2 def $s2368; CHECK-GI-NOFP16-NEXT: // kill: def $h3 killed $h3 def $s3369; CHECK-GI-NOFP16-NEXT: fmov w8, s2370; CHECK-GI-NOFP16-NEXT: fmov w9, s3371; CHECK-GI-NOFP16-NEXT: fcmp s0, s1372; CHECK-GI-NOFP16-NEXT: csel w8, w8, w9, mi373; CHECK-GI-NOFP16-NEXT: fmov s0, w8374; CHECK-GI-NOFP16-NEXT: // kill: def $h0 killed $h0 killed $s0375; CHECK-GI-NOFP16-NEXT: ret376;377; CHECK-GI-FP16-LABEL: f16_half:378; CHECK-GI-FP16: // %bb.0: // %entry379; CHECK-GI-FP16-NEXT: // kill: def $h2 killed $h2 def $s2380; CHECK-GI-FP16-NEXT: // kill: def $h3 killed $h3 def $s3381; CHECK-GI-FP16-NEXT: fcmp h0, h1382; CHECK-GI-FP16-NEXT: fmov w8, s2383; CHECK-GI-FP16-NEXT: fmov w9, s3384; CHECK-GI-FP16-NEXT: csel w8, w8, w9, mi385; CHECK-GI-FP16-NEXT: fmov s0, w8386; CHECK-GI-FP16-NEXT: // kill: def $h0 killed $h0 killed $s0387; CHECK-GI-FP16-NEXT: ret388entry:389 %c = fcmp olt half %a, %b390 %s = select i1 %c, half %d, half %e391 ret half %s392}393 394define i32 @f16_i32(half %a, half %b, i32 %d, i32 %e) {395; CHECK-SD-NOFP16-LABEL: f16_i32:396; CHECK-SD-NOFP16: // %bb.0: // %entry397; CHECK-SD-NOFP16-NEXT: fcvt s1, h1398; CHECK-SD-NOFP16-NEXT: fcvt s0, h0399; CHECK-SD-NOFP16-NEXT: fcmp s0, s1400; CHECK-SD-NOFP16-NEXT: csel w0, w0, w1, mi401; CHECK-SD-NOFP16-NEXT: ret402;403; CHECK-SD-FP16-LABEL: f16_i32:404; CHECK-SD-FP16: // %bb.0: // %entry405; CHECK-SD-FP16-NEXT: fcmp h0, h1406; CHECK-SD-FP16-NEXT: csel w0, w0, w1, mi407; CHECK-SD-FP16-NEXT: ret408;409; CHECK-GI-NOFP16-LABEL: f16_i32:410; CHECK-GI-NOFP16: // %bb.0: // %entry411; CHECK-GI-NOFP16-NEXT: fcvt s0, h0412; CHECK-GI-NOFP16-NEXT: fcvt s1, h1413; CHECK-GI-NOFP16-NEXT: fcmp s0, s1414; CHECK-GI-NOFP16-NEXT: csel w0, w0, w1, mi415; CHECK-GI-NOFP16-NEXT: ret416;417; CHECK-GI-FP16-LABEL: f16_i32:418; CHECK-GI-FP16: // %bb.0: // %entry419; CHECK-GI-FP16-NEXT: fcmp h0, h1420; CHECK-GI-FP16-NEXT: csel w0, w0, w1, mi421; CHECK-GI-FP16-NEXT: ret422entry:423 %c = fcmp olt half %a, %b424 %s = select i1 %c, i32 %d, i32 %e425 ret i32 %s426}427 428define <2 x fp128> @v2f128_fp128(<2 x fp128> %a, <2 x fp128> %b, <2 x fp128> %d, <2 x fp128> %e) {429; CHECK-SD-LABEL: v2f128_fp128:430; CHECK-SD: // %bb.0: // %entry431; CHECK-SD-NEXT: sub sp, sp, #112432; CHECK-SD-NEXT: str x30, [sp, #96] // 8-byte Spill433; CHECK-SD-NEXT: .cfi_def_cfa_offset 112434; CHECK-SD-NEXT: .cfi_offset w30, -16435; CHECK-SD-NEXT: stp q4, q5, [sp] // 32-byte Folded Spill436; CHECK-SD-NEXT: stp q1, q3, [sp, #32] // 32-byte Folded Spill437; CHECK-SD-NEXT: mov v1.16b, v2.16b438; CHECK-SD-NEXT: stp q7, q6, [sp, #64] // 32-byte Folded Spill439; CHECK-SD-NEXT: bl __lttf2440; CHECK-SD-NEXT: cmp w0, #0441; CHECK-SD-NEXT: b.pl .LBB12_2442; CHECK-SD-NEXT: // %bb.1: // %entry443; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload444; CHECK-SD-NEXT: str q0, [sp, #80] // 16-byte Spill445; CHECK-SD-NEXT: .LBB12_2: // %entry446; CHECK-SD-NEXT: ldp q0, q1, [sp, #32] // 32-byte Folded Reload447; CHECK-SD-NEXT: bl __lttf2448; CHECK-SD-NEXT: ldr q1, [sp, #64] // 16-byte Reload449; CHECK-SD-NEXT: cmp w0, #0450; CHECK-SD-NEXT: b.pl .LBB12_4451; CHECK-SD-NEXT: // %bb.3: // %entry452; CHECK-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload453; CHECK-SD-NEXT: .LBB12_4: // %entry454; CHECK-SD-NEXT: ldr q0, [sp, #80] // 16-byte Reload455; CHECK-SD-NEXT: ldr x30, [sp, #96] // 8-byte Reload456; CHECK-SD-NEXT: add sp, sp, #112457; CHECK-SD-NEXT: ret458;459; CHECK-GI-LABEL: v2f128_fp128:460; CHECK-GI: // %bb.0: // %entry461; CHECK-GI-NEXT: sub sp, sp, #112462; CHECK-GI-NEXT: stp x30, x19, [sp, #96] // 16-byte Folded Spill463; CHECK-GI-NEXT: .cfi_def_cfa_offset 112464; CHECK-GI-NEXT: .cfi_offset w19, -8465; CHECK-GI-NEXT: .cfi_offset w30, -16466; CHECK-GI-NEXT: stp q3, q1, [sp] // 32-byte Folded Spill467; CHECK-GI-NEXT: mov v1.16b, v2.16b468; CHECK-GI-NEXT: stp q6, q4, [sp, #32] // 32-byte Folded Spill469; CHECK-GI-NEXT: stp q7, q5, [sp, #64] // 32-byte Folded Spill470; CHECK-GI-NEXT: bl __lttf2471; CHECK-GI-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload472; CHECK-GI-NEXT: mov w19, w0473; CHECK-GI-NEXT: bl __lttf2474; CHECK-GI-NEXT: ldp q3, q2, [sp, #32] // 32-byte Folded Reload475; CHECK-GI-NEXT: cmp w19, #0476; CHECK-GI-NEXT: ldp x30, x19, [sp, #96] // 16-byte Folded Reload477; CHECK-GI-NEXT: mov d0, v2.d[1]478; CHECK-GI-NEXT: mov d1, v3.d[1]479; CHECK-GI-NEXT: fcsel d2, d2, d3, mi480; CHECK-GI-NEXT: fmov x8, d2481; CHECK-GI-NEXT: fcsel d3, d0, d1, mi482; CHECK-GI-NEXT: ldp q5, q0, [sp, #64] // 32-byte Folded Reload483; CHECK-GI-NEXT: cmp w0, #0484; CHECK-GI-NEXT: mov d1, v0.d[1]485; CHECK-GI-NEXT: mov d4, v5.d[1]486; CHECK-GI-NEXT: fcsel d0, d0, d5, mi487; CHECK-GI-NEXT: fmov x9, d0488; CHECK-GI-NEXT: mov v0.d[0], x8489; CHECK-GI-NEXT: fmov x8, d3490; CHECK-GI-NEXT: fcsel d2, d1, d4, mi491; CHECK-GI-NEXT: mov v1.d[0], x9492; CHECK-GI-NEXT: fmov x9, d2493; CHECK-GI-NEXT: mov v0.d[1], x8494; CHECK-GI-NEXT: mov v1.d[1], x9495; CHECK-GI-NEXT: add sp, sp, #112496; CHECK-GI-NEXT: ret497entry:498 %c = fcmp olt <2 x fp128> %a, %b499 %s = select <2 x i1> %c, <2 x fp128> %d, <2 x fp128> %e500 ret <2 x fp128> %s501}502 503define <3 x fp128> @v3f128_fp128(<3 x fp128> %a, <3 x fp128> %b, <3 x fp128> %d, <3 x fp128> %e) {504; CHECK-SD-LABEL: v3f128_fp128:505; CHECK-SD: // %bb.0: // %entry506; CHECK-SD-NEXT: sub sp, sp, #112507; CHECK-SD-NEXT: str x30, [sp, #96] // 8-byte Spill508; CHECK-SD-NEXT: .cfi_def_cfa_offset 112509; CHECK-SD-NEXT: .cfi_offset w30, -16510; CHECK-SD-NEXT: stp q1, q4, [sp] // 32-byte Folded Spill511; CHECK-SD-NEXT: mov v1.16b, v3.16b512; CHECK-SD-NEXT: stp q2, q5, [sp, #32] // 32-byte Folded Spill513; CHECK-SD-NEXT: stp q6, q7, [sp, #64] // 32-byte Folded Spill514; CHECK-SD-NEXT: bl __lttf2515; CHECK-SD-NEXT: cmp w0, #0516; CHECK-SD-NEXT: b.mi .LBB13_2517; CHECK-SD-NEXT: // %bb.1:518; CHECK-SD-NEXT: ldr q0, [sp, #128]519; CHECK-SD-NEXT: str q0, [sp, #64] // 16-byte Spill520; CHECK-SD-NEXT: .LBB13_2: // %entry521; CHECK-SD-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload522; CHECK-SD-NEXT: bl __lttf2523; CHECK-SD-NEXT: cmp w0, #0524; CHECK-SD-NEXT: b.mi .LBB13_4525; CHECK-SD-NEXT: // %bb.3:526; CHECK-SD-NEXT: ldr q0, [sp, #144]527; CHECK-SD-NEXT: str q0, [sp, #80] // 16-byte Spill528; CHECK-SD-NEXT: .LBB13_4: // %entry529; CHECK-SD-NEXT: ldp q0, q1, [sp, #32] // 32-byte Folded Reload530; CHECK-SD-NEXT: bl __lttf2531; CHECK-SD-NEXT: add x8, sp, #160532; CHECK-SD-NEXT: cmp w0, #0533; CHECK-SD-NEXT: add x9, sp, #112534; CHECK-SD-NEXT: csel x8, x9, x8, mi535; CHECK-SD-NEXT: ldp q0, q1, [sp, #64] // 32-byte Folded Reload536; CHECK-SD-NEXT: ldr q2, [x8]537; CHECK-SD-NEXT: ldr x30, [sp, #96] // 8-byte Reload538; CHECK-SD-NEXT: add sp, sp, #112539; CHECK-SD-NEXT: ret540;541; CHECK-GI-LABEL: v3f128_fp128:542; CHECK-GI: // %bb.0: // %entry543; CHECK-GI-NEXT: sub sp, sp, #192544; CHECK-GI-NEXT: str x30, [sp, #160] // 8-byte Spill545; CHECK-GI-NEXT: stp x20, x19, [sp, #176] // 16-byte Folded Spill546; CHECK-GI-NEXT: .cfi_def_cfa_offset 192547; CHECK-GI-NEXT: .cfi_offset w19, -8548; CHECK-GI-NEXT: .cfi_offset w20, -16549; CHECK-GI-NEXT: .cfi_offset w30, -32550; CHECK-GI-NEXT: stp q4, q1, [sp] // 32-byte Folded Spill551; CHECK-GI-NEXT: mov v1.16b, v3.16b552; CHECK-GI-NEXT: stp q5, q2, [sp, #32] // 32-byte Folded Spill553; CHECK-GI-NEXT: ldr q2, [sp, #192]554; CHECK-GI-NEXT: str q2, [sp, #144] // 16-byte Spill555; CHECK-GI-NEXT: ldr q2, [sp, #208]556; CHECK-GI-NEXT: stp q2, q6, [sp, #64] // 32-byte Folded Spill557; CHECK-GI-NEXT: ldr q2, [sp, #224]558; CHECK-GI-NEXT: stp q7, q2, [sp, #96] // 32-byte Folded Spill559; CHECK-GI-NEXT: ldr q2, [sp, #240]560; CHECK-GI-NEXT: str q2, [sp, #128] // 16-byte Spill561; CHECK-GI-NEXT: bl __lttf2562; CHECK-GI-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload563; CHECK-GI-NEXT: mov w19, w0564; CHECK-GI-NEXT: bl __lttf2565; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload566; CHECK-GI-NEXT: mov w20, w0567; CHECK-GI-NEXT: bl __lttf2568; CHECK-GI-NEXT: ldp q5, q4, [sp, #64] // 32-byte Folded Reload569; CHECK-GI-NEXT: cmp w19, #0570; CHECK-GI-NEXT: ldp q7, q6, [sp, #96] // 32-byte Folded Reload571; CHECK-GI-NEXT: ldr x30, [sp, #160] // 8-byte Reload572; CHECK-GI-NEXT: mov d0, v4.d[1]573; CHECK-GI-NEXT: mov d1, v5.d[1]574; CHECK-GI-NEXT: fcsel d4, d4, d5, mi575; CHECK-GI-NEXT: mov d2, v7.d[1]576; CHECK-GI-NEXT: mov d3, v6.d[1]577; CHECK-GI-NEXT: fmov x8, d4578; CHECK-GI-NEXT: fcsel d5, d0, d1, mi579; CHECK-GI-NEXT: cmp w20, #0580; CHECK-GI-NEXT: fcsel d1, d7, d6, mi581; CHECK-GI-NEXT: ldp q7, q0, [sp, #128] // 32-byte Folded Reload582; CHECK-GI-NEXT: fcsel d3, d2, d3, mi583; CHECK-GI-NEXT: cmp w0, #0584; CHECK-GI-NEXT: ldp x20, x19, [sp, #176] // 16-byte Folded Reload585; CHECK-GI-NEXT: mov d2, v0.d[1]586; CHECK-GI-NEXT: mov d6, v7.d[1]587; CHECK-GI-NEXT: fcsel d7, d0, d7, mi588; CHECK-GI-NEXT: mov v0.d[0], x8589; CHECK-GI-NEXT: fmov x8, d1590; CHECK-GI-NEXT: fmov x9, d7591; CHECK-GI-NEXT: fcsel d4, d2, d6, mi592; CHECK-GI-NEXT: mov v1.d[0], x8593; CHECK-GI-NEXT: fmov x8, d5594; CHECK-GI-NEXT: mov v2.d[0], x9595; CHECK-GI-NEXT: fmov x9, d3596; CHECK-GI-NEXT: fmov x10, d4597; CHECK-GI-NEXT: mov v0.d[1], x8598; CHECK-GI-NEXT: mov v1.d[1], x9599; CHECK-GI-NEXT: mov v2.d[1], x10600; CHECK-GI-NEXT: add sp, sp, #192601; CHECK-GI-NEXT: ret602entry:603 %c = fcmp olt <3 x fp128> %a, %b604 %s = select <3 x i1> %c, <3 x fp128> %d, <3 x fp128> %e605 ret <3 x fp128> %s606}607 608 609define <2 x double> @v2f128_double(<2 x fp128> %a, <2 x fp128> %b, <2 x double> %d, <2 x double> %e) {610; CHECK-SD-LABEL: v2f128_double:611; CHECK-SD: // %bb.0: // %entry612; CHECK-SD-NEXT: sub sp, sp, #96613; CHECK-SD-NEXT: str x30, [sp, #80] // 8-byte Spill614; CHECK-SD-NEXT: .cfi_def_cfa_offset 96615; CHECK-SD-NEXT: .cfi_offset w30, -16616; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill617; CHECK-SD-NEXT: mov v0.16b, v1.16b618; CHECK-SD-NEXT: mov v1.16b, v3.16b619; CHECK-SD-NEXT: stp q4, q5, [sp, #48] // 32-byte Folded Spill620; CHECK-SD-NEXT: str q2, [sp, #32] // 16-byte Spill621; CHECK-SD-NEXT: bl __lttf2622; CHECK-SD-NEXT: cmp w0, #0623; CHECK-SD-NEXT: ldr q1, [sp, #32] // 16-byte Reload624; CHECK-SD-NEXT: cset w8, mi625; CHECK-SD-NEXT: sbfx x8, x8, #0, #1626; CHECK-SD-NEXT: fmov d0, x8627; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Spill628; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload629; CHECK-SD-NEXT: bl __lttf2630; CHECK-SD-NEXT: cmp w0, #0631; CHECK-SD-NEXT: ldr q1, [sp, #16] // 16-byte Reload632; CHECK-SD-NEXT: ldr x30, [sp, #80] // 8-byte Reload633; CHECK-SD-NEXT: cset w8, mi634; CHECK-SD-NEXT: sbfx x8, x8, #0, #1635; CHECK-SD-NEXT: fmov d0, x8636; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]637; CHECK-SD-NEXT: ldp q2, q1, [sp, #48] // 32-byte Folded Reload638; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v1.16b639; CHECK-SD-NEXT: add sp, sp, #96640; CHECK-SD-NEXT: ret641;642; CHECK-GI-LABEL: v2f128_double:643; CHECK-GI: // %bb.0: // %entry644; CHECK-GI-NEXT: sub sp, sp, #80645; CHECK-GI-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill646; CHECK-GI-NEXT: .cfi_def_cfa_offset 80647; CHECK-GI-NEXT: .cfi_offset w19, -8648; CHECK-GI-NEXT: .cfi_offset w30, -16649; CHECK-GI-NEXT: stp q3, q1, [sp] // 32-byte Folded Spill650; CHECK-GI-NEXT: mov v1.16b, v2.16b651; CHECK-GI-NEXT: stp q5, q4, [sp, #32] // 32-byte Folded Spill652; CHECK-GI-NEXT: bl __lttf2653; CHECK-GI-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload654; CHECK-GI-NEXT: cmp w0, #0655; CHECK-GI-NEXT: cset w19, mi656; CHECK-GI-NEXT: bl __lttf2657; CHECK-GI-NEXT: fmov d0, x19658; CHECK-GI-NEXT: cmp w0, #0659; CHECK-GI-NEXT: cset w8, mi660; CHECK-GI-NEXT: ldp q2, q1, [sp, #32] // 32-byte Folded Reload661; CHECK-GI-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload662; CHECK-GI-NEXT: mov v0.d[1], x8663; CHECK-GI-NEXT: shl v0.2d, v0.2d, #63664; CHECK-GI-NEXT: cmlt v0.2d, v0.2d, #0665; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b666; CHECK-GI-NEXT: add sp, sp, #80667; CHECK-GI-NEXT: ret668entry:669 %c = fcmp olt <2 x fp128> %a, %b670 %s = select <2 x i1> %c, <2 x double> %d, <2 x double> %e671 ret <2 x double> %s672}673 674define <3 x double> @v3f128_double(<3 x fp128> %a, <3 x fp128> %b, <3 x double> %d, <3 x double> %e) {675; CHECK-SD-LABEL: v3f128_double:676; CHECK-SD: // %bb.0: // %entry677; CHECK-SD-NEXT: sub sp, sp, #160678; CHECK-SD-NEXT: str x30, [sp, #144] // 8-byte Spill679; CHECK-SD-NEXT: .cfi_def_cfa_offset 160680; CHECK-SD-NEXT: .cfi_offset w30, -16681; CHECK-SD-NEXT: stp q2, q5, [sp, #112] // 32-byte Folded Spill682; CHECK-SD-NEXT: // kill: def $d6 killed $d6 def $q6683; CHECK-SD-NEXT: // kill: def $d7 killed $d7 def $q7684; CHECK-SD-NEXT: ldr d5, [sp, #184]685; CHECK-SD-NEXT: str q3, [sp, #64] // 16-byte Spill686; CHECK-SD-NEXT: ldp d3, d2, [sp, #168]687; CHECK-SD-NEXT: mov v6.d[1], v7.d[0]688; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Spill689; CHECK-SD-NEXT: mov v0.16b, v1.16b690; CHECK-SD-NEXT: mov v1.16b, v4.16b691; CHECK-SD-NEXT: str q5, [sp, #96] // 16-byte Spill692; CHECK-SD-NEXT: ldr d5, [sp, #160]693; CHECK-SD-NEXT: mov v3.d[1], v2.d[0]694; CHECK-SD-NEXT: str q5, [sp, #80] // 16-byte Spill695; CHECK-SD-NEXT: stp q6, q3, [sp, #32] // 32-byte Folded Spill696; CHECK-SD-NEXT: bl __lttf2697; CHECK-SD-NEXT: cmp w0, #0698; CHECK-SD-NEXT: ldr q1, [sp, #64] // 16-byte Reload699; CHECK-SD-NEXT: cset w8, mi700; CHECK-SD-NEXT: sbfx x8, x8, #0, #1701; CHECK-SD-NEXT: fmov d0, x8702; CHECK-SD-NEXT: str q0, [sp] // 16-byte Spill703; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Reload704; CHECK-SD-NEXT: bl __lttf2705; CHECK-SD-NEXT: cmp w0, #0706; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Reload707; CHECK-SD-NEXT: cset w8, mi708; CHECK-SD-NEXT: sbfx x8, x8, #0, #1709; CHECK-SD-NEXT: fmov d1, x8710; CHECK-SD-NEXT: mov v1.d[1], v0.d[0]711; CHECK-SD-NEXT: str q1, [sp, #64] // 16-byte Spill712; CHECK-SD-NEXT: ldp q0, q1, [sp, #112] // 32-byte Folded Reload713; CHECK-SD-NEXT: bl __lttf2714; CHECK-SD-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload715; CHECK-SD-NEXT: cmp w0, #0716; CHECK-SD-NEXT: ldp q2, q4, [sp, #64] // 32-byte Folded Reload717; CHECK-SD-NEXT: cset w8, mi718; CHECK-SD-NEXT: sbfx x8, x8, #0, #1719; CHECK-SD-NEXT: ldr q3, [sp, #96] // 16-byte Reload720; CHECK-SD-NEXT: ldr x30, [sp, #144] // 8-byte Reload721; CHECK-SD-NEXT: bit v0.16b, v1.16b, v2.16b722; CHECK-SD-NEXT: fmov d2, x8723; CHECK-SD-NEXT: bsl v2.16b, v4.16b, v3.16b724; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8725; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0726; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2727; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1728; CHECK-SD-NEXT: add sp, sp, #160729; CHECK-SD-NEXT: ret730;731; CHECK-GI-LABEL: v3f128_double:732; CHECK-GI: // %bb.0: // %entry733; CHECK-GI-NEXT: sub sp, sp, #176734; CHECK-GI-NEXT: str x30, [sp, #128] // 8-byte Spill735; CHECK-GI-NEXT: stp x22, x21, [sp, #144] // 16-byte Folded Spill736; CHECK-GI-NEXT: stp x20, x19, [sp, #160] // 16-byte Folded Spill737; CHECK-GI-NEXT: .cfi_def_cfa_offset 176738; CHECK-GI-NEXT: .cfi_offset w19, -8739; CHECK-GI-NEXT: .cfi_offset w20, -16740; CHECK-GI-NEXT: .cfi_offset w21, -24741; CHECK-GI-NEXT: .cfi_offset w22, -32742; CHECK-GI-NEXT: .cfi_offset w30, -48743; CHECK-GI-NEXT: stp q4, q1, [sp] // 32-byte Folded Spill744; CHECK-GI-NEXT: mov v1.16b, v3.16b745; CHECK-GI-NEXT: ldr x19, [sp, #176]746; CHECK-GI-NEXT: stp q5, q2, [sp, #32] // 32-byte Folded Spill747; CHECK-GI-NEXT: ldr d2, [sp, #184]748; CHECK-GI-NEXT: ldr x20, [sp, #200]749; CHECK-GI-NEXT: // kill: def $d6 killed $d6 def $q6750; CHECK-GI-NEXT: // kill: def $d7 killed $d7 def $q7751; CHECK-GI-NEXT: str q7, [sp, #64] // 16-byte Spill752; CHECK-GI-NEXT: str q2, [sp, #112] // 16-byte Spill753; CHECK-GI-NEXT: ldr d2, [sp, #192]754; CHECK-GI-NEXT: stp q6, q2, [sp, #80] // 32-byte Folded Spill755; CHECK-GI-NEXT: bl __lttf2756; CHECK-GI-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload757; CHECK-GI-NEXT: cmp w0, #0758; CHECK-GI-NEXT: cset w21, mi759; CHECK-GI-NEXT: bl __lttf2760; CHECK-GI-NEXT: ldp q1, q0, [sp, #32] // 32-byte Folded Reload761; CHECK-GI-NEXT: cmp w0, #0762; CHECK-GI-NEXT: cset w22, mi763; CHECK-GI-NEXT: bl __lttf2764; CHECK-GI-NEXT: ldp q0, q2, [sp, #64] // 32-byte Folded Reload765; CHECK-GI-NEXT: sbfx x8, x21, #0, #1766; CHECK-GI-NEXT: ldp q4, q3, [sp, #96] // 32-byte Folded Reload767; CHECK-GI-NEXT: sbfx x9, x22, #0, #1768; CHECK-GI-NEXT: fmov d1, x8769; CHECK-GI-NEXT: cmp w0, #0770; CHECK-GI-NEXT: ldr x30, [sp, #128] // 8-byte Reload771; CHECK-GI-NEXT: mov v2.d[1], v0.d[0]772; CHECK-GI-NEXT: fmov d0, x8773; CHECK-GI-NEXT: cset w8, mi774; CHECK-GI-NEXT: mov v3.d[1], v4.d[0]775; CHECK-GI-NEXT: sbfx x8, x8, #0, #1776; CHECK-GI-NEXT: mov v1.d[1], x9777; CHECK-GI-NEXT: ldp x22, x21, [sp, #144] // 16-byte Folded Reload778; CHECK-GI-NEXT: mov v0.d[1], x9779; CHECK-GI-NEXT: and x9, x19, x8780; CHECK-GI-NEXT: bic x8, x20, x8781; CHECK-GI-NEXT: ldp x20, x19, [sp, #160] // 16-byte Folded Reload782; CHECK-GI-NEXT: orr x8, x9, x8783; CHECK-GI-NEXT: bic v1.16b, v3.16b, v1.16b784; CHECK-GI-NEXT: and v0.16b, v2.16b, v0.16b785; CHECK-GI-NEXT: fmov d2, x8786; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b787; CHECK-GI-NEXT: mov d1, v0.d[1]788; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0789; CHECK-GI-NEXT: add sp, sp, #176790; CHECK-GI-NEXT: ret791entry:792 %c = fcmp olt <3 x fp128> %a, %b793 %s = select <3 x i1> %c, <3 x double> %d, <3 x double> %e794 ret <3 x double> %s795}796 797define <2 x double> @v2f64_double(<2 x double> %a, <2 x double> %b, <2 x double> %d, <2 x double> %e) {798; CHECK-LABEL: v2f64_double:799; CHECK: // %bb.0: // %entry800; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d801; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b802; CHECK-NEXT: ret803entry:804 %c = fcmp olt <2 x double> %a, %b805 %s = select <2 x i1> %c, <2 x double> %d, <2 x double> %e806 ret <2 x double> %s807}808 809define <3 x double> @v3f64_double(<3 x double> %a, <3 x double> %b, <3 x double> %d, <3 x double> %e) {810; CHECK-SD-LABEL: v3f64_double:811; CHECK-SD: // %bb.0: // %entry812; CHECK-SD-NEXT: // kill: def $d3 killed $d3 def $q3813; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0814; CHECK-SD-NEXT: // kill: def $d4 killed $d4 def $q4815; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1816; CHECK-SD-NEXT: // kill: def $d6 killed $d6 def $q6817; CHECK-SD-NEXT: // kill: def $d7 killed $d7 def $q7818; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2819; CHECK-SD-NEXT: // kill: def $d5 killed $d5 def $q5820; CHECK-SD-NEXT: ldr d16, [sp, #24]821; CHECK-SD-NEXT: ldr d17, [sp]822; CHECK-SD-NEXT: mov v3.d[1], v4.d[0]823; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]824; CHECK-SD-NEXT: mov v6.d[1], v7.d[0]825; CHECK-SD-NEXT: ldp d1, d4, [sp, #8]826; CHECK-SD-NEXT: fcmgt v2.2d, v5.2d, v2.2d827; CHECK-SD-NEXT: mov v1.d[1], v4.d[0]828; CHECK-SD-NEXT: fcmgt v0.2d, v3.2d, v0.2d829; CHECK-SD-NEXT: bsl v2.16b, v17.16b, v16.16b830; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2831; CHECK-SD-NEXT: bsl v0.16b, v6.16b, v1.16b832; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8833; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0834; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1835; CHECK-SD-NEXT: ret836;837; CHECK-GI-LABEL: v3f64_double:838; CHECK-GI: // %bb.0: // %entry839; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0840; CHECK-GI-NEXT: // kill: def $d3 killed $d3 def $q3841; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1842; CHECK-GI-NEXT: // kill: def $d4 killed $d4 def $q4843; CHECK-GI-NEXT: // kill: def $d6 killed $d6 def $q6844; CHECK-GI-NEXT: // kill: def $d7 killed $d7 def $q7845; CHECK-GI-NEXT: fcmp d2, d5846; CHECK-GI-NEXT: ldr x8, [sp]847; CHECK-GI-NEXT: ldr x10, [sp, #24]848; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]849; CHECK-GI-NEXT: mov v3.d[1], v4.d[0]850; CHECK-GI-NEXT: mov v6.d[1], v7.d[0]851; CHECK-GI-NEXT: ldp d1, d4, [sp, #8]852; CHECK-GI-NEXT: cset w9, mi853; CHECK-GI-NEXT: sbfx x9, x9, #0, #1854; CHECK-GI-NEXT: fcmgt v0.2d, v3.2d, v0.2d855; CHECK-GI-NEXT: mov v1.d[1], v4.d[0]856; CHECK-GI-NEXT: and x8, x8, x9857; CHECK-GI-NEXT: bic x9, x10, x9858; CHECK-GI-NEXT: orr x8, x8, x9859; CHECK-GI-NEXT: fmov d2, x8860; CHECK-GI-NEXT: bsl v0.16b, v6.16b, v1.16b861; CHECK-GI-NEXT: mov d1, v0.d[1]862; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0863; CHECK-GI-NEXT: ret864entry:865 %c = fcmp olt <3 x double> %a, %b866 %s = select <3 x i1> %c, <3 x double> %d, <3 x double> %e867 ret <3 x double> %s868}869 870define <4 x double> @v4f64_double(<4 x double> %a, <4 x double> %b, <4 x double> %d, <4 x double> %e) {871; CHECK-SD-LABEL: v4f64_double:872; CHECK-SD: // %bb.0: // %entry873; CHECK-SD-NEXT: fcmgt v1.2d, v3.2d, v1.2d874; CHECK-SD-NEXT: fcmgt v0.2d, v2.2d, v0.2d875; CHECK-SD-NEXT: bsl v1.16b, v5.16b, v7.16b876; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v6.16b877; CHECK-SD-NEXT: ret878;879; CHECK-GI-LABEL: v4f64_double:880; CHECK-GI: // %bb.0: // %entry881; CHECK-GI-NEXT: fcmgt v0.2d, v2.2d, v0.2d882; CHECK-GI-NEXT: fcmgt v1.2d, v3.2d, v1.2d883; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v6.16b884; CHECK-GI-NEXT: bsl v1.16b, v5.16b, v7.16b885; CHECK-GI-NEXT: ret886entry:887 %c = fcmp olt <4 x double> %a, %b888 %s = select <4 x i1> %c, <4 x double> %d, <4 x double> %e889 ret <4 x double> %s890}891 892define <2 x i32> @v2f64_i32(<2 x double> %a, <2 x double> %b, <2 x i32> %d, <2 x i32> %e) {893; CHECK-LABEL: v2f64_i32:894; CHECK: // %bb.0: // %entry895; CHECK-NEXT: fcmgt v0.2d, v1.2d, v0.2d896; CHECK-NEXT: xtn v0.2s, v0.2d897; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b898; CHECK-NEXT: ret899entry:900 %c = fcmp olt <2 x double> %a, %b901 %s = select <2 x i1> %c, <2 x i32> %d, <2 x i32> %e902 ret <2 x i32> %s903}904 905define <3 x i32> @v3f64_i32(<3 x double> %a, <3 x double> %b, <3 x i32> %d, <3 x i32> %e) {906; CHECK-SD-LABEL: v3f64_i32:907; CHECK-SD: // %bb.0: // %entry908; CHECK-SD-NEXT: // kill: def $d3 killed $d3 def $q3909; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0910; CHECK-SD-NEXT: // kill: def $d4 killed $d4 def $q4911; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1912; CHECK-SD-NEXT: // kill: def $d5 killed $d5 def $q5913; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2914; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]915; CHECK-SD-NEXT: mov v3.d[1], v4.d[0]916; CHECK-SD-NEXT: fcmgt v1.2d, v5.2d, v2.2d917; CHECK-SD-NEXT: fcmgt v0.2d, v3.2d, v0.2d918; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s919; CHECK-SD-NEXT: bsl v0.16b, v6.16b, v7.16b920; CHECK-SD-NEXT: ret921;922; CHECK-GI-LABEL: v3f64_i32:923; CHECK-GI: // %bb.0: // %entry924; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0925; CHECK-GI-NEXT: // kill: def $d3 killed $d3 def $q3926; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1927; CHECK-GI-NEXT: // kill: def $d4 killed $d4 def $q4928; CHECK-GI-NEXT: mov w8, #31 // =0x1f929; CHECK-GI-NEXT: fcmp d2, d5930; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]931; CHECK-GI-NEXT: mov v3.d[1], v4.d[0]932; CHECK-GI-NEXT: fmov s1, w8933; CHECK-GI-NEXT: cset w9, mi934; CHECK-GI-NEXT: mov v1.s[1], w8935; CHECK-GI-NEXT: fmov s2, w9936; CHECK-GI-NEXT: fcmgt v0.2d, v3.2d, v0.2d937; CHECK-GI-NEXT: mov v1.s[2], w8938; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff939; CHECK-GI-NEXT: xtn v0.2s, v0.2d940; CHECK-GI-NEXT: mov v0.d[1], v2.d[0]941; CHECK-GI-NEXT: fmov s2, w8942; CHECK-GI-NEXT: mov v2.s[1], w8943; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v1.4s944; CHECK-GI-NEXT: neg v1.4s, v1.4s945; CHECK-GI-NEXT: mov v2.s[2], w8946; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v1.4s947; CHECK-GI-NEXT: eor v1.16b, v0.16b, v2.16b948; CHECK-GI-NEXT: and v0.16b, v6.16b, v0.16b949; CHECK-GI-NEXT: and v1.16b, v7.16b, v1.16b950; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b951; CHECK-GI-NEXT: ret952entry:953 %c = fcmp olt <3 x double> %a, %b954 %s = select <3 x i1> %c, <3 x i32> %d, <3 x i32> %e955 ret <3 x i32> %s956}957 958define <4 x i32> @v4f64_i32(<4 x double> %a, <4 x double> %b, <4 x i32> %d, <4 x i32> %e) {959; CHECK-SD-LABEL: v4f64_i32:960; CHECK-SD: // %bb.0: // %entry961; CHECK-SD-NEXT: fcmgt v1.2d, v3.2d, v1.2d962; CHECK-SD-NEXT: fcmgt v0.2d, v2.2d, v0.2d963; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s964; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v5.16b965; CHECK-SD-NEXT: ret966;967; CHECK-GI-LABEL: v4f64_i32:968; CHECK-GI: // %bb.0: // %entry969; CHECK-GI-NEXT: fcmgt v0.2d, v2.2d, v0.2d970; CHECK-GI-NEXT: fcmgt v1.2d, v3.2d, v1.2d971; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s972; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v5.16b973; CHECK-GI-NEXT: ret974entry:975 %c = fcmp olt <4 x double> %a, %b976 %s = select <4 x i1> %c, <4 x i32> %d, <4 x i32> %e977 ret <4 x i32> %s978}979 980define <2 x float> @v2f32_float(<2 x float> %a, <2 x float> %b, <2 x float> %d, <2 x float> %e) {981; CHECK-LABEL: v2f32_float:982; CHECK: // %bb.0: // %entry983; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s984; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b985; CHECK-NEXT: ret986entry:987 %c = fcmp olt <2 x float> %a, %b988 %s = select <2 x i1> %c, <2 x float> %d, <2 x float> %e989 ret <2 x float> %s990}991 992define <3 x float> @v3f32_float(<3 x float> %a, <3 x float> %b, <3 x float> %d, <3 x float> %e) {993; CHECK-SD-LABEL: v3f32_float:994; CHECK-SD: // %bb.0: // %entry995; CHECK-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s996; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b997; CHECK-SD-NEXT: ret998;999; CHECK-GI-LABEL: v3f32_float:1000; CHECK-GI: // %bb.0: // %entry1001; CHECK-GI-NEXT: mov w8, #31 // =0x1f1002; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s1003; CHECK-GI-NEXT: fmov s4, w81004; CHECK-GI-NEXT: mov v4.s[1], w81005; CHECK-GI-NEXT: mov v4.s[2], w81006; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff1007; CHECK-GI-NEXT: fmov s1, w81008; CHECK-GI-NEXT: mov v1.s[1], w81009; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v4.4s1010; CHECK-GI-NEXT: neg v4.4s, v4.4s1011; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v4.4s1012; CHECK-GI-NEXT: mov v1.s[2], w81013; CHECK-GI-NEXT: eor v1.16b, v0.16b, v1.16b1014; CHECK-GI-NEXT: and v0.16b, v2.16b, v0.16b1015; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b1016; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b1017; CHECK-GI-NEXT: ret1018entry:1019 %c = fcmp olt <3 x float> %a, %b1020 %s = select <3 x i1> %c, <3 x float> %d, <3 x float> %e1021 ret <3 x float> %s1022}1023 1024define <4 x float> @v4f32_float(<4 x float> %a, <4 x float> %b, <4 x float> %d, <4 x float> %e) {1025; CHECK-LABEL: v4f32_float:1026; CHECK: // %bb.0: // %entry1027; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s1028; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b1029; CHECK-NEXT: ret1030entry:1031 %c = fcmp olt <4 x float> %a, %b1032 %s = select <4 x i1> %c, <4 x float> %d, <4 x float> %e1033 ret <4 x float> %s1034}1035 1036define <8 x float> @v8f32_float(<8 x float> %a, <8 x float> %b, <8 x float> %d, <8 x float> %e) {1037; CHECK-SD-LABEL: v8f32_float:1038; CHECK-SD: // %bb.0: // %entry1039; CHECK-SD-NEXT: fcmgt v1.4s, v3.4s, v1.4s1040; CHECK-SD-NEXT: fcmgt v0.4s, v2.4s, v0.4s1041; CHECK-SD-NEXT: bsl v1.16b, v5.16b, v7.16b1042; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v6.16b1043; CHECK-SD-NEXT: ret1044;1045; CHECK-GI-LABEL: v8f32_float:1046; CHECK-GI: // %bb.0: // %entry1047; CHECK-GI-NEXT: fcmgt v0.4s, v2.4s, v0.4s1048; CHECK-GI-NEXT: fcmgt v1.4s, v3.4s, v1.4s1049; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v6.16b1050; CHECK-GI-NEXT: bsl v1.16b, v5.16b, v7.16b1051; CHECK-GI-NEXT: ret1052entry:1053 %c = fcmp olt <8 x float> %a, %b1054 %s = select <8 x i1> %c, <8 x float> %d, <8 x float> %e1055 ret <8 x float> %s1056}1057 1058define <2 x i32> @v2f32_i32(<2 x float> %a, <2 x float> %b, <2 x i32> %d, <2 x i32> %e) {1059; CHECK-LABEL: v2f32_i32:1060; CHECK: // %bb.0: // %entry1061; CHECK-NEXT: fcmgt v0.2s, v1.2s, v0.2s1062; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b1063; CHECK-NEXT: ret1064entry:1065 %c = fcmp olt <2 x float> %a, %b1066 %s = select <2 x i1> %c, <2 x i32> %d, <2 x i32> %e1067 ret <2 x i32> %s1068}1069 1070define <3 x i32> @v3f32_i32(<3 x float> %a, <3 x float> %b, <3 x i32> %d, <3 x i32> %e) {1071; CHECK-SD-LABEL: v3f32_i32:1072; CHECK-SD: // %bb.0: // %entry1073; CHECK-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s1074; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b1075; CHECK-SD-NEXT: ret1076;1077; CHECK-GI-LABEL: v3f32_i32:1078; CHECK-GI: // %bb.0: // %entry1079; CHECK-GI-NEXT: mov w8, #31 // =0x1f1080; CHECK-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s1081; CHECK-GI-NEXT: fmov s4, w81082; CHECK-GI-NEXT: mov v4.s[1], w81083; CHECK-GI-NEXT: mov v4.s[2], w81084; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff1085; CHECK-GI-NEXT: fmov s1, w81086; CHECK-GI-NEXT: mov v1.s[1], w81087; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v4.4s1088; CHECK-GI-NEXT: neg v4.4s, v4.4s1089; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v4.4s1090; CHECK-GI-NEXT: mov v1.s[2], w81091; CHECK-GI-NEXT: eor v1.16b, v0.16b, v1.16b1092; CHECK-GI-NEXT: and v0.16b, v2.16b, v0.16b1093; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b1094; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b1095; CHECK-GI-NEXT: ret1096entry:1097 %c = fcmp olt <3 x float> %a, %b1098 %s = select <3 x i1> %c, <3 x i32> %d, <3 x i32> %e1099 ret <3 x i32> %s1100}1101 1102define <4 x i32> @v4f32_i32(<4 x float> %a, <4 x float> %b, <4 x i32> %d, <4 x i32> %e) {1103; CHECK-LABEL: v4f32_i32:1104; CHECK: // %bb.0: // %entry1105; CHECK-NEXT: fcmgt v0.4s, v1.4s, v0.4s1106; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b1107; CHECK-NEXT: ret1108entry:1109 %c = fcmp olt <4 x float> %a, %b1110 %s = select <4 x i1> %c, <4 x i32> %d, <4 x i32> %e1111 ret <4 x i32> %s1112}1113 1114define <8 x i32> @v8f32_i32(<8 x float> %a, <8 x float> %b, <8 x i32> %d, <8 x i32> %e) {1115; CHECK-SD-LABEL: v8f32_i32:1116; CHECK-SD: // %bb.0: // %entry1117; CHECK-SD-NEXT: fcmgt v1.4s, v3.4s, v1.4s1118; CHECK-SD-NEXT: fcmgt v0.4s, v2.4s, v0.4s1119; CHECK-SD-NEXT: bsl v1.16b, v5.16b, v7.16b1120; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v6.16b1121; CHECK-SD-NEXT: ret1122;1123; CHECK-GI-LABEL: v8f32_i32:1124; CHECK-GI: // %bb.0: // %entry1125; CHECK-GI-NEXT: fcmgt v0.4s, v2.4s, v0.4s1126; CHECK-GI-NEXT: fcmgt v1.4s, v3.4s, v1.4s1127; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v6.16b1128; CHECK-GI-NEXT: bsl v1.16b, v5.16b, v7.16b1129; CHECK-GI-NEXT: ret1130entry:1131 %c = fcmp olt <8 x float> %a, %b1132 %s = select <8 x i1> %c, <8 x i32> %d, <8 x i32> %e1133 ret <8 x i32> %s1134}1135 1136define <7 x half> @v7f16_half(<7 x half> %a, <7 x half> %b, <7 x half> %d, <7 x half> %e) {1137; CHECK-SD-NOFP16-LABEL: v7f16_half:1138; CHECK-SD-NOFP16: // %bb.0: // %entry1139; CHECK-SD-NOFP16-NEXT: fcvtl2 v4.4s, v0.8h1140; CHECK-SD-NOFP16-NEXT: fcvtl2 v5.4s, v1.8h1141; CHECK-SD-NOFP16-NEXT: fcvtl v0.4s, v0.4h1142; CHECK-SD-NOFP16-NEXT: fcvtl v1.4s, v1.4h1143; CHECK-SD-NOFP16-NEXT: fcmgt v4.4s, v5.4s, v4.4s1144; CHECK-SD-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s1145; CHECK-SD-NOFP16-NEXT: uzp1 v0.8h, v0.8h, v4.8h1146; CHECK-SD-NOFP16-NEXT: bsl v0.16b, v2.16b, v3.16b1147; CHECK-SD-NOFP16-NEXT: ret1148;1149; CHECK-SD-FP16-LABEL: v7f16_half:1150; CHECK-SD-FP16: // %bb.0: // %entry1151; CHECK-SD-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h1152; CHECK-SD-FP16-NEXT: bsl v0.16b, v2.16b, v3.16b1153; CHECK-SD-FP16-NEXT: ret1154;1155; CHECK-GI-NOFP16-LABEL: v7f16_half:1156; CHECK-GI-NOFP16: // %bb.0: // %entry1157; CHECK-GI-NOFP16-NEXT: mov w8, #15 // =0xf1158; CHECK-GI-NOFP16-NEXT: mov v4.h[0], v0.h[4]1159; CHECK-GI-NOFP16-NEXT: mov v6.h[0], v1.h[4]1160; CHECK-GI-NOFP16-NEXT: fmov s5, w81161; CHECK-GI-NOFP16-NEXT: mov w9, #65535 // =0xffff1162; CHECK-GI-NOFP16-NEXT: fmov s7, w91163; CHECK-GI-NOFP16-NEXT: mov v5.h[1], w81164; CHECK-GI-NOFP16-NEXT: mov v4.h[1], v0.h[5]1165; CHECK-GI-NOFP16-NEXT: mov v6.h[1], v1.h[5]1166; CHECK-GI-NOFP16-NEXT: mov v7.h[1], w91167; CHECK-GI-NOFP16-NEXT: mov v5.h[2], w81168; CHECK-GI-NOFP16-NEXT: mov v4.h[2], v0.h[6]1169; CHECK-GI-NOFP16-NEXT: mov v6.h[2], v1.h[6]1170; CHECK-GI-NOFP16-NEXT: mov v7.h[2], w91171; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h1172; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h1173; CHECK-GI-NOFP16-NEXT: mov v5.h[3], w81174; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v4.4h1175; CHECK-GI-NOFP16-NEXT: fcvtl v6.4s, v6.4h1176; CHECK-GI-NOFP16-NEXT: mov v7.h[3], w91177; CHECK-GI-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s1178; CHECK-GI-NOFP16-NEXT: mov v5.h[4], w81179; CHECK-GI-NOFP16-NEXT: fcmgt v1.4s, v6.4s, v4.4s1180; CHECK-GI-NOFP16-NEXT: mov v7.h[4], w91181; CHECK-GI-NOFP16-NEXT: mov v5.h[5], w81182; CHECK-GI-NOFP16-NEXT: uzp1 v0.8h, v0.8h, v1.8h1183; CHECK-GI-NOFP16-NEXT: mov v7.h[5], w91184; CHECK-GI-NOFP16-NEXT: mov v5.h[6], w81185; CHECK-GI-NOFP16-NEXT: mov v7.h[6], w91186; CHECK-GI-NOFP16-NEXT: ushl v0.8h, v0.8h, v5.8h1187; CHECK-GI-NOFP16-NEXT: neg v1.8h, v5.8h1188; CHECK-GI-NOFP16-NEXT: sshl v0.8h, v0.8h, v1.8h1189; CHECK-GI-NOFP16-NEXT: eor v1.16b, v0.16b, v7.16b1190; CHECK-GI-NOFP16-NEXT: and v0.16b, v2.16b, v0.16b1191; CHECK-GI-NOFP16-NEXT: and v1.16b, v3.16b, v1.16b1192; CHECK-GI-NOFP16-NEXT: orr v0.16b, v0.16b, v1.16b1193; CHECK-GI-NOFP16-NEXT: ret1194;1195; CHECK-GI-FP16-LABEL: v7f16_half:1196; CHECK-GI-FP16: // %bb.0: // %entry1197; CHECK-GI-FP16-NEXT: mov w8, #15 // =0xf1198; CHECK-GI-FP16-NEXT: mov w9, #65535 // =0xffff1199; CHECK-GI-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h1200; CHECK-GI-FP16-NEXT: fmov s4, w81201; CHECK-GI-FP16-NEXT: fmov s5, w91202; CHECK-GI-FP16-NEXT: mov v4.h[1], w81203; CHECK-GI-FP16-NEXT: mov v5.h[1], w91204; CHECK-GI-FP16-NEXT: mov v4.h[2], w81205; CHECK-GI-FP16-NEXT: mov v5.h[2], w91206; CHECK-GI-FP16-NEXT: mov v4.h[3], w81207; CHECK-GI-FP16-NEXT: mov v5.h[3], w91208; CHECK-GI-FP16-NEXT: mov v4.h[4], w81209; CHECK-GI-FP16-NEXT: mov v5.h[4], w91210; CHECK-GI-FP16-NEXT: mov v4.h[5], w81211; CHECK-GI-FP16-NEXT: mov v5.h[5], w91212; CHECK-GI-FP16-NEXT: mov v4.h[6], w81213; CHECK-GI-FP16-NEXT: mov v5.h[6], w91214; CHECK-GI-FP16-NEXT: ushl v0.8h, v0.8h, v4.8h1215; CHECK-GI-FP16-NEXT: neg v1.8h, v4.8h1216; CHECK-GI-FP16-NEXT: sshl v0.8h, v0.8h, v1.8h1217; CHECK-GI-FP16-NEXT: eor v1.16b, v0.16b, v5.16b1218; CHECK-GI-FP16-NEXT: and v0.16b, v2.16b, v0.16b1219; CHECK-GI-FP16-NEXT: and v1.16b, v3.16b, v1.16b1220; CHECK-GI-FP16-NEXT: orr v0.16b, v0.16b, v1.16b1221; CHECK-GI-FP16-NEXT: ret1222entry:1223 %c = fcmp olt <7 x half> %a, %b1224 %s = select <7 x i1> %c, <7 x half> %d, <7 x half> %e1225 ret <7 x half> %s1226}1227 1228define <4 x half> @v4f16_half(<4 x half> %a, <4 x half> %b, <4 x half> %d, <4 x half> %e) {1229; CHECK-SD-NOFP16-LABEL: v4f16_half:1230; CHECK-SD-NOFP16: // %bb.0: // %entry1231; CHECK-SD-NOFP16-NEXT: fcvtl v0.4s, v0.4h1232; CHECK-SD-NOFP16-NEXT: fcvtl v1.4s, v1.4h1233; CHECK-SD-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s1234; CHECK-SD-NOFP16-NEXT: xtn v0.4h, v0.4s1235; CHECK-SD-NOFP16-NEXT: bsl v0.8b, v2.8b, v3.8b1236; CHECK-SD-NOFP16-NEXT: ret1237;1238; CHECK-SD-FP16-LABEL: v4f16_half:1239; CHECK-SD-FP16: // %bb.0: // %entry1240; CHECK-SD-FP16-NEXT: fcmgt v0.4h, v1.4h, v0.4h1241; CHECK-SD-FP16-NEXT: bsl v0.8b, v2.8b, v3.8b1242; CHECK-SD-FP16-NEXT: ret1243;1244; CHECK-GI-NOFP16-LABEL: v4f16_half:1245; CHECK-GI-NOFP16: // %bb.0: // %entry1246; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h1247; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h1248; CHECK-GI-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s1249; CHECK-GI-NOFP16-NEXT: xtn v0.4h, v0.4s1250; CHECK-GI-NOFP16-NEXT: bsl v0.8b, v2.8b, v3.8b1251; CHECK-GI-NOFP16-NEXT: ret1252;1253; CHECK-GI-FP16-LABEL: v4f16_half:1254; CHECK-GI-FP16: // %bb.0: // %entry1255; CHECK-GI-FP16-NEXT: fcmgt v0.4h, v1.4h, v0.4h1256; CHECK-GI-FP16-NEXT: bsl v0.8b, v2.8b, v3.8b1257; CHECK-GI-FP16-NEXT: ret1258entry:1259 %c = fcmp olt <4 x half> %a, %b1260 %s = select <4 x i1> %c, <4 x half> %d, <4 x half> %e1261 ret <4 x half> %s1262}1263 1264define <8 x half> @v8f16_half(<8 x half> %a, <8 x half> %b, <8 x half> %d, <8 x half> %e) {1265; CHECK-SD-NOFP16-LABEL: v8f16_half:1266; CHECK-SD-NOFP16: // %bb.0: // %entry1267; CHECK-SD-NOFP16-NEXT: fcvtl2 v4.4s, v0.8h1268; CHECK-SD-NOFP16-NEXT: fcvtl2 v5.4s, v1.8h1269; CHECK-SD-NOFP16-NEXT: fcvtl v0.4s, v0.4h1270; CHECK-SD-NOFP16-NEXT: fcvtl v1.4s, v1.4h1271; CHECK-SD-NOFP16-NEXT: fcmgt v4.4s, v5.4s, v4.4s1272; CHECK-SD-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s1273; CHECK-SD-NOFP16-NEXT: uzp1 v0.8h, v0.8h, v4.8h1274; CHECK-SD-NOFP16-NEXT: bsl v0.16b, v2.16b, v3.16b1275; CHECK-SD-NOFP16-NEXT: ret1276;1277; CHECK-SD-FP16-LABEL: v8f16_half:1278; CHECK-SD-FP16: // %bb.0: // %entry1279; CHECK-SD-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h1280; CHECK-SD-FP16-NEXT: bsl v0.16b, v2.16b, v3.16b1281; CHECK-SD-FP16-NEXT: ret1282;1283; CHECK-GI-NOFP16-LABEL: v8f16_half:1284; CHECK-GI-NOFP16: // %bb.0: // %entry1285; CHECK-GI-NOFP16-NEXT: fcvtl v4.4s, v0.4h1286; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h1287; CHECK-GI-NOFP16-NEXT: fcvtl v5.4s, v1.4h1288; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h1289; CHECK-GI-NOFP16-NEXT: fcmgt v4.4s, v5.4s, v4.4s1290; CHECK-GI-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s1291; CHECK-GI-NOFP16-NEXT: uzp1 v0.8h, v4.8h, v0.8h1292; CHECK-GI-NOFP16-NEXT: bsl v0.16b, v2.16b, v3.16b1293; CHECK-GI-NOFP16-NEXT: ret1294;1295; CHECK-GI-FP16-LABEL: v8f16_half:1296; CHECK-GI-FP16: // %bb.0: // %entry1297; CHECK-GI-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h1298; CHECK-GI-FP16-NEXT: bsl v0.16b, v2.16b, v3.16b1299; CHECK-GI-FP16-NEXT: ret1300entry:1301 %c = fcmp olt <8 x half> %a, %b1302 %s = select <8 x i1> %c, <8 x half> %d, <8 x half> %e1303 ret <8 x half> %s1304}1305 1306define <16 x half> @v16f16_half(<16 x half> %a, <16 x half> %b, <16 x half> %d, <16 x half> %e) {1307; CHECK-SD-NOFP16-LABEL: v16f16_half:1308; CHECK-SD-NOFP16: // %bb.0: // %entry1309; CHECK-SD-NOFP16-NEXT: fcvtl2 v16.4s, v1.8h1310; CHECK-SD-NOFP16-NEXT: fcvtl2 v17.4s, v3.8h1311; CHECK-SD-NOFP16-NEXT: fcvtl v1.4s, v1.4h1312; CHECK-SD-NOFP16-NEXT: fcvtl v3.4s, v3.4h1313; CHECK-SD-NOFP16-NEXT: fcvtl2 v18.4s, v0.8h1314; CHECK-SD-NOFP16-NEXT: fcvtl2 v19.4s, v2.8h1315; CHECK-SD-NOFP16-NEXT: fcvtl v0.4s, v0.4h1316; CHECK-SD-NOFP16-NEXT: fcvtl v2.4s, v2.4h1317; CHECK-SD-NOFP16-NEXT: fcmgt v16.4s, v17.4s, v16.4s1318; CHECK-SD-NOFP16-NEXT: fcmgt v1.4s, v3.4s, v1.4s1319; CHECK-SD-NOFP16-NEXT: fcmgt v3.4s, v19.4s, v18.4s1320; CHECK-SD-NOFP16-NEXT: fcmgt v0.4s, v2.4s, v0.4s1321; CHECK-SD-NOFP16-NEXT: uzp1 v1.8h, v1.8h, v16.8h1322; CHECK-SD-NOFP16-NEXT: uzp1 v0.8h, v0.8h, v3.8h1323; CHECK-SD-NOFP16-NEXT: bsl v1.16b, v5.16b, v7.16b1324; CHECK-SD-NOFP16-NEXT: bsl v0.16b, v4.16b, v6.16b1325; CHECK-SD-NOFP16-NEXT: ret1326;1327; CHECK-SD-FP16-LABEL: v16f16_half:1328; CHECK-SD-FP16: // %bb.0: // %entry1329; CHECK-SD-FP16-NEXT: fcmgt v1.8h, v3.8h, v1.8h1330; CHECK-SD-FP16-NEXT: fcmgt v0.8h, v2.8h, v0.8h1331; CHECK-SD-FP16-NEXT: bsl v1.16b, v5.16b, v7.16b1332; CHECK-SD-FP16-NEXT: bsl v0.16b, v4.16b, v6.16b1333; CHECK-SD-FP16-NEXT: ret1334;1335; CHECK-GI-NOFP16-LABEL: v16f16_half:1336; CHECK-GI-NOFP16: // %bb.0: // %entry1337; CHECK-GI-NOFP16-NEXT: fcvtl v16.4s, v0.4h1338; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h1339; CHECK-GI-NOFP16-NEXT: fcvtl v17.4s, v1.4h1340; CHECK-GI-NOFP16-NEXT: fcvtl v18.4s, v2.4h1341; CHECK-GI-NOFP16-NEXT: fcvtl2 v2.4s, v2.8h1342; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h1343; CHECK-GI-NOFP16-NEXT: fcvtl v19.4s, v3.4h1344; CHECK-GI-NOFP16-NEXT: fcvtl2 v3.4s, v3.8h1345; CHECK-GI-NOFP16-NEXT: fcmgt v16.4s, v18.4s, v16.4s1346; CHECK-GI-NOFP16-NEXT: fcmgt v0.4s, v2.4s, v0.4s1347; CHECK-GI-NOFP16-NEXT: fcmgt v2.4s, v19.4s, v17.4s1348; CHECK-GI-NOFP16-NEXT: fcmgt v1.4s, v3.4s, v1.4s1349; CHECK-GI-NOFP16-NEXT: uzp1 v0.8h, v16.8h, v0.8h1350; CHECK-GI-NOFP16-NEXT: uzp1 v1.8h, v2.8h, v1.8h1351; CHECK-GI-NOFP16-NEXT: and v2.16b, v4.16b, v0.16b1352; CHECK-GI-NOFP16-NEXT: bic v0.16b, v6.16b, v0.16b1353; CHECK-GI-NOFP16-NEXT: and v3.16b, v5.16b, v1.16b1354; CHECK-GI-NOFP16-NEXT: bic v1.16b, v7.16b, v1.16b1355; CHECK-GI-NOFP16-NEXT: orr v0.16b, v2.16b, v0.16b1356; CHECK-GI-NOFP16-NEXT: orr v1.16b, v3.16b, v1.16b1357; CHECK-GI-NOFP16-NEXT: ret1358;1359; CHECK-GI-FP16-LABEL: v16f16_half:1360; CHECK-GI-FP16: // %bb.0: // %entry1361; CHECK-GI-FP16-NEXT: fcmgt v0.8h, v2.8h, v0.8h1362; CHECK-GI-FP16-NEXT: fcmgt v1.8h, v3.8h, v1.8h1363; CHECK-GI-FP16-NEXT: bsl v0.16b, v4.16b, v6.16b1364; CHECK-GI-FP16-NEXT: bsl v1.16b, v5.16b, v7.16b1365; CHECK-GI-FP16-NEXT: ret1366entry:1367 %c = fcmp olt <16 x half> %a, %b1368 %s = select <16 x i1> %c, <16 x half> %d, <16 x half> %e1369 ret <16 x half> %s1370}1371 1372define <7 x i32> @v7f16_i32(<7 x half> %a, <7 x half> %b, <7 x i32> %d, <7 x i32> %e) {1373; CHECK-SD-NOFP16-LABEL: v7f16_i32:1374; CHECK-SD-NOFP16: // %bb.0: // %entry1375; CHECK-SD-NOFP16-NEXT: fmov s2, w01376; CHECK-SD-NOFP16-NEXT: fmov s4, w71377; CHECK-SD-NOFP16-NEXT: mov x8, sp1378; CHECK-SD-NOFP16-NEXT: fmov s5, w41379; CHECK-SD-NOFP16-NEXT: fcvtl v6.4s, v0.4h1380; CHECK-SD-NOFP16-NEXT: ldr s3, [sp, #24]1381; CHECK-SD-NOFP16-NEXT: fcvtl v7.4s, v1.4h1382; CHECK-SD-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h1383; CHECK-SD-NOFP16-NEXT: add x9, sp, #81384; CHECK-SD-NOFP16-NEXT: mov v2.s[1], w11385; CHECK-SD-NOFP16-NEXT: ld1 { v4.s }[1], [x8]1386; CHECK-SD-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h1387; CHECK-SD-NOFP16-NEXT: mov v5.s[1], w51388; CHECK-SD-NOFP16-NEXT: add x8, sp, #321389; CHECK-SD-NOFP16-NEXT: ld1 { v3.s }[1], [x8]1390; CHECK-SD-NOFP16-NEXT: add x8, sp, #161391; CHECK-SD-NOFP16-NEXT: fcmgt v6.4s, v7.4s, v6.4s1392; CHECK-SD-NOFP16-NEXT: ld1 { v4.s }[2], [x9]1393; CHECK-SD-NOFP16-NEXT: add x9, sp, #401394; CHECK-SD-NOFP16-NEXT: mov v2.s[2], w21395; CHECK-SD-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s1396; CHECK-SD-NOFP16-NEXT: mov v5.s[2], w61397; CHECK-SD-NOFP16-NEXT: ld1 { v3.s }[2], [x9]1398; CHECK-SD-NOFP16-NEXT: ld1 { v4.s }[3], [x8]1399; CHECK-SD-NOFP16-NEXT: mov v1.16b, v6.16b1400; CHECK-SD-NOFP16-NEXT: mov v2.s[3], w31401; CHECK-SD-NOFP16-NEXT: bsl v0.16b, v5.16b, v3.16b1402; CHECK-SD-NOFP16-NEXT: bsl v1.16b, v2.16b, v4.16b1403; CHECK-SD-NOFP16-NEXT: mov w5, v0.s[1]1404; CHECK-SD-NOFP16-NEXT: mov w6, v0.s[2]1405; CHECK-SD-NOFP16-NEXT: fmov w4, s01406; CHECK-SD-NOFP16-NEXT: mov w1, v1.s[1]1407; CHECK-SD-NOFP16-NEXT: mov w2, v1.s[2]1408; CHECK-SD-NOFP16-NEXT: mov w3, v1.s[3]1409; CHECK-SD-NOFP16-NEXT: fmov w0, s11410; CHECK-SD-NOFP16-NEXT: ret1411;1412; CHECK-SD-FP16-LABEL: v7f16_i32:1413; CHECK-SD-FP16: // %bb.0: // %entry1414; CHECK-SD-FP16-NEXT: fmov s2, w01415; CHECK-SD-FP16-NEXT: fmov s3, w71416; CHECK-SD-FP16-NEXT: mov x8, sp1417; CHECK-SD-FP16-NEXT: fmov s5, w41418; CHECK-SD-FP16-NEXT: ldr s4, [sp, #24]1419; CHECK-SD-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h1420; CHECK-SD-FP16-NEXT: add x9, sp, #321421; CHECK-SD-FP16-NEXT: mov v2.s[1], w11422; CHECK-SD-FP16-NEXT: ld1 { v3.s }[1], [x8]1423; CHECK-SD-FP16-NEXT: add x8, sp, #81424; CHECK-SD-FP16-NEXT: mov v5.s[1], w51425; CHECK-SD-FP16-NEXT: ld1 { v4.s }[1], [x9]1426; CHECK-SD-FP16-NEXT: add x9, sp, #161427; CHECK-SD-FP16-NEXT: sshll v1.4s, v0.4h, #01428; CHECK-SD-FP16-NEXT: sshll2 v0.4s, v0.8h, #01429; CHECK-SD-FP16-NEXT: ld1 { v3.s }[2], [x8]1430; CHECK-SD-FP16-NEXT: add x8, sp, #401431; CHECK-SD-FP16-NEXT: mov v2.s[2], w21432; CHECK-SD-FP16-NEXT: ld1 { v4.s }[2], [x8]1433; CHECK-SD-FP16-NEXT: mov v5.s[2], w61434; CHECK-SD-FP16-NEXT: ld1 { v3.s }[3], [x9]1435; CHECK-SD-FP16-NEXT: mov v2.s[3], w31436; CHECK-SD-FP16-NEXT: bsl v0.16b, v5.16b, v4.16b1437; CHECK-SD-FP16-NEXT: bsl v1.16b, v2.16b, v3.16b1438; CHECK-SD-FP16-NEXT: mov w5, v0.s[1]1439; CHECK-SD-FP16-NEXT: mov w6, v0.s[2]1440; CHECK-SD-FP16-NEXT: fmov w4, s01441; CHECK-SD-FP16-NEXT: mov w1, v1.s[1]1442; CHECK-SD-FP16-NEXT: mov w2, v1.s[2]1443; CHECK-SD-FP16-NEXT: mov w3, v1.s[3]1444; CHECK-SD-FP16-NEXT: fmov w0, s11445; CHECK-SD-FP16-NEXT: ret1446;1447; CHECK-GI-NOFP16-LABEL: v7f16_i32:1448; CHECK-GI-NOFP16: // %bb.0: // %entry1449; CHECK-GI-NOFP16-NEXT: mov v2.h[0], v0.h[4]1450; CHECK-GI-NOFP16-NEXT: mov v3.h[0], v1.h[4]1451; CHECK-GI-NOFP16-NEXT: mov w8, #31 // =0x1f1452; CHECK-GI-NOFP16-NEXT: fmov s4, w81453; CHECK-GI-NOFP16-NEXT: fmov s7, w01454; CHECK-GI-NOFP16-NEXT: ldr s5, [sp]1455; CHECK-GI-NOFP16-NEXT: fmov s16, w71456; CHECK-GI-NOFP16-NEXT: fmov s18, w41457; CHECK-GI-NOFP16-NEXT: ldr s17, [sp, #32]1458; CHECK-GI-NOFP16-NEXT: ldr s6, [sp, #8]1459; CHECK-GI-NOFP16-NEXT: mov v2.h[1], v0.h[5]1460; CHECK-GI-NOFP16-NEXT: mov v3.h[1], v1.h[5]1461; CHECK-GI-NOFP16-NEXT: mov v4.s[1], w81462; CHECK-GI-NOFP16-NEXT: mov v7.s[1], w11463; CHECK-GI-NOFP16-NEXT: mov v16.s[1], v5.s[0]1464; CHECK-GI-NOFP16-NEXT: ldr s5, [sp, #24]1465; CHECK-GI-NOFP16-NEXT: mov v18.s[1], w51466; CHECK-GI-NOFP16-NEXT: mov v5.s[1], v17.s[0]1467; CHECK-GI-NOFP16-NEXT: mov v2.h[2], v0.h[6]1468; CHECK-GI-NOFP16-NEXT: mov v3.h[2], v1.h[6]1469; CHECK-GI-NOFP16-NEXT: mov v4.s[2], w81470; CHECK-GI-NOFP16-NEXT: mov w8, #-1 // =0xffffffff1471; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h1472; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h1473; CHECK-GI-NOFP16-NEXT: mov v7.s[2], w21474; CHECK-GI-NOFP16-NEXT: mov v16.s[2], v6.s[0]1475; CHECK-GI-NOFP16-NEXT: ldr s6, [sp, #40]1476; CHECK-GI-NOFP16-NEXT: mov v18.s[2], w61477; CHECK-GI-NOFP16-NEXT: fcvtl v2.4s, v2.4h1478; CHECK-GI-NOFP16-NEXT: fcvtl v3.4s, v3.4h1479; CHECK-GI-NOFP16-NEXT: mov v5.s[2], v6.s[0]1480; CHECK-GI-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s1481; CHECK-GI-NOFP16-NEXT: mov v7.s[3], w31482; CHECK-GI-NOFP16-NEXT: fcmgt v2.4s, v3.4s, v2.4s1483; CHECK-GI-NOFP16-NEXT: fmov s3, w81484; CHECK-GI-NOFP16-NEXT: mov v3.s[1], w81485; CHECK-GI-NOFP16-NEXT: ushl v2.4s, v2.4s, v4.4s1486; CHECK-GI-NOFP16-NEXT: neg v4.4s, v4.4s1487; CHECK-GI-NOFP16-NEXT: mov v3.s[2], w81488; CHECK-GI-NOFP16-NEXT: sshl v2.4s, v2.4s, v4.4s1489; CHECK-GI-NOFP16-NEXT: ldr s4, [sp, #16]1490; CHECK-GI-NOFP16-NEXT: mov v16.s[3], v4.s[0]1491; CHECK-GI-NOFP16-NEXT: eor v1.16b, v2.16b, v3.16b1492; CHECK-GI-NOFP16-NEXT: and v2.16b, v18.16b, v2.16b1493; CHECK-GI-NOFP16-NEXT: bsl v0.16b, v7.16b, v16.16b1494; CHECK-GI-NOFP16-NEXT: and v1.16b, v5.16b, v1.16b1495; CHECK-GI-NOFP16-NEXT: orr v1.16b, v2.16b, v1.16b1496; CHECK-GI-NOFP16-NEXT: mov s2, v0.s[1]1497; CHECK-GI-NOFP16-NEXT: mov s3, v0.s[2]1498; CHECK-GI-NOFP16-NEXT: mov s4, v0.s[3]1499; CHECK-GI-NOFP16-NEXT: fmov w0, s01500; CHECK-GI-NOFP16-NEXT: mov s5, v1.s[1]1501; CHECK-GI-NOFP16-NEXT: mov s6, v1.s[2]1502; CHECK-GI-NOFP16-NEXT: fmov w4, s11503; CHECK-GI-NOFP16-NEXT: fmov w1, s21504; CHECK-GI-NOFP16-NEXT: fmov w2, s31505; CHECK-GI-NOFP16-NEXT: fmov w3, s41506; CHECK-GI-NOFP16-NEXT: fmov w5, s51507; CHECK-GI-NOFP16-NEXT: fmov w6, s61508; CHECK-GI-NOFP16-NEXT: ret1509;1510; CHECK-GI-FP16-LABEL: v7f16_i32:1511; CHECK-GI-FP16: // %bb.0: // %entry1512; CHECK-GI-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h1513; CHECK-GI-FP16-NEXT: mov w10, #31 // =0x1f1514; CHECK-GI-FP16-NEXT: fmov s5, w01515; CHECK-GI-FP16-NEXT: fmov s2, w101516; CHECK-GI-FP16-NEXT: fmov s6, w71517; CHECK-GI-FP16-NEXT: ldr s3, [sp]1518; CHECK-GI-FP16-NEXT: fmov s17, w41519; CHECK-GI-FP16-NEXT: ldr s7, [sp, #24]1520; CHECK-GI-FP16-NEXT: ldr s16, [sp, #32]1521; CHECK-GI-FP16-NEXT: mov v5.s[1], w11522; CHECK-GI-FP16-NEXT: umov w8, v0.h[4]1523; CHECK-GI-FP16-NEXT: umov w9, v0.h[5]1524; CHECK-GI-FP16-NEXT: mov v2.s[1], w101525; CHECK-GI-FP16-NEXT: mov v6.s[1], v3.s[0]1526; CHECK-GI-FP16-NEXT: ldr s3, [sp, #8]1527; CHECK-GI-FP16-NEXT: mov v17.s[1], w51528; CHECK-GI-FP16-NEXT: mov v7.s[1], v16.s[0]1529; CHECK-GI-FP16-NEXT: mov v5.s[2], w21530; CHECK-GI-FP16-NEXT: fmov s1, w81531; CHECK-GI-FP16-NEXT: umov w8, v0.h[6]1532; CHECK-GI-FP16-NEXT: mov v2.s[2], w101533; CHECK-GI-FP16-NEXT: ushll v0.4s, v0.4h, #01534; CHECK-GI-FP16-NEXT: mov v6.s[2], v3.s[0]1535; CHECK-GI-FP16-NEXT: ldr s3, [sp, #40]1536; CHECK-GI-FP16-NEXT: mov v17.s[2], w61537; CHECK-GI-FP16-NEXT: mov v1.s[1], w91538; CHECK-GI-FP16-NEXT: mov v7.s[2], v3.s[0]1539; CHECK-GI-FP16-NEXT: mov v5.s[3], w31540; CHECK-GI-FP16-NEXT: shl v0.4s, v0.4s, #311541; CHECK-GI-FP16-NEXT: mov v1.s[2], w81542; CHECK-GI-FP16-NEXT: mov w8, #-1 // =0xffffffff1543; CHECK-GI-FP16-NEXT: cmlt v0.4s, v0.4s, #01544; CHECK-GI-FP16-NEXT: fmov s4, w81545; CHECK-GI-FP16-NEXT: mov v4.s[1], w81546; CHECK-GI-FP16-NEXT: ushl v1.4s, v1.4s, v2.4s1547; CHECK-GI-FP16-NEXT: neg v2.4s, v2.4s1548; CHECK-GI-FP16-NEXT: sshl v1.4s, v1.4s, v2.4s1549; CHECK-GI-FP16-NEXT: ldr s2, [sp, #16]1550; CHECK-GI-FP16-NEXT: mov v4.s[2], w81551; CHECK-GI-FP16-NEXT: mov v6.s[3], v2.s[0]1552; CHECK-GI-FP16-NEXT: eor v3.16b, v1.16b, v4.16b1553; CHECK-GI-FP16-NEXT: and v1.16b, v17.16b, v1.16b1554; CHECK-GI-FP16-NEXT: bsl v0.16b, v5.16b, v6.16b1555; CHECK-GI-FP16-NEXT: and v2.16b, v7.16b, v3.16b1556; CHECK-GI-FP16-NEXT: mov s3, v0.s[2]1557; CHECK-GI-FP16-NEXT: mov s4, v0.s[3]1558; CHECK-GI-FP16-NEXT: fmov w0, s01559; CHECK-GI-FP16-NEXT: orr v1.16b, v1.16b, v2.16b1560; CHECK-GI-FP16-NEXT: mov s2, v0.s[1]1561; CHECK-GI-FP16-NEXT: mov s5, v1.s[1]1562; CHECK-GI-FP16-NEXT: mov s6, v1.s[2]1563; CHECK-GI-FP16-NEXT: fmov w2, s31564; CHECK-GI-FP16-NEXT: fmov w1, s21565; CHECK-GI-FP16-NEXT: fmov w3, s41566; CHECK-GI-FP16-NEXT: fmov w4, s11567; CHECK-GI-FP16-NEXT: fmov w5, s51568; CHECK-GI-FP16-NEXT: fmov w6, s61569; CHECK-GI-FP16-NEXT: ret1570entry:1571 %c = fcmp olt <7 x half> %a, %b1572 %s = select <7 x i1> %c, <7 x i32> %d, <7 x i32> %e1573 ret <7 x i32> %s1574}1575 1576define <4 x i32> @v4f16_i32(<4 x half> %a, <4 x half> %b, <4 x i32> %d, <4 x i32> %e) {1577; CHECK-SD-NOFP16-LABEL: v4f16_i32:1578; CHECK-SD-NOFP16: // %bb.0: // %entry1579; CHECK-SD-NOFP16-NEXT: fcvtl v0.4s, v0.4h1580; CHECK-SD-NOFP16-NEXT: fcvtl v1.4s, v1.4h1581; CHECK-SD-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s1582; CHECK-SD-NOFP16-NEXT: bsl v0.16b, v2.16b, v3.16b1583; CHECK-SD-NOFP16-NEXT: ret1584;1585; CHECK-SD-FP16-LABEL: v4f16_i32:1586; CHECK-SD-FP16: // %bb.0: // %entry1587; CHECK-SD-FP16-NEXT: fcmgt v0.4h, v1.4h, v0.4h1588; CHECK-SD-FP16-NEXT: sshll v0.4s, v0.4h, #01589; CHECK-SD-FP16-NEXT: bsl v0.16b, v2.16b, v3.16b1590; CHECK-SD-FP16-NEXT: ret1591;1592; CHECK-GI-NOFP16-LABEL: v4f16_i32:1593; CHECK-GI-NOFP16: // %bb.0: // %entry1594; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h1595; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v1.4h1596; CHECK-GI-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s1597; CHECK-GI-NOFP16-NEXT: bsl v0.16b, v2.16b, v3.16b1598; CHECK-GI-NOFP16-NEXT: ret1599;1600; CHECK-GI-FP16-LABEL: v4f16_i32:1601; CHECK-GI-FP16: // %bb.0: // %entry1602; CHECK-GI-FP16-NEXT: fcmgt v0.4h, v1.4h, v0.4h1603; CHECK-GI-FP16-NEXT: ushll v0.4s, v0.4h, #01604; CHECK-GI-FP16-NEXT: shl v0.4s, v0.4s, #311605; CHECK-GI-FP16-NEXT: cmlt v0.4s, v0.4s, #01606; CHECK-GI-FP16-NEXT: bsl v0.16b, v2.16b, v3.16b1607; CHECK-GI-FP16-NEXT: ret1608entry:1609 %c = fcmp olt <4 x half> %a, %b1610 %s = select <4 x i1> %c, <4 x i32> %d, <4 x i32> %e1611 ret <4 x i32> %s1612}1613 1614define <8 x i32> @v8f16_i32(<8 x half> %a, <8 x half> %b, <8 x i32> %d, <8 x i32> %e) {1615; CHECK-SD-NOFP16-LABEL: v8f16_i32:1616; CHECK-SD-NOFP16: // %bb.0: // %entry1617; CHECK-SD-NOFP16-NEXT: fcvtl v6.4s, v0.4h1618; CHECK-SD-NOFP16-NEXT: fcvtl v7.4s, v1.4h1619; CHECK-SD-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h1620; CHECK-SD-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h1621; CHECK-SD-NOFP16-NEXT: fcmgt v6.4s, v7.4s, v6.4s1622; CHECK-SD-NOFP16-NEXT: fcmgt v0.4s, v1.4s, v0.4s1623; CHECK-SD-NOFP16-NEXT: mov v1.16b, v0.16b1624; CHECK-SD-NOFP16-NEXT: mov v0.16b, v6.16b1625; CHECK-SD-NOFP16-NEXT: bsl v1.16b, v3.16b, v5.16b1626; CHECK-SD-NOFP16-NEXT: bsl v0.16b, v2.16b, v4.16b1627; CHECK-SD-NOFP16-NEXT: ret1628;1629; CHECK-SD-FP16-LABEL: v8f16_i32:1630; CHECK-SD-FP16: // %bb.0: // %entry1631; CHECK-SD-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h1632; CHECK-SD-FP16-NEXT: sshll v6.4s, v0.4h, #01633; CHECK-SD-FP16-NEXT: sshll2 v0.4s, v0.8h, #01634; CHECK-SD-FP16-NEXT: mov v1.16b, v0.16b1635; CHECK-SD-FP16-NEXT: mov v0.16b, v6.16b1636; CHECK-SD-FP16-NEXT: bsl v1.16b, v3.16b, v5.16b1637; CHECK-SD-FP16-NEXT: bsl v0.16b, v2.16b, v4.16b1638; CHECK-SD-FP16-NEXT: ret1639;1640; CHECK-GI-NOFP16-LABEL: v8f16_i32:1641; CHECK-GI-NOFP16: // %bb.0: // %entry1642; CHECK-GI-NOFP16-NEXT: fcvtl v6.4s, v0.4h1643; CHECK-GI-NOFP16-NEXT: fcvtl v7.4s, v1.4h1644; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h1645; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h1646; CHECK-GI-NOFP16-NEXT: fcmgt v6.4s, v7.4s, v6.4s1647; CHECK-GI-NOFP16-NEXT: fcmgt v1.4s, v1.4s, v0.4s1648; CHECK-GI-NOFP16-NEXT: mov v0.16b, v6.16b1649; CHECK-GI-NOFP16-NEXT: bsl v1.16b, v3.16b, v5.16b1650; CHECK-GI-NOFP16-NEXT: bsl v0.16b, v2.16b, v4.16b1651; CHECK-GI-NOFP16-NEXT: ret1652;1653; CHECK-GI-FP16-LABEL: v8f16_i32:1654; CHECK-GI-FP16: // %bb.0: // %entry1655; CHECK-GI-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h1656; CHECK-GI-FP16-NEXT: ushll v1.4s, v0.4h, #01657; CHECK-GI-FP16-NEXT: ushll2 v0.4s, v0.8h, #01658; CHECK-GI-FP16-NEXT: shl v1.4s, v1.4s, #311659; CHECK-GI-FP16-NEXT: shl v0.4s, v0.4s, #311660; CHECK-GI-FP16-NEXT: cmlt v1.4s, v1.4s, #01661; CHECK-GI-FP16-NEXT: cmlt v6.4s, v0.4s, #01662; CHECK-GI-FP16-NEXT: mov v0.16b, v1.16b1663; CHECK-GI-FP16-NEXT: mov v1.16b, v6.16b1664; CHECK-GI-FP16-NEXT: bsl v0.16b, v2.16b, v4.16b1665; CHECK-GI-FP16-NEXT: bsl v1.16b, v3.16b, v5.16b1666; CHECK-GI-FP16-NEXT: ret1667entry:1668 %c = fcmp olt <8 x half> %a, %b1669 %s = select <8 x i1> %c, <8 x i32> %d, <8 x i32> %e1670 ret <8 x i32> %s1671}1672 1673define <16 x i32> @v16f16_i32(<16 x half> %a, <16 x half> %b, <16 x i32> %d, <16 x i32> %e) {1674; CHECK-SD-NOFP16-LABEL: v16f16_i32:1675; CHECK-SD-NOFP16: // %bb.0: // %entry1676; CHECK-SD-NOFP16-NEXT: fcvtl v16.4s, v1.4h1677; CHECK-SD-NOFP16-NEXT: fcvtl v17.4s, v3.4h1678; CHECK-SD-NOFP16-NEXT: fcvtl v18.4s, v0.4h1679; CHECK-SD-NOFP16-NEXT: fcvtl v19.4s, v2.4h1680; CHECK-SD-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h1681; CHECK-SD-NOFP16-NEXT: fcvtl2 v3.4s, v3.8h1682; CHECK-SD-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h1683; CHECK-SD-NOFP16-NEXT: fcvtl2 v2.4s, v2.8h1684; CHECK-SD-NOFP16-NEXT: fcmgt v16.4s, v17.4s, v16.4s1685; CHECK-SD-NOFP16-NEXT: fcmgt v18.4s, v19.4s, v18.4s1686; CHECK-SD-NOFP16-NEXT: fcmgt v3.4s, v3.4s, v1.4s1687; CHECK-SD-NOFP16-NEXT: fcmgt v1.4s, v2.4s, v0.4s1688; CHECK-SD-NOFP16-NEXT: ldp q0, q19, [sp]1689; CHECK-SD-NOFP16-NEXT: ldp q2, q17, [sp, #32]1690; CHECK-SD-NOFP16-NEXT: bit v0.16b, v4.16b, v18.16b1691; CHECK-SD-NOFP16-NEXT: bsl v1.16b, v5.16b, v19.16b1692; CHECK-SD-NOFP16-NEXT: bsl v3.16b, v7.16b, v17.16b1693; CHECK-SD-NOFP16-NEXT: bit v2.16b, v6.16b, v16.16b1694; CHECK-SD-NOFP16-NEXT: ret1695;1696; CHECK-SD-FP16-LABEL: v16f16_i32:1697; CHECK-SD-FP16: // %bb.0: // %entry1698; CHECK-SD-FP16-NEXT: fcmgt v0.8h, v2.8h, v0.8h1699; CHECK-SD-FP16-NEXT: fcmgt v1.8h, v3.8h, v1.8h1700; CHECK-SD-FP16-NEXT: ldp q2, q20, [sp]1701; CHECK-SD-FP16-NEXT: ldp q18, q19, [sp, #32]1702; CHECK-SD-FP16-NEXT: sshll v3.4s, v0.4h, #01703; CHECK-SD-FP16-NEXT: sshll v16.4s, v1.4h, #01704; CHECK-SD-FP16-NEXT: sshll2 v17.4s, v1.8h, #01705; CHECK-SD-FP16-NEXT: sshll2 v1.4s, v0.8h, #01706; CHECK-SD-FP16-NEXT: mov v0.16b, v3.16b1707; CHECK-SD-FP16-NEXT: mov v3.16b, v17.16b1708; CHECK-SD-FP16-NEXT: bsl v1.16b, v5.16b, v20.16b1709; CHECK-SD-FP16-NEXT: bsl v0.16b, v4.16b, v2.16b1710; CHECK-SD-FP16-NEXT: mov v2.16b, v16.16b1711; CHECK-SD-FP16-NEXT: bsl v3.16b, v7.16b, v19.16b1712; CHECK-SD-FP16-NEXT: bsl v2.16b, v6.16b, v18.16b1713; CHECK-SD-FP16-NEXT: ret1714;1715; CHECK-GI-NOFP16-LABEL: v16f16_i32:1716; CHECK-GI-NOFP16: // %bb.0: // %entry1717; CHECK-GI-NOFP16-NEXT: fcvtl v16.4s, v0.4h1718; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h1719; CHECK-GI-NOFP16-NEXT: fcvtl v17.4s, v1.4h1720; CHECK-GI-NOFP16-NEXT: fcvtl v18.4s, v2.4h1721; CHECK-GI-NOFP16-NEXT: fcvtl2 v2.4s, v2.8h1722; CHECK-GI-NOFP16-NEXT: fcvtl v19.4s, v3.4h1723; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h1724; CHECK-GI-NOFP16-NEXT: fcvtl2 v3.4s, v3.8h1725; CHECK-GI-NOFP16-NEXT: fcmgt v2.4s, v2.4s, v0.4s1726; CHECK-GI-NOFP16-NEXT: fcmgt v17.4s, v19.4s, v17.4s1727; CHECK-GI-NOFP16-NEXT: fcmgt v16.4s, v18.4s, v16.4s1728; CHECK-GI-NOFP16-NEXT: fcmgt v3.4s, v3.4s, v1.4s1729; CHECK-GI-NOFP16-NEXT: ldp q0, q1, [sp]1730; CHECK-GI-NOFP16-NEXT: ldp q18, q19, [sp, #32]1731; CHECK-GI-NOFP16-NEXT: bit v1.16b, v5.16b, v2.16b1732; CHECK-GI-NOFP16-NEXT: mov v2.16b, v17.16b1733; CHECK-GI-NOFP16-NEXT: bit v0.16b, v4.16b, v16.16b1734; CHECK-GI-NOFP16-NEXT: bsl v3.16b, v7.16b, v19.16b1735; CHECK-GI-NOFP16-NEXT: bsl v2.16b, v6.16b, v18.16b1736; CHECK-GI-NOFP16-NEXT: ret1737;1738; CHECK-GI-FP16-LABEL: v16f16_i32:1739; CHECK-GI-FP16: // %bb.0: // %entry1740; CHECK-GI-FP16-NEXT: fcmgt v0.8h, v2.8h, v0.8h1741; CHECK-GI-FP16-NEXT: fcmgt v1.8h, v3.8h, v1.8h1742; CHECK-GI-FP16-NEXT: ldp q18, q19, [sp, #32]1743; CHECK-GI-FP16-NEXT: ushll v2.4s, v0.4h, #01744; CHECK-GI-FP16-NEXT: ushll2 v0.4s, v0.8h, #01745; CHECK-GI-FP16-NEXT: ushll v3.4s, v1.4h, #01746; CHECK-GI-FP16-NEXT: ushll2 v1.4s, v1.8h, #01747; CHECK-GI-FP16-NEXT: shl v2.4s, v2.4s, #311748; CHECK-GI-FP16-NEXT: shl v0.4s, v0.4s, #311749; CHECK-GI-FP16-NEXT: shl v3.4s, v3.4s, #311750; CHECK-GI-FP16-NEXT: shl v1.4s, v1.4s, #311751; CHECK-GI-FP16-NEXT: cmlt v2.4s, v2.4s, #01752; CHECK-GI-FP16-NEXT: cmlt v16.4s, v0.4s, #01753; CHECK-GI-FP16-NEXT: cmlt v3.4s, v3.4s, #01754; CHECK-GI-FP16-NEXT: cmlt v17.4s, v1.4s, #01755; CHECK-GI-FP16-NEXT: ldp q0, q1, [sp]1756; CHECK-GI-FP16-NEXT: bit v0.16b, v4.16b, v2.16b1757; CHECK-GI-FP16-NEXT: mov v2.16b, v3.16b1758; CHECK-GI-FP16-NEXT: mov v3.16b, v17.16b1759; CHECK-GI-FP16-NEXT: bit v1.16b, v5.16b, v16.16b1760; CHECK-GI-FP16-NEXT: bsl v2.16b, v6.16b, v18.16b1761; CHECK-GI-FP16-NEXT: bsl v3.16b, v7.16b, v19.16b1762; CHECK-GI-FP16-NEXT: ret1763entry:1764 %c = fcmp olt <16 x half> %a, %b1765 %s = select <16 x i1> %c, <16 x i32> %d, <16 x i32> %e1766 ret <16 x i32> %s1767}1768