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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-NO16,CHECK-SD-NO163; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-FP16,CHECK-SD-FP164; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-NO16,CHECK-GI-NO165; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-FP16,CHECK-GI-FP166 7; fptoui8 9define i32 @fcvtzs_f32_i32_7(float %flt) {10; CHECK-SD-LABEL: fcvtzs_f32_i32_7:11; CHECK-SD: // %bb.0:12; CHECK-SD-NEXT: fcvtzs w0, s0, #713; CHECK-SD-NEXT: ret14;15; CHECK-GI-LABEL: fcvtzs_f32_i32_7:16; CHECK-GI: // %bb.0:17; CHECK-GI-NEXT: movi v1.2s, #67, lsl #2418; CHECK-GI-NEXT: fmul s0, s0, s119; CHECK-GI-NEXT: fcvtzs w0, s020; CHECK-GI-NEXT: ret21 %fix = fmul float %flt, 128.022 %cvt = fptosi float %fix to i3223 ret i32 %cvt24}25 26define i32 @fcvtzs_f32_i32_32(float %flt) {27; CHECK-SD-LABEL: fcvtzs_f32_i32_32:28; CHECK-SD: // %bb.0:29; CHECK-SD-NEXT: fcvtzs w0, s0, #3230; CHECK-SD-NEXT: ret31;32; CHECK-GI-LABEL: fcvtzs_f32_i32_32:33; CHECK-GI: // %bb.0:34; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f80000035; CHECK-GI-NEXT: fmov s1, w836; CHECK-GI-NEXT: fmul s0, s0, s137; CHECK-GI-NEXT: fcvtzs w0, s038; CHECK-GI-NEXT: ret39 %fix = fmul float %flt, 4294967296.040 %cvt = fptosi float %fix to i3241 ret i32 %cvt42}43 44define i64 @fcvtzs_f32_i64_7(float %flt) {45; CHECK-SD-LABEL: fcvtzs_f32_i64_7:46; CHECK-SD: // %bb.0:47; CHECK-SD-NEXT: fcvtzs x0, s0, #748; CHECK-SD-NEXT: ret49;50; CHECK-GI-LABEL: fcvtzs_f32_i64_7:51; CHECK-GI: // %bb.0:52; CHECK-GI-NEXT: movi v1.2s, #67, lsl #2453; CHECK-GI-NEXT: fmul s0, s0, s154; CHECK-GI-NEXT: fcvtzs x0, s055; CHECK-GI-NEXT: ret56 %fix = fmul float %flt, 128.057 %cvt = fptosi float %fix to i6458 ret i64 %cvt59}60 61define i64 @fcvtzs_f32_i64_64(float %flt) {62; CHECK-SD-LABEL: fcvtzs_f32_i64_64:63; CHECK-SD: // %bb.0:64; CHECK-SD-NEXT: fcvtzs x0, s0, #6465; CHECK-SD-NEXT: ret66;67; CHECK-GI-LABEL: fcvtzs_f32_i64_64:68; CHECK-GI: // %bb.0:69; CHECK-GI-NEXT: mov w8, #1602224128 // =0x5f80000070; CHECK-GI-NEXT: fmov s1, w871; CHECK-GI-NEXT: fmul s0, s0, s172; CHECK-GI-NEXT: fcvtzs x0, s073; CHECK-GI-NEXT: ret74 %fix = fmul float %flt, 18446744073709551616.075 %cvt = fptosi float %fix to i6476 ret i64 %cvt77}78 79define i32 @fcvtzs_f64_i32_7(double %dbl) {80; CHECK-SD-LABEL: fcvtzs_f64_i32_7:81; CHECK-SD: // %bb.0:82; CHECK-SD-NEXT: fcvtzs w0, d0, #783; CHECK-SD-NEXT: ret84;85; CHECK-GI-LABEL: fcvtzs_f64_i32_7:86; CHECK-GI: // %bb.0:87; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x406000000000000088; CHECK-GI-NEXT: fmov d1, x889; CHECK-GI-NEXT: fmul d0, d0, d190; CHECK-GI-NEXT: fcvtzs w0, d091; CHECK-GI-NEXT: ret92 %fix = fmul double %dbl, 128.093 %cvt = fptosi double %fix to i3294 ret i32 %cvt95}96 97define i32 @fcvtzs_f64_i32_32(double %dbl) {98; CHECK-SD-LABEL: fcvtzs_f64_i32_32:99; CHECK-SD: // %bb.0:100; CHECK-SD-NEXT: fcvtzs w0, d0, #32101; CHECK-SD-NEXT: ret102;103; CHECK-GI-LABEL: fcvtzs_f64_i32_32:104; CHECK-GI: // %bb.0:105; CHECK-GI-NEXT: mov x8, #4751297606875873280 // =0x41f0000000000000106; CHECK-GI-NEXT: fmov d1, x8107; CHECK-GI-NEXT: fmul d0, d0, d1108; CHECK-GI-NEXT: fcvtzs w0, d0109; CHECK-GI-NEXT: ret110 %fix = fmul double %dbl, 4294967296.0111 %cvt = fptosi double %fix to i32112 ret i32 %cvt113}114 115define i64 @fcvtzs_f64_i64_7(double %dbl) {116; CHECK-SD-LABEL: fcvtzs_f64_i64_7:117; CHECK-SD: // %bb.0:118; CHECK-SD-NEXT: fcvtzs x0, d0, #7119; CHECK-SD-NEXT: ret120;121; CHECK-GI-LABEL: fcvtzs_f64_i64_7:122; CHECK-GI: // %bb.0:123; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000124; CHECK-GI-NEXT: fmov d1, x8125; CHECK-GI-NEXT: fmul d0, d0, d1126; CHECK-GI-NEXT: fcvtzs x0, d0127; CHECK-GI-NEXT: ret128 %fix = fmul double %dbl, 128.0129 %cvt = fptosi double %fix to i64130 ret i64 %cvt131}132 133define i64 @fcvtzs_f64_i64_64(double %dbl) {134; CHECK-SD-LABEL: fcvtzs_f64_i64_64:135; CHECK-SD: // %bb.0:136; CHECK-SD-NEXT: fcvtzs x0, d0, #64137; CHECK-SD-NEXT: ret138;139; CHECK-GI-LABEL: fcvtzs_f64_i64_64:140; CHECK-GI: // %bb.0:141; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f0000000000000142; CHECK-GI-NEXT: fmov d1, x8143; CHECK-GI-NEXT: fmul d0, d0, d1144; CHECK-GI-NEXT: fcvtzs x0, d0145; CHECK-GI-NEXT: ret146 %fix = fmul double %dbl, 18446744073709551616.0147 %cvt = fptosi double %fix to i64148 ret i64 %cvt149}150 151define i32 @fcvtzs_f16_i32_7(half %flt) {152; CHECK-NO16-LABEL: fcvtzs_f16_i32_7:153; CHECK-NO16: // %bb.0:154; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #24155; CHECK-NO16-NEXT: fcvt s0, h0156; CHECK-NO16-NEXT: fmul s0, s0, s1157; CHECK-NO16-NEXT: fcvt h0, s0158; CHECK-NO16-NEXT: fcvt s0, h0159; CHECK-NO16-NEXT: fcvtzs w0, s0160; CHECK-NO16-NEXT: ret161;162; CHECK-SD-FP16-LABEL: fcvtzs_f16_i32_7:163; CHECK-SD-FP16: // %bb.0:164; CHECK-SD-FP16-NEXT: fcvtzs w0, h0, #7165; CHECK-SD-FP16-NEXT: ret166;167; CHECK-GI-FP16-LABEL: fcvtzs_f16_i32_7:168; CHECK-GI-FP16: // %bb.0:169; CHECK-GI-FP16-NEXT: adrp x8, .LCPI8_0170; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI8_0]171; CHECK-GI-FP16-NEXT: fmul h0, h0, h1172; CHECK-GI-FP16-NEXT: fcvtzs w0, h0173; CHECK-GI-FP16-NEXT: ret174 %fix = fmul half %flt, 128.0175 %cvt = fptosi half %fix to i32176 ret i32 %cvt177}178 179define i32 @fcvtzs_f16_i32_15(half %flt) {180; CHECK-NO16-LABEL: fcvtzs_f16_i32_15:181; CHECK-NO16: // %bb.0:182; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #24183; CHECK-NO16-NEXT: fcvt s0, h0184; CHECK-NO16-NEXT: fmul s0, s0, s1185; CHECK-NO16-NEXT: fcvt h0, s0186; CHECK-NO16-NEXT: fcvt s0, h0187; CHECK-NO16-NEXT: fcvtzs w0, s0188; CHECK-NO16-NEXT: ret189;190; CHECK-SD-FP16-LABEL: fcvtzs_f16_i32_15:191; CHECK-SD-FP16: // %bb.0:192; CHECK-SD-FP16-NEXT: fcvtzs w0, h0, #15193; CHECK-SD-FP16-NEXT: ret194;195; CHECK-GI-FP16-LABEL: fcvtzs_f16_i32_15:196; CHECK-GI-FP16: // %bb.0:197; CHECK-GI-FP16-NEXT: adrp x8, .LCPI9_0198; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI9_0]199; CHECK-GI-FP16-NEXT: fmul h0, h0, h1200; CHECK-GI-FP16-NEXT: fcvtzs w0, h0201; CHECK-GI-FP16-NEXT: ret202 %fix = fmul half %flt, 32768.0203 %cvt = fptosi half %fix to i32204 ret i32 %cvt205}206 207define i64 @fcvtzs_f16_i64_7(half %flt) {208; CHECK-NO16-LABEL: fcvtzs_f16_i64_7:209; CHECK-NO16: // %bb.0:210; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #24211; CHECK-NO16-NEXT: fcvt s0, h0212; CHECK-NO16-NEXT: fmul s0, s0, s1213; CHECK-NO16-NEXT: fcvt h0, s0214; CHECK-NO16-NEXT: fcvt s0, h0215; CHECK-NO16-NEXT: fcvtzs x0, s0216; CHECK-NO16-NEXT: ret217;218; CHECK-SD-FP16-LABEL: fcvtzs_f16_i64_7:219; CHECK-SD-FP16: // %bb.0:220; CHECK-SD-FP16-NEXT: fcvtzs x0, h0, #7221; CHECK-SD-FP16-NEXT: ret222;223; CHECK-GI-FP16-LABEL: fcvtzs_f16_i64_7:224; CHECK-GI-FP16: // %bb.0:225; CHECK-GI-FP16-NEXT: adrp x8, .LCPI10_0226; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI10_0]227; CHECK-GI-FP16-NEXT: fmul h0, h0, h1228; CHECK-GI-FP16-NEXT: fcvtzs x0, h0229; CHECK-GI-FP16-NEXT: ret230 %fix = fmul half %flt, 128.0231 %cvt = fptosi half %fix to i64232 ret i64 %cvt233}234 235define i64 @fcvtzs_f16_i64_15(half %flt) {236; CHECK-NO16-LABEL: fcvtzs_f16_i64_15:237; CHECK-NO16: // %bb.0:238; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #24239; CHECK-NO16-NEXT: fcvt s0, h0240; CHECK-NO16-NEXT: fmul s0, s0, s1241; CHECK-NO16-NEXT: fcvt h0, s0242; CHECK-NO16-NEXT: fcvt s0, h0243; CHECK-NO16-NEXT: fcvtzs x0, s0244; CHECK-NO16-NEXT: ret245;246; CHECK-SD-FP16-LABEL: fcvtzs_f16_i64_15:247; CHECK-SD-FP16: // %bb.0:248; CHECK-SD-FP16-NEXT: fcvtzs x0, h0, #15249; CHECK-SD-FP16-NEXT: ret250;251; CHECK-GI-FP16-LABEL: fcvtzs_f16_i64_15:252; CHECK-GI-FP16: // %bb.0:253; CHECK-GI-FP16-NEXT: adrp x8, .LCPI11_0254; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI11_0]255; CHECK-GI-FP16-NEXT: fmul h0, h0, h1256; CHECK-GI-FP16-NEXT: fcvtzs x0, h0257; CHECK-GI-FP16-NEXT: ret258 %fix = fmul half %flt, 32768.0259 %cvt = fptosi half %fix to i64260 ret i64 %cvt261}262 263; fptoui264 265define i32 @fcvtzu_f32_i32_7(float %flt) {266; CHECK-SD-LABEL: fcvtzu_f32_i32_7:267; CHECK-SD: // %bb.0:268; CHECK-SD-NEXT: fcvtzu w0, s0, #7269; CHECK-SD-NEXT: ret270;271; CHECK-GI-LABEL: fcvtzu_f32_i32_7:272; CHECK-GI: // %bb.0:273; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24274; CHECK-GI-NEXT: fmul s0, s0, s1275; CHECK-GI-NEXT: fcvtzu w0, s0276; CHECK-GI-NEXT: ret277 %fix = fmul float %flt, 128.0278 %cvt = fptoui float %fix to i32279 ret i32 %cvt280}281 282define i32 @fcvtzu_f32_i32_32(float %flt) {283; CHECK-SD-LABEL: fcvtzu_f32_i32_32:284; CHECK-SD: // %bb.0:285; CHECK-SD-NEXT: fcvtzu w0, s0, #32286; CHECK-SD-NEXT: ret287;288; CHECK-GI-LABEL: fcvtzu_f32_i32_32:289; CHECK-GI: // %bb.0:290; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000291; CHECK-GI-NEXT: fmov s1, w8292; CHECK-GI-NEXT: fmul s0, s0, s1293; CHECK-GI-NEXT: fcvtzu w0, s0294; CHECK-GI-NEXT: ret295 %fix = fmul float %flt, 4294967296.0296 %cvt = fptoui float %fix to i32297 ret i32 %cvt298}299 300define i64 @fcvtzu_f32_i64_7(float %flt) {301; CHECK-SD-LABEL: fcvtzu_f32_i64_7:302; CHECK-SD: // %bb.0:303; CHECK-SD-NEXT: fcvtzu x0, s0, #7304; CHECK-SD-NEXT: ret305;306; CHECK-GI-LABEL: fcvtzu_f32_i64_7:307; CHECK-GI: // %bb.0:308; CHECK-GI-NEXT: movi v1.2s, #67, lsl #24309; CHECK-GI-NEXT: fmul s0, s0, s1310; CHECK-GI-NEXT: fcvtzu x0, s0311; CHECK-GI-NEXT: ret312 %fix = fmul float %flt, 128.0313 %cvt = fptoui float %fix to i64314 ret i64 %cvt315}316 317define i64 @fcvtzu_f32_i64_64(float %flt) {318; CHECK-SD-LABEL: fcvtzu_f32_i64_64:319; CHECK-SD: // %bb.0:320; CHECK-SD-NEXT: fcvtzu x0, s0, #64321; CHECK-SD-NEXT: ret322;323; CHECK-GI-LABEL: fcvtzu_f32_i64_64:324; CHECK-GI: // %bb.0:325; CHECK-GI-NEXT: mov w8, #1602224128 // =0x5f800000326; CHECK-GI-NEXT: fmov s1, w8327; CHECK-GI-NEXT: fmul s0, s0, s1328; CHECK-GI-NEXT: fcvtzu x0, s0329; CHECK-GI-NEXT: ret330 %fix = fmul float %flt, 18446744073709551616.0331 %cvt = fptoui float %fix to i64332 ret i64 %cvt333}334 335define i32 @fcvtzu_f64_i32_7(double %dbl) {336; CHECK-SD-LABEL: fcvtzu_f64_i32_7:337; CHECK-SD: // %bb.0:338; CHECK-SD-NEXT: fcvtzu w0, d0, #7339; CHECK-SD-NEXT: ret340;341; CHECK-GI-LABEL: fcvtzu_f64_i32_7:342; CHECK-GI: // %bb.0:343; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000344; CHECK-GI-NEXT: fmov d1, x8345; CHECK-GI-NEXT: fmul d0, d0, d1346; CHECK-GI-NEXT: fcvtzu w0, d0347; CHECK-GI-NEXT: ret348 %fix = fmul double %dbl, 128.0349 %cvt = fptoui double %fix to i32350 ret i32 %cvt351}352 353define i32 @fcvtzu_f64_i32_32(double %dbl) {354; CHECK-SD-LABEL: fcvtzu_f64_i32_32:355; CHECK-SD: // %bb.0:356; CHECK-SD-NEXT: fcvtzu w0, d0, #32357; CHECK-SD-NEXT: ret358;359; CHECK-GI-LABEL: fcvtzu_f64_i32_32:360; CHECK-GI: // %bb.0:361; CHECK-GI-NEXT: mov x8, #4751297606875873280 // =0x41f0000000000000362; CHECK-GI-NEXT: fmov d1, x8363; CHECK-GI-NEXT: fmul d0, d0, d1364; CHECK-GI-NEXT: fcvtzu w0, d0365; CHECK-GI-NEXT: ret366 %fix = fmul double %dbl, 4294967296.0367 %cvt = fptoui double %fix to i32368 ret i32 %cvt369}370 371define i64 @fcvtzu_f64_i64_7(double %dbl) {372; CHECK-SD-LABEL: fcvtzu_f64_i64_7:373; CHECK-SD: // %bb.0:374; CHECK-SD-NEXT: fcvtzu x0, d0, #7375; CHECK-SD-NEXT: ret376;377; CHECK-GI-LABEL: fcvtzu_f64_i64_7:378; CHECK-GI: // %bb.0:379; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000380; CHECK-GI-NEXT: fmov d1, x8381; CHECK-GI-NEXT: fmul d0, d0, d1382; CHECK-GI-NEXT: fcvtzu x0, d0383; CHECK-GI-NEXT: ret384 %fix = fmul double %dbl, 128.0385 %cvt = fptoui double %fix to i64386 ret i64 %cvt387}388 389define i64 @fcvtzu_f64_i64_64(double %dbl) {390; CHECK-SD-LABEL: fcvtzu_f64_i64_64:391; CHECK-SD: // %bb.0:392; CHECK-SD-NEXT: fcvtzu x0, d0, #64393; CHECK-SD-NEXT: ret394;395; CHECK-GI-LABEL: fcvtzu_f64_i64_64:396; CHECK-GI: // %bb.0:397; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f0000000000000398; CHECK-GI-NEXT: fmov d1, x8399; CHECK-GI-NEXT: fmul d0, d0, d1400; CHECK-GI-NEXT: fcvtzu x0, d0401; CHECK-GI-NEXT: ret402 %fix = fmul double %dbl, 18446744073709551616.0403 %cvt = fptoui double %fix to i64404 ret i64 %cvt405}406 407define i32 @fcvtzu_f16_i32_7(half %flt) {408; CHECK-NO16-LABEL: fcvtzu_f16_i32_7:409; CHECK-NO16: // %bb.0:410; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #24411; CHECK-NO16-NEXT: fcvt s0, h0412; CHECK-NO16-NEXT: fmul s0, s0, s1413; CHECK-NO16-NEXT: fcvt h0, s0414; CHECK-NO16-NEXT: fcvt s0, h0415; CHECK-NO16-NEXT: fcvtzu w0, s0416; CHECK-NO16-NEXT: ret417;418; CHECK-SD-FP16-LABEL: fcvtzu_f16_i32_7:419; CHECK-SD-FP16: // %bb.0:420; CHECK-SD-FP16-NEXT: fcvtzu w0, h0, #7421; CHECK-SD-FP16-NEXT: ret422;423; CHECK-GI-FP16-LABEL: fcvtzu_f16_i32_7:424; CHECK-GI-FP16: // %bb.0:425; CHECK-GI-FP16-NEXT: adrp x8, .LCPI20_0426; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI20_0]427; CHECK-GI-FP16-NEXT: fmul h0, h0, h1428; CHECK-GI-FP16-NEXT: fcvtzu w0, h0429; CHECK-GI-FP16-NEXT: ret430 %fix = fmul half %flt, 128.0431 %cvt = fptoui half %fix to i32432 ret i32 %cvt433}434 435define i32 @fcvtzu_f16_i32_15(half %flt) {436; CHECK-NO16-LABEL: fcvtzu_f16_i32_15:437; CHECK-NO16: // %bb.0:438; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #24439; CHECK-NO16-NEXT: fcvt s0, h0440; CHECK-NO16-NEXT: fmul s0, s0, s1441; CHECK-NO16-NEXT: fcvt h0, s0442; CHECK-NO16-NEXT: fcvt s0, h0443; CHECK-NO16-NEXT: fcvtzu w0, s0444; CHECK-NO16-NEXT: ret445;446; CHECK-SD-FP16-LABEL: fcvtzu_f16_i32_15:447; CHECK-SD-FP16: // %bb.0:448; CHECK-SD-FP16-NEXT: fcvtzu w0, h0, #15449; CHECK-SD-FP16-NEXT: ret450;451; CHECK-GI-FP16-LABEL: fcvtzu_f16_i32_15:452; CHECK-GI-FP16: // %bb.0:453; CHECK-GI-FP16-NEXT: adrp x8, .LCPI21_0454; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI21_0]455; CHECK-GI-FP16-NEXT: fmul h0, h0, h1456; CHECK-GI-FP16-NEXT: fcvtzu w0, h0457; CHECK-GI-FP16-NEXT: ret458 %fix = fmul half %flt, 32768.0459 %cvt = fptoui half %fix to i32460 ret i32 %cvt461}462 463define i64 @fcvtzu_f16_i64_7(half %flt) {464; CHECK-NO16-LABEL: fcvtzu_f16_i64_7:465; CHECK-NO16: // %bb.0:466; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #24467; CHECK-NO16-NEXT: fcvt s0, h0468; CHECK-NO16-NEXT: fmul s0, s0, s1469; CHECK-NO16-NEXT: fcvt h0, s0470; CHECK-NO16-NEXT: fcvt s0, h0471; CHECK-NO16-NEXT: fcvtzu x0, s0472; CHECK-NO16-NEXT: ret473;474; CHECK-SD-FP16-LABEL: fcvtzu_f16_i64_7:475; CHECK-SD-FP16: // %bb.0:476; CHECK-SD-FP16-NEXT: fcvtzu x0, h0, #7477; CHECK-SD-FP16-NEXT: ret478;479; CHECK-GI-FP16-LABEL: fcvtzu_f16_i64_7:480; CHECK-GI-FP16: // %bb.0:481; CHECK-GI-FP16-NEXT: adrp x8, .LCPI22_0482; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI22_0]483; CHECK-GI-FP16-NEXT: fmul h0, h0, h1484; CHECK-GI-FP16-NEXT: fcvtzu x0, h0485; CHECK-GI-FP16-NEXT: ret486 %fix = fmul half %flt, 128.0487 %cvt = fptoui half %fix to i64488 ret i64 %cvt489}490 491define i64 @fcvtzu_f16_i64_15(half %flt) {492; CHECK-NO16-LABEL: fcvtzu_f16_i64_15:493; CHECK-NO16: // %bb.0:494; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #24495; CHECK-NO16-NEXT: fcvt s0, h0496; CHECK-NO16-NEXT: fmul s0, s0, s1497; CHECK-NO16-NEXT: fcvt h0, s0498; CHECK-NO16-NEXT: fcvt s0, h0499; CHECK-NO16-NEXT: fcvtzu x0, s0500; CHECK-NO16-NEXT: ret501;502; CHECK-SD-FP16-LABEL: fcvtzu_f16_i64_15:503; CHECK-SD-FP16: // %bb.0:504; CHECK-SD-FP16-NEXT: fcvtzu x0, h0, #15505; CHECK-SD-FP16-NEXT: ret506;507; CHECK-GI-FP16-LABEL: fcvtzu_f16_i64_15:508; CHECK-GI-FP16: // %bb.0:509; CHECK-GI-FP16-NEXT: adrp x8, .LCPI23_0510; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI23_0]511; CHECK-GI-FP16-NEXT: fmul h0, h0, h1512; CHECK-GI-FP16-NEXT: fcvtzu x0, h0513; CHECK-GI-FP16-NEXT: ret514 %fix = fmul half %flt, 32768.0515 %cvt = fptoui half %fix to i64516 ret i64 %cvt517}518 519; sitofp520 521define float @scvtf_f32_i32_7(i32 %int) {522; CHECK-SD-LABEL: scvtf_f32_i32_7:523; CHECK-SD: // %bb.0:524; CHECK-SD-NEXT: scvtf s0, w0, #7525; CHECK-SD-NEXT: ret526;527; CHECK-GI-LABEL: scvtf_f32_i32_7:528; CHECK-GI: // %bb.0:529; CHECK-GI-NEXT: movi v0.2s, #67, lsl #24530; CHECK-GI-NEXT: scvtf s1, w0531; CHECK-GI-NEXT: fdiv s0, s1, s0532; CHECK-GI-NEXT: ret533 %cvt = sitofp i32 %int to float534 %fix = fdiv float %cvt, 128.0535 ret float %fix536}537 538define float @scvtf_f32_i32_32(i32 %int) {539; CHECK-SD-LABEL: scvtf_f32_i32_32:540; CHECK-SD: // %bb.0:541; CHECK-SD-NEXT: scvtf s0, w0, #32542; CHECK-SD-NEXT: ret543;544; CHECK-GI-LABEL: scvtf_f32_i32_32:545; CHECK-GI: // %bb.0:546; CHECK-GI-NEXT: scvtf s0, w0547; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000548; CHECK-GI-NEXT: fmov s1, w8549; CHECK-GI-NEXT: fdiv s0, s0, s1550; CHECK-GI-NEXT: ret551 %cvt = sitofp i32 %int to float552 %fix = fdiv float %cvt, 4294967296.0553 ret float %fix554}555 556define float @scvtf_f32_i64_7(i64 %long) {557; CHECK-SD-LABEL: scvtf_f32_i64_7:558; CHECK-SD: // %bb.0:559; CHECK-SD-NEXT: scvtf s0, x0, #7560; CHECK-SD-NEXT: ret561;562; CHECK-GI-LABEL: scvtf_f32_i64_7:563; CHECK-GI: // %bb.0:564; CHECK-GI-NEXT: movi v0.2s, #67, lsl #24565; CHECK-GI-NEXT: scvtf s1, x0566; CHECK-GI-NEXT: fdiv s0, s1, s0567; CHECK-GI-NEXT: ret568 %cvt = sitofp i64 %long to float569 %fix = fdiv float %cvt, 128.0570 ret float %fix571}572 573define float @scvtf_f32_i64_64(i64 %long) {574; CHECK-SD-LABEL: scvtf_f32_i64_64:575; CHECK-SD: // %bb.0:576; CHECK-SD-NEXT: scvtf s0, x0, #64577; CHECK-SD-NEXT: ret578;579; CHECK-GI-LABEL: scvtf_f32_i64_64:580; CHECK-GI: // %bb.0:581; CHECK-GI-NEXT: scvtf s0, x0582; CHECK-GI-NEXT: mov w8, #1602224128 // =0x5f800000583; CHECK-GI-NEXT: fmov s1, w8584; CHECK-GI-NEXT: fdiv s0, s0, s1585; CHECK-GI-NEXT: ret586 %cvt = sitofp i64 %long to float587 %fix = fdiv float %cvt, 18446744073709551616.0588 ret float %fix589}590 591define double @scvtf_f64_i32_7(i32 %int) {592; CHECK-SD-LABEL: scvtf_f64_i32_7:593; CHECK-SD: // %bb.0:594; CHECK-SD-NEXT: scvtf d0, w0, #7595; CHECK-SD-NEXT: ret596;597; CHECK-GI-LABEL: scvtf_f64_i32_7:598; CHECK-GI: // %bb.0:599; CHECK-GI-NEXT: scvtf d0, w0600; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000601; CHECK-GI-NEXT: fmov d1, x8602; CHECK-GI-NEXT: fdiv d0, d0, d1603; CHECK-GI-NEXT: ret604 %cvt = sitofp i32 %int to double605 %fix = fdiv double %cvt, 128.0606 ret double %fix607}608 609define double @scvtf_f64_i32_32(i32 %int) {610; CHECK-SD-LABEL: scvtf_f64_i32_32:611; CHECK-SD: // %bb.0:612; CHECK-SD-NEXT: scvtf d0, w0, #32613; CHECK-SD-NEXT: ret614;615; CHECK-GI-LABEL: scvtf_f64_i32_32:616; CHECK-GI: // %bb.0:617; CHECK-GI-NEXT: scvtf d0, w0618; CHECK-GI-NEXT: mov x8, #4751297606875873280 // =0x41f0000000000000619; CHECK-GI-NEXT: fmov d1, x8620; CHECK-GI-NEXT: fdiv d0, d0, d1621; CHECK-GI-NEXT: ret622 %cvt = sitofp i32 %int to double623 %fix = fdiv double %cvt, 4294967296.0624 ret double %fix625}626 627define double @scvtf_f64_i64_7(i64 %long) {628; CHECK-SD-LABEL: scvtf_f64_i64_7:629; CHECK-SD: // %bb.0:630; CHECK-SD-NEXT: scvtf d0, x0, #7631; CHECK-SD-NEXT: ret632;633; CHECK-GI-LABEL: scvtf_f64_i64_7:634; CHECK-GI: // %bb.0:635; CHECK-GI-NEXT: scvtf d0, x0636; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000637; CHECK-GI-NEXT: fmov d1, x8638; CHECK-GI-NEXT: fdiv d0, d0, d1639; CHECK-GI-NEXT: ret640 %cvt = sitofp i64 %long to double641 %fix = fdiv double %cvt, 128.0642 ret double %fix643}644 645define double @scvtf_f64_i64_64(i64 %long) {646; CHECK-SD-LABEL: scvtf_f64_i64_64:647; CHECK-SD: // %bb.0:648; CHECK-SD-NEXT: scvtf d0, x0, #64649; CHECK-SD-NEXT: ret650;651; CHECK-GI-LABEL: scvtf_f64_i64_64:652; CHECK-GI: // %bb.0:653; CHECK-GI-NEXT: scvtf d0, x0654; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f0000000000000655; CHECK-GI-NEXT: fmov d1, x8656; CHECK-GI-NEXT: fdiv d0, d0, d1657; CHECK-GI-NEXT: ret658 %cvt = sitofp i64 %long to double659 %fix = fdiv double %cvt, 18446744073709551616.0660 ret double %fix661}662 663define half @scvtf_f16_i32_7(i32 %int) {664; CHECK-SD-NO16-LABEL: scvtf_f16_i32_7:665; CHECK-SD-NO16: // %bb.0:666; CHECK-SD-NO16-NEXT: scvtf s1, w0667; CHECK-SD-NO16-NEXT: movi v0.2s, #60, lsl #24668; CHECK-SD-NO16-NEXT: fcvt h1, s1669; CHECK-SD-NO16-NEXT: fcvt s1, h1670; CHECK-SD-NO16-NEXT: fmul s0, s1, s0671; CHECK-SD-NO16-NEXT: fcvt h0, s0672; CHECK-SD-NO16-NEXT: ret673;674; CHECK-SD-FP16-LABEL: scvtf_f16_i32_7:675; CHECK-SD-FP16: // %bb.0:676; CHECK-SD-FP16-NEXT: scvtf h0, w0, #7677; CHECK-SD-FP16-NEXT: ret678;679; CHECK-GI-NO16-LABEL: scvtf_f16_i32_7:680; CHECK-GI-NO16: // %bb.0:681; CHECK-GI-NO16-NEXT: scvtf s1, w0682; CHECK-GI-NO16-NEXT: movi v0.2s, #67, lsl #24683; CHECK-GI-NO16-NEXT: fcvt h1, s1684; CHECK-GI-NO16-NEXT: fcvt s1, h1685; CHECK-GI-NO16-NEXT: fdiv s0, s1, s0686; CHECK-GI-NO16-NEXT: fcvt h0, s0687; CHECK-GI-NO16-NEXT: ret688;689; CHECK-GI-FP16-LABEL: scvtf_f16_i32_7:690; CHECK-GI-FP16: // %bb.0:691; CHECK-GI-FP16-NEXT: scvtf h0, w0692; CHECK-GI-FP16-NEXT: adrp x8, .LCPI32_0693; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI32_0]694; CHECK-GI-FP16-NEXT: fdiv h0, h0, h1695; CHECK-GI-FP16-NEXT: ret696 %cvt = sitofp i32 %int to half697 %fix = fdiv half %cvt, 128.0698 ret half %fix699}700 701define half @scvtf_f16_i32_15(i32 %int) {702; CHECK-SD-NO16-LABEL: scvtf_f16_i32_15:703; CHECK-SD-NO16: // %bb.0:704; CHECK-SD-NO16-NEXT: scvtf s1, w0705; CHECK-SD-NO16-NEXT: movi v0.2s, #56, lsl #24706; CHECK-SD-NO16-NEXT: fcvt h1, s1707; CHECK-SD-NO16-NEXT: fcvt s1, h1708; CHECK-SD-NO16-NEXT: fmul s0, s1, s0709; CHECK-SD-NO16-NEXT: fcvt h0, s0710; CHECK-SD-NO16-NEXT: ret711;712; CHECK-SD-FP16-LABEL: scvtf_f16_i32_15:713; CHECK-SD-FP16: // %bb.0:714; CHECK-SD-FP16-NEXT: scvtf h0, w0, #15715; CHECK-SD-FP16-NEXT: ret716;717; CHECK-GI-NO16-LABEL: scvtf_f16_i32_15:718; CHECK-GI-NO16: // %bb.0:719; CHECK-GI-NO16-NEXT: scvtf s1, w0720; CHECK-GI-NO16-NEXT: movi v0.2s, #71, lsl #24721; CHECK-GI-NO16-NEXT: fcvt h1, s1722; CHECK-GI-NO16-NEXT: fcvt s1, h1723; CHECK-GI-NO16-NEXT: fdiv s0, s1, s0724; CHECK-GI-NO16-NEXT: fcvt h0, s0725; CHECK-GI-NO16-NEXT: ret726;727; CHECK-GI-FP16-LABEL: scvtf_f16_i32_15:728; CHECK-GI-FP16: // %bb.0:729; CHECK-GI-FP16-NEXT: scvtf h0, w0730; CHECK-GI-FP16-NEXT: adrp x8, .LCPI33_0731; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI33_0]732; CHECK-GI-FP16-NEXT: fdiv h0, h0, h1733; CHECK-GI-FP16-NEXT: ret734 %cvt = sitofp i32 %int to half735 %fix = fdiv half %cvt, 32768.0736 ret half %fix737}738 739define half @scvtf_f16_i64_7(i64 %long) {740; CHECK-SD-NO16-LABEL: scvtf_f16_i64_7:741; CHECK-SD-NO16: // %bb.0:742; CHECK-SD-NO16-NEXT: scvtf s1, x0743; CHECK-SD-NO16-NEXT: movi v0.2s, #60, lsl #24744; CHECK-SD-NO16-NEXT: fcvt h1, s1745; CHECK-SD-NO16-NEXT: fcvt s1, h1746; CHECK-SD-NO16-NEXT: fmul s0, s1, s0747; CHECK-SD-NO16-NEXT: fcvt h0, s0748; CHECK-SD-NO16-NEXT: ret749;750; CHECK-SD-FP16-LABEL: scvtf_f16_i64_7:751; CHECK-SD-FP16: // %bb.0:752; CHECK-SD-FP16-NEXT: scvtf h0, x0, #7753; CHECK-SD-FP16-NEXT: ret754;755; CHECK-GI-NO16-LABEL: scvtf_f16_i64_7:756; CHECK-GI-NO16: // %bb.0:757; CHECK-GI-NO16-NEXT: scvtf s1, x0758; CHECK-GI-NO16-NEXT: movi v0.2s, #67, lsl #24759; CHECK-GI-NO16-NEXT: fcvt h1, s1760; CHECK-GI-NO16-NEXT: fcvt s1, h1761; CHECK-GI-NO16-NEXT: fdiv s0, s1, s0762; CHECK-GI-NO16-NEXT: fcvt h0, s0763; CHECK-GI-NO16-NEXT: ret764;765; CHECK-GI-FP16-LABEL: scvtf_f16_i64_7:766; CHECK-GI-FP16: // %bb.0:767; CHECK-GI-FP16-NEXT: scvtf h0, x0768; CHECK-GI-FP16-NEXT: adrp x8, .LCPI34_0769; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI34_0]770; CHECK-GI-FP16-NEXT: fdiv h0, h0, h1771; CHECK-GI-FP16-NEXT: ret772 %cvt = sitofp i64 %long to half773 %fix = fdiv half %cvt, 128.0774 ret half %fix775}776 777define half @scvtf_f16_i64_15(i64 %long) {778; CHECK-SD-NO16-LABEL: scvtf_f16_i64_15:779; CHECK-SD-NO16: // %bb.0:780; CHECK-SD-NO16-NEXT: scvtf s1, x0781; CHECK-SD-NO16-NEXT: movi v0.2s, #56, lsl #24782; CHECK-SD-NO16-NEXT: fcvt h1, s1783; CHECK-SD-NO16-NEXT: fcvt s1, h1784; CHECK-SD-NO16-NEXT: fmul s0, s1, s0785; CHECK-SD-NO16-NEXT: fcvt h0, s0786; CHECK-SD-NO16-NEXT: ret787;788; CHECK-SD-FP16-LABEL: scvtf_f16_i64_15:789; CHECK-SD-FP16: // %bb.0:790; CHECK-SD-FP16-NEXT: scvtf h0, x0, #15791; CHECK-SD-FP16-NEXT: ret792;793; CHECK-GI-NO16-LABEL: scvtf_f16_i64_15:794; CHECK-GI-NO16: // %bb.0:795; CHECK-GI-NO16-NEXT: scvtf s1, x0796; CHECK-GI-NO16-NEXT: movi v0.2s, #71, lsl #24797; CHECK-GI-NO16-NEXT: fcvt h1, s1798; CHECK-GI-NO16-NEXT: fcvt s1, h1799; CHECK-GI-NO16-NEXT: fdiv s0, s1, s0800; CHECK-GI-NO16-NEXT: fcvt h0, s0801; CHECK-GI-NO16-NEXT: ret802;803; CHECK-GI-FP16-LABEL: scvtf_f16_i64_15:804; CHECK-GI-FP16: // %bb.0:805; CHECK-GI-FP16-NEXT: scvtf h0, x0806; CHECK-GI-FP16-NEXT: adrp x8, .LCPI35_0807; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI35_0]808; CHECK-GI-FP16-NEXT: fdiv h0, h0, h1809; CHECK-GI-FP16-NEXT: ret810 %cvt = sitofp i64 %long to half811 %fix = fdiv half %cvt, 32768.0812 ret half %fix813}814 815; uitofp816 817define float @ucvtf_f32_i32_7(i32 %int) {818; CHECK-SD-LABEL: ucvtf_f32_i32_7:819; CHECK-SD: // %bb.0:820; CHECK-SD-NEXT: ucvtf s0, w0, #7821; CHECK-SD-NEXT: ret822;823; CHECK-GI-LABEL: ucvtf_f32_i32_7:824; CHECK-GI: // %bb.0:825; CHECK-GI-NEXT: movi v0.2s, #67, lsl #24826; CHECK-GI-NEXT: ucvtf s1, w0827; CHECK-GI-NEXT: fdiv s0, s1, s0828; CHECK-GI-NEXT: ret829 %cvt = uitofp i32 %int to float830 %fix = fdiv float %cvt, 128.0831 ret float %fix832}833 834define float @ucvtf_f32_i32_32(i32 %int) {835; CHECK-SD-LABEL: ucvtf_f32_i32_32:836; CHECK-SD: // %bb.0:837; CHECK-SD-NEXT: ucvtf s0, w0, #32838; CHECK-SD-NEXT: ret839;840; CHECK-GI-LABEL: ucvtf_f32_i32_32:841; CHECK-GI: // %bb.0:842; CHECK-GI-NEXT: ucvtf s0, w0843; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000844; CHECK-GI-NEXT: fmov s1, w8845; CHECK-GI-NEXT: fdiv s0, s0, s1846; CHECK-GI-NEXT: ret847 %cvt = uitofp i32 %int to float848 %fix = fdiv float %cvt, 4294967296.0849 ret float %fix850}851 852define float @ucvtf_f32_i64_7(i64 %long) {853; CHECK-SD-LABEL: ucvtf_f32_i64_7:854; CHECK-SD: // %bb.0:855; CHECK-SD-NEXT: ucvtf s0, x0, #7856; CHECK-SD-NEXT: ret857;858; CHECK-GI-LABEL: ucvtf_f32_i64_7:859; CHECK-GI: // %bb.0:860; CHECK-GI-NEXT: movi v0.2s, #67, lsl #24861; CHECK-GI-NEXT: ucvtf s1, x0862; CHECK-GI-NEXT: fdiv s0, s1, s0863; CHECK-GI-NEXT: ret864 %cvt = uitofp i64 %long to float865 %fix = fdiv float %cvt, 128.0866 ret float %fix867}868 869define float @ucvtf_f32_i64_64(i64 %long) {870; CHECK-SD-LABEL: ucvtf_f32_i64_64:871; CHECK-SD: // %bb.0:872; CHECK-SD-NEXT: ucvtf s0, x0, #64873; CHECK-SD-NEXT: ret874;875; CHECK-GI-LABEL: ucvtf_f32_i64_64:876; CHECK-GI: // %bb.0:877; CHECK-GI-NEXT: ucvtf s0, x0878; CHECK-GI-NEXT: mov w8, #1602224128 // =0x5f800000879; CHECK-GI-NEXT: fmov s1, w8880; CHECK-GI-NEXT: fdiv s0, s0, s1881; CHECK-GI-NEXT: ret882 %cvt = uitofp i64 %long to float883 %fix = fdiv float %cvt, 18446744073709551616.0884 ret float %fix885}886 887define double @ucvtf_f64_i32_7(i32 %int) {888; CHECK-SD-LABEL: ucvtf_f64_i32_7:889; CHECK-SD: // %bb.0:890; CHECK-SD-NEXT: ucvtf d0, w0, #7891; CHECK-SD-NEXT: ret892;893; CHECK-GI-LABEL: ucvtf_f64_i32_7:894; CHECK-GI: // %bb.0:895; CHECK-GI-NEXT: ucvtf d0, w0896; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000897; CHECK-GI-NEXT: fmov d1, x8898; CHECK-GI-NEXT: fdiv d0, d0, d1899; CHECK-GI-NEXT: ret900 %cvt = uitofp i32 %int to double901 %fix = fdiv double %cvt, 128.0902 ret double %fix903}904 905define double @ucvtf_f64_i32_32(i32 %int) {906; CHECK-SD-LABEL: ucvtf_f64_i32_32:907; CHECK-SD: // %bb.0:908; CHECK-SD-NEXT: ucvtf d0, w0, #32909; CHECK-SD-NEXT: ret910;911; CHECK-GI-LABEL: ucvtf_f64_i32_32:912; CHECK-GI: // %bb.0:913; CHECK-GI-NEXT: ucvtf d0, w0914; CHECK-GI-NEXT: mov x8, #4751297606875873280 // =0x41f0000000000000915; CHECK-GI-NEXT: fmov d1, x8916; CHECK-GI-NEXT: fdiv d0, d0, d1917; CHECK-GI-NEXT: ret918 %cvt = uitofp i32 %int to double919 %fix = fdiv double %cvt, 4294967296.0920 ret double %fix921}922 923define double @ucvtf_f64_i64_7(i64 %long) {924; CHECK-SD-LABEL: ucvtf_f64_i64_7:925; CHECK-SD: // %bb.0:926; CHECK-SD-NEXT: ucvtf d0, x0, #7927; CHECK-SD-NEXT: ret928;929; CHECK-GI-LABEL: ucvtf_f64_i64_7:930; CHECK-GI: // %bb.0:931; CHECK-GI-NEXT: ucvtf d0, x0932; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x4060000000000000933; CHECK-GI-NEXT: fmov d1, x8934; CHECK-GI-NEXT: fdiv d0, d0, d1935; CHECK-GI-NEXT: ret936 %cvt = uitofp i64 %long to double937 %fix = fdiv double %cvt, 128.0938 ret double %fix939}940 941define double @ucvtf_f64_i64_64(i64 %long) {942; CHECK-SD-LABEL: ucvtf_f64_i64_64:943; CHECK-SD: // %bb.0:944; CHECK-SD-NEXT: ucvtf d0, x0, #64945; CHECK-SD-NEXT: ret946;947; CHECK-GI-LABEL: ucvtf_f64_i64_64:948; CHECK-GI: // %bb.0:949; CHECK-GI-NEXT: ucvtf d0, x0950; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f0000000000000951; CHECK-GI-NEXT: fmov d1, x8952; CHECK-GI-NEXT: fdiv d0, d0, d1953; CHECK-GI-NEXT: ret954 %cvt = uitofp i64 %long to double955 %fix = fdiv double %cvt, 18446744073709551616.0956 ret double %fix957}958 959define half @ucvtf_f16_i32_7(i32 %int) {960; CHECK-SD-NO16-LABEL: ucvtf_f16_i32_7:961; CHECK-SD-NO16: // %bb.0:962; CHECK-SD-NO16-NEXT: ucvtf s1, w0963; CHECK-SD-NO16-NEXT: movi v0.2s, #60, lsl #24964; CHECK-SD-NO16-NEXT: fcvt h1, s1965; CHECK-SD-NO16-NEXT: fcvt s1, h1966; CHECK-SD-NO16-NEXT: fmul s0, s1, s0967; CHECK-SD-NO16-NEXT: fcvt h0, s0968; CHECK-SD-NO16-NEXT: ret969;970; CHECK-SD-FP16-LABEL: ucvtf_f16_i32_7:971; CHECK-SD-FP16: // %bb.0:972; CHECK-SD-FP16-NEXT: ucvtf h0, w0, #7973; CHECK-SD-FP16-NEXT: ret974;975; CHECK-GI-NO16-LABEL: ucvtf_f16_i32_7:976; CHECK-GI-NO16: // %bb.0:977; CHECK-GI-NO16-NEXT: ucvtf s1, w0978; CHECK-GI-NO16-NEXT: movi v0.2s, #67, lsl #24979; CHECK-GI-NO16-NEXT: fcvt h1, s1980; CHECK-GI-NO16-NEXT: fcvt s1, h1981; CHECK-GI-NO16-NEXT: fdiv s0, s1, s0982; CHECK-GI-NO16-NEXT: fcvt h0, s0983; CHECK-GI-NO16-NEXT: ret984;985; CHECK-GI-FP16-LABEL: ucvtf_f16_i32_7:986; CHECK-GI-FP16: // %bb.0:987; CHECK-GI-FP16-NEXT: ucvtf h0, w0988; CHECK-GI-FP16-NEXT: adrp x8, .LCPI44_0989; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI44_0]990; CHECK-GI-FP16-NEXT: fdiv h0, h0, h1991; CHECK-GI-FP16-NEXT: ret992 %cvt = uitofp i32 %int to half993 %fix = fdiv half %cvt, 128.0994 ret half %fix995}996 997define half @ucvtf_f16_i32_15(i32 %int) {998; CHECK-SD-NO16-LABEL: ucvtf_f16_i32_15:999; CHECK-SD-NO16: // %bb.0:1000; CHECK-SD-NO16-NEXT: ucvtf s1, w01001; CHECK-SD-NO16-NEXT: movi v0.2s, #56, lsl #241002; CHECK-SD-NO16-NEXT: fcvt h1, s11003; CHECK-SD-NO16-NEXT: fcvt s1, h11004; CHECK-SD-NO16-NEXT: fmul s0, s1, s01005; CHECK-SD-NO16-NEXT: fcvt h0, s01006; CHECK-SD-NO16-NEXT: ret1007;1008; CHECK-SD-FP16-LABEL: ucvtf_f16_i32_15:1009; CHECK-SD-FP16: // %bb.0:1010; CHECK-SD-FP16-NEXT: ucvtf h0, w0, #151011; CHECK-SD-FP16-NEXT: ret1012;1013; CHECK-GI-NO16-LABEL: ucvtf_f16_i32_15:1014; CHECK-GI-NO16: // %bb.0:1015; CHECK-GI-NO16-NEXT: ucvtf s1, w01016; CHECK-GI-NO16-NEXT: movi v0.2s, #71, lsl #241017; CHECK-GI-NO16-NEXT: fcvt h1, s11018; CHECK-GI-NO16-NEXT: fcvt s1, h11019; CHECK-GI-NO16-NEXT: fdiv s0, s1, s01020; CHECK-GI-NO16-NEXT: fcvt h0, s01021; CHECK-GI-NO16-NEXT: ret1022;1023; CHECK-GI-FP16-LABEL: ucvtf_f16_i32_15:1024; CHECK-GI-FP16: // %bb.0:1025; CHECK-GI-FP16-NEXT: ucvtf h0, w01026; CHECK-GI-FP16-NEXT: adrp x8, .LCPI45_01027; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI45_0]1028; CHECK-GI-FP16-NEXT: fdiv h0, h0, h11029; CHECK-GI-FP16-NEXT: ret1030 %cvt = uitofp i32 %int to half1031 %fix = fdiv half %cvt, 32768.01032 ret half %fix1033}1034 1035define half @ucvtf_f16_i64_7(i64 %long) {1036; CHECK-SD-NO16-LABEL: ucvtf_f16_i64_7:1037; CHECK-SD-NO16: // %bb.0:1038; CHECK-SD-NO16-NEXT: ucvtf s1, x01039; CHECK-SD-NO16-NEXT: movi v0.2s, #60, lsl #241040; CHECK-SD-NO16-NEXT: fcvt h1, s11041; CHECK-SD-NO16-NEXT: fcvt s1, h11042; CHECK-SD-NO16-NEXT: fmul s0, s1, s01043; CHECK-SD-NO16-NEXT: fcvt h0, s01044; CHECK-SD-NO16-NEXT: ret1045;1046; CHECK-SD-FP16-LABEL: ucvtf_f16_i64_7:1047; CHECK-SD-FP16: // %bb.0:1048; CHECK-SD-FP16-NEXT: ucvtf h0, x0, #71049; CHECK-SD-FP16-NEXT: ret1050;1051; CHECK-GI-NO16-LABEL: ucvtf_f16_i64_7:1052; CHECK-GI-NO16: // %bb.0:1053; CHECK-GI-NO16-NEXT: ucvtf s1, x01054; CHECK-GI-NO16-NEXT: movi v0.2s, #67, lsl #241055; CHECK-GI-NO16-NEXT: fcvt h1, s11056; CHECK-GI-NO16-NEXT: fcvt s1, h11057; CHECK-GI-NO16-NEXT: fdiv s0, s1, s01058; CHECK-GI-NO16-NEXT: fcvt h0, s01059; CHECK-GI-NO16-NEXT: ret1060;1061; CHECK-GI-FP16-LABEL: ucvtf_f16_i64_7:1062; CHECK-GI-FP16: // %bb.0:1063; CHECK-GI-FP16-NEXT: ucvtf h0, x01064; CHECK-GI-FP16-NEXT: adrp x8, .LCPI46_01065; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI46_0]1066; CHECK-GI-FP16-NEXT: fdiv h0, h0, h11067; CHECK-GI-FP16-NEXT: ret1068 %cvt = uitofp i64 %long to half1069 %fix = fdiv half %cvt, 128.01070 ret half %fix1071}1072 1073define half @ucvtf_f16_i64_15(i64 %long) {1074; CHECK-SD-NO16-LABEL: ucvtf_f16_i64_15:1075; CHECK-SD-NO16: // %bb.0:1076; CHECK-SD-NO16-NEXT: ucvtf s1, x01077; CHECK-SD-NO16-NEXT: movi v0.2s, #56, lsl #241078; CHECK-SD-NO16-NEXT: fcvt h1, s11079; CHECK-SD-NO16-NEXT: fcvt s1, h11080; CHECK-SD-NO16-NEXT: fmul s0, s1, s01081; CHECK-SD-NO16-NEXT: fcvt h0, s01082; CHECK-SD-NO16-NEXT: ret1083;1084; CHECK-SD-FP16-LABEL: ucvtf_f16_i64_15:1085; CHECK-SD-FP16: // %bb.0:1086; CHECK-SD-FP16-NEXT: ucvtf h0, x0, #151087; CHECK-SD-FP16-NEXT: ret1088;1089; CHECK-GI-NO16-LABEL: ucvtf_f16_i64_15:1090; CHECK-GI-NO16: // %bb.0:1091; CHECK-GI-NO16-NEXT: ucvtf s1, x01092; CHECK-GI-NO16-NEXT: movi v0.2s, #71, lsl #241093; CHECK-GI-NO16-NEXT: fcvt h1, s11094; CHECK-GI-NO16-NEXT: fcvt s1, h11095; CHECK-GI-NO16-NEXT: fdiv s0, s1, s01096; CHECK-GI-NO16-NEXT: fcvt h0, s01097; CHECK-GI-NO16-NEXT: ret1098;1099; CHECK-GI-FP16-LABEL: ucvtf_f16_i64_15:1100; CHECK-GI-FP16: // %bb.0:1101; CHECK-GI-FP16-NEXT: ucvtf h0, x01102; CHECK-GI-FP16-NEXT: adrp x8, .LCPI47_01103; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI47_0]1104; CHECK-GI-FP16-NEXT: fdiv h0, h0, h11105; CHECK-GI-FP16-NEXT: ret1106 %cvt = uitofp i64 %long to half1107 %fix = fdiv half %cvt, 32768.01108 ret half %fix1109}1110 1111 1112; fptoui.sat1113 1114declare i32 @llvm.fptosi.sat.i32.f32(float)1115declare i64 @llvm.fptosi.sat.i64.f32(float)1116declare i32 @llvm.fptosi.sat.i32.f64(double)1117declare i64 @llvm.fptosi.sat.i64.f64(double)1118declare i32 @llvm.fptosi.sat.i32.f16(half)1119declare i64 @llvm.fptosi.sat.i64.f16(half)1120 1121define i32 @fcvtzs_sat_f32_i32_7(float %flt) {1122; CHECK-SD-LABEL: fcvtzs_sat_f32_i32_7:1123; CHECK-SD: // %bb.0:1124; CHECK-SD-NEXT: fcvtzs w0, s0, #71125; CHECK-SD-NEXT: ret1126;1127; CHECK-GI-LABEL: fcvtzs_sat_f32_i32_7:1128; CHECK-GI: // %bb.0:1129; CHECK-GI-NEXT: movi v1.2s, #67, lsl #241130; CHECK-GI-NEXT: fmul s0, s0, s11131; CHECK-GI-NEXT: fcvtzs w0, s01132; CHECK-GI-NEXT: ret1133 %fix = fmul float %flt, 128.01134 %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)1135 ret i32 %cvt1136}1137 1138define i32 @fcvtzs_sat_f32_i32_32(float %flt) {1139; CHECK-SD-LABEL: fcvtzs_sat_f32_i32_32:1140; CHECK-SD: // %bb.0:1141; CHECK-SD-NEXT: fcvtzs w0, s0, #321142; CHECK-SD-NEXT: ret1143;1144; CHECK-GI-LABEL: fcvtzs_sat_f32_i32_32:1145; CHECK-GI: // %bb.0:1146; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f8000001147; CHECK-GI-NEXT: fmov s1, w81148; CHECK-GI-NEXT: fmul s0, s0, s11149; CHECK-GI-NEXT: fcvtzs w0, s01150; CHECK-GI-NEXT: ret1151 %fix = fmul float %flt, 4294967296.01152 %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)1153 ret i32 %cvt1154}1155 1156define i64 @fcvtzs_sat_f32_i64_64(float %flt) {1157; CHECK-SD-LABEL: fcvtzs_sat_f32_i64_64:1158; CHECK-SD: // %bb.0:1159; CHECK-SD-NEXT: fcvtzs x0, s0, #641160; CHECK-SD-NEXT: ret1161;1162; CHECK-GI-LABEL: fcvtzs_sat_f32_i64_64:1163; CHECK-GI: // %bb.0:1164; CHECK-GI-NEXT: mov w8, #1602224128 // =0x5f8000001165; CHECK-GI-NEXT: fmov s1, w81166; CHECK-GI-NEXT: fmul s0, s0, s11167; CHECK-GI-NEXT: fcvtzs x0, s01168; CHECK-GI-NEXT: ret1169 %fix = fmul float %flt, 18446744073709551616.01170 %cvt = call i64 @llvm.fptosi.sat.i64.f32(float %fix)1171 ret i64 %cvt1172}1173 1174define i32 @fcvtzs_sat_f64_i32_7(double %dbl) {1175; CHECK-SD-LABEL: fcvtzs_sat_f64_i32_7:1176; CHECK-SD: // %bb.0:1177; CHECK-SD-NEXT: fcvtzs w0, d0, #71178; CHECK-SD-NEXT: ret1179;1180; CHECK-GI-LABEL: fcvtzs_sat_f64_i32_7:1181; CHECK-GI: // %bb.0:1182; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x40600000000000001183; CHECK-GI-NEXT: fmov d1, x81184; CHECK-GI-NEXT: fmul d0, d0, d11185; CHECK-GI-NEXT: fcvtzs w0, d01186; CHECK-GI-NEXT: ret1187 %fix = fmul double %dbl, 128.01188 %cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)1189 ret i32 %cvt1190}1191 1192define i32 @fcvtzs_sat_f64_i32_32(double %dbl) {1193; CHECK-SD-LABEL: fcvtzs_sat_f64_i32_32:1194; CHECK-SD: // %bb.0:1195; CHECK-SD-NEXT: fcvtzs w0, d0, #321196; CHECK-SD-NEXT: ret1197;1198; CHECK-GI-LABEL: fcvtzs_sat_f64_i32_32:1199; CHECK-GI: // %bb.0:1200; CHECK-GI-NEXT: mov x8, #4751297606875873280 // =0x41f00000000000001201; CHECK-GI-NEXT: fmov d1, x81202; CHECK-GI-NEXT: fmul d0, d0, d11203; CHECK-GI-NEXT: fcvtzs w0, d01204; CHECK-GI-NEXT: ret1205 %fix = fmul double %dbl, 4294967296.01206 %cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)1207 ret i32 %cvt1208}1209 1210define i64 @fcvtzs_sat_f64_i64_7(double %dbl) {1211; CHECK-SD-LABEL: fcvtzs_sat_f64_i64_7:1212; CHECK-SD: // %bb.0:1213; CHECK-SD-NEXT: fcvtzs x0, d0, #71214; CHECK-SD-NEXT: ret1215;1216; CHECK-GI-LABEL: fcvtzs_sat_f64_i64_7:1217; CHECK-GI: // %bb.0:1218; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x40600000000000001219; CHECK-GI-NEXT: fmov d1, x81220; CHECK-GI-NEXT: fmul d0, d0, d11221; CHECK-GI-NEXT: fcvtzs x0, d01222; CHECK-GI-NEXT: ret1223 %fix = fmul double %dbl, 128.01224 %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)1225 ret i64 %cvt1226}1227 1228define i64 @fcvtzs_sat_f64_i64_64(double %dbl) {1229; CHECK-SD-LABEL: fcvtzs_sat_f64_i64_64:1230; CHECK-SD: // %bb.0:1231; CHECK-SD-NEXT: fcvtzs x0, d0, #641232; CHECK-SD-NEXT: ret1233;1234; CHECK-GI-LABEL: fcvtzs_sat_f64_i64_64:1235; CHECK-GI: // %bb.0:1236; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f00000000000001237; CHECK-GI-NEXT: fmov d1, x81238; CHECK-GI-NEXT: fmul d0, d0, d11239; CHECK-GI-NEXT: fcvtzs x0, d01240; CHECK-GI-NEXT: ret1241 %fix = fmul double %dbl, 18446744073709551616.01242 %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)1243 ret i64 %cvt1244}1245 1246define i32 @fcvtzs_sat_f16_i32_7(half %dbl) {1247; CHECK-NO16-LABEL: fcvtzs_sat_f16_i32_7:1248; CHECK-NO16: // %bb.0:1249; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #241250; CHECK-NO16-NEXT: fcvt s0, h01251; CHECK-NO16-NEXT: fmul s0, s0, s11252; CHECK-NO16-NEXT: fcvt h0, s01253; CHECK-NO16-NEXT: fcvt s0, h01254; CHECK-NO16-NEXT: fcvtzs w0, s01255; CHECK-NO16-NEXT: ret1256;1257; CHECK-SD-FP16-LABEL: fcvtzs_sat_f16_i32_7:1258; CHECK-SD-FP16: // %bb.0:1259; CHECK-SD-FP16-NEXT: fcvtzs w0, h0, #71260; CHECK-SD-FP16-NEXT: ret1261;1262; CHECK-GI-FP16-LABEL: fcvtzs_sat_f16_i32_7:1263; CHECK-GI-FP16: // %bb.0:1264; CHECK-GI-FP16-NEXT: adrp x8, .LCPI55_01265; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI55_0]1266; CHECK-GI-FP16-NEXT: fmul h0, h0, h11267; CHECK-GI-FP16-NEXT: fcvtzs w0, h01268; CHECK-GI-FP16-NEXT: ret1269 %fix = fmul half %dbl, 128.01270 %cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)1271 ret i32 %cvt1272}1273 1274define i32 @fcvtzs_sat_f16_i32_15(half %dbl) {1275; CHECK-NO16-LABEL: fcvtzs_sat_f16_i32_15:1276; CHECK-NO16: // %bb.0:1277; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #241278; CHECK-NO16-NEXT: fcvt s0, h01279; CHECK-NO16-NEXT: fmul s0, s0, s11280; CHECK-NO16-NEXT: fcvt h0, s01281; CHECK-NO16-NEXT: fcvt s0, h01282; CHECK-NO16-NEXT: fcvtzs w0, s01283; CHECK-NO16-NEXT: ret1284;1285; CHECK-SD-FP16-LABEL: fcvtzs_sat_f16_i32_15:1286; CHECK-SD-FP16: // %bb.0:1287; CHECK-SD-FP16-NEXT: fcvtzs w0, h0, #151288; CHECK-SD-FP16-NEXT: ret1289;1290; CHECK-GI-FP16-LABEL: fcvtzs_sat_f16_i32_15:1291; CHECK-GI-FP16: // %bb.0:1292; CHECK-GI-FP16-NEXT: adrp x8, .LCPI56_01293; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI56_0]1294; CHECK-GI-FP16-NEXT: fmul h0, h0, h11295; CHECK-GI-FP16-NEXT: fcvtzs w0, h01296; CHECK-GI-FP16-NEXT: ret1297 %fix = fmul half %dbl, 32768.01298 %cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)1299 ret i32 %cvt1300}1301 1302define i64 @fcvtzs_sat_f16_i64_7(half %dbl) {1303; CHECK-NO16-LABEL: fcvtzs_sat_f16_i64_7:1304; CHECK-NO16: // %bb.0:1305; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #241306; CHECK-NO16-NEXT: fcvt s0, h01307; CHECK-NO16-NEXT: fmul s0, s0, s11308; CHECK-NO16-NEXT: fcvt h0, s01309; CHECK-NO16-NEXT: fcvt s0, h01310; CHECK-NO16-NEXT: fcvtzs x0, s01311; CHECK-NO16-NEXT: ret1312;1313; CHECK-SD-FP16-LABEL: fcvtzs_sat_f16_i64_7:1314; CHECK-SD-FP16: // %bb.0:1315; CHECK-SD-FP16-NEXT: fcvtzs x0, h0, #71316; CHECK-SD-FP16-NEXT: ret1317;1318; CHECK-GI-FP16-LABEL: fcvtzs_sat_f16_i64_7:1319; CHECK-GI-FP16: // %bb.0:1320; CHECK-GI-FP16-NEXT: adrp x8, .LCPI57_01321; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI57_0]1322; CHECK-GI-FP16-NEXT: fmul h0, h0, h11323; CHECK-GI-FP16-NEXT: fcvtzs x0, h01324; CHECK-GI-FP16-NEXT: ret1325 %fix = fmul half %dbl, 128.01326 %cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)1327 ret i64 %cvt1328}1329 1330define i64 @fcvtzs_sat_f16_i64_15(half %dbl) {1331; CHECK-NO16-LABEL: fcvtzs_sat_f16_i64_15:1332; CHECK-NO16: // %bb.0:1333; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #241334; CHECK-NO16-NEXT: fcvt s0, h01335; CHECK-NO16-NEXT: fmul s0, s0, s11336; CHECK-NO16-NEXT: fcvt h0, s01337; CHECK-NO16-NEXT: fcvt s0, h01338; CHECK-NO16-NEXT: fcvtzs x0, s01339; CHECK-NO16-NEXT: ret1340;1341; CHECK-SD-FP16-LABEL: fcvtzs_sat_f16_i64_15:1342; CHECK-SD-FP16: // %bb.0:1343; CHECK-SD-FP16-NEXT: fcvtzs x0, h0, #151344; CHECK-SD-FP16-NEXT: ret1345;1346; CHECK-GI-FP16-LABEL: fcvtzs_sat_f16_i64_15:1347; CHECK-GI-FP16: // %bb.0:1348; CHECK-GI-FP16-NEXT: adrp x8, .LCPI58_01349; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI58_0]1350; CHECK-GI-FP16-NEXT: fmul h0, h0, h11351; CHECK-GI-FP16-NEXT: fcvtzs x0, h01352; CHECK-GI-FP16-NEXT: ret1353 %fix = fmul half %dbl, 32768.01354 %cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)1355 ret i64 %cvt1356}1357 1358; fptoui1359 1360declare i32 @llvm.fptoui.sat.i32.f32(float)1361declare i64 @llvm.fptoui.sat.i64.f32(float)1362declare i32 @llvm.fptoui.sat.i32.f64(double)1363declare i64 @llvm.fptoui.sat.i64.f64(double)1364declare i32 @llvm.fptoui.sat.i32.f16(half)1365declare i64 @llvm.fptoui.sat.i64.f16(half)1366 1367define i32 @fcvtzu_sat_f32_i32_7(float %flt) {1368; CHECK-SD-LABEL: fcvtzu_sat_f32_i32_7:1369; CHECK-SD: // %bb.0:1370; CHECK-SD-NEXT: fcvtzu w0, s0, #71371; CHECK-SD-NEXT: ret1372;1373; CHECK-GI-LABEL: fcvtzu_sat_f32_i32_7:1374; CHECK-GI: // %bb.0:1375; CHECK-GI-NEXT: movi v1.2s, #67, lsl #241376; CHECK-GI-NEXT: fmul s0, s0, s11377; CHECK-GI-NEXT: fcvtzu w0, s01378; CHECK-GI-NEXT: ret1379 %fix = fmul float %flt, 128.01380 %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)1381 ret i32 %cvt1382}1383 1384define i32 @fcvtzu_sat_f32_i32_32(float %flt) {1385; CHECK-SD-LABEL: fcvtzu_sat_f32_i32_32:1386; CHECK-SD: // %bb.0:1387; CHECK-SD-NEXT: fcvtzu w0, s0, #321388; CHECK-SD-NEXT: ret1389;1390; CHECK-GI-LABEL: fcvtzu_sat_f32_i32_32:1391; CHECK-GI: // %bb.0:1392; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f8000001393; CHECK-GI-NEXT: fmov s1, w81394; CHECK-GI-NEXT: fmul s0, s0, s11395; CHECK-GI-NEXT: fcvtzu w0, s01396; CHECK-GI-NEXT: ret1397 %fix = fmul float %flt, 4294967296.01398 %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)1399 ret i32 %cvt1400}1401 1402define i64 @fcvtzu_sat_f32_i64_64(float %flt) {1403; CHECK-SD-LABEL: fcvtzu_sat_f32_i64_64:1404; CHECK-SD: // %bb.0:1405; CHECK-SD-NEXT: fcvtzu x0, s0, #641406; CHECK-SD-NEXT: ret1407;1408; CHECK-GI-LABEL: fcvtzu_sat_f32_i64_64:1409; CHECK-GI: // %bb.0:1410; CHECK-GI-NEXT: mov w8, #1602224128 // =0x5f8000001411; CHECK-GI-NEXT: fmov s1, w81412; CHECK-GI-NEXT: fmul s0, s0, s11413; CHECK-GI-NEXT: fcvtzu x0, s01414; CHECK-GI-NEXT: ret1415 %fix = fmul float %flt, 18446744073709551616.01416 %cvt = call i64 @llvm.fptoui.sat.i64.f32(float %fix)1417 ret i64 %cvt1418}1419 1420define i32 @fcvtzu_sat_f64_i32_7(double %dbl) {1421; CHECK-SD-LABEL: fcvtzu_sat_f64_i32_7:1422; CHECK-SD: // %bb.0:1423; CHECK-SD-NEXT: fcvtzu w0, d0, #71424; CHECK-SD-NEXT: ret1425;1426; CHECK-GI-LABEL: fcvtzu_sat_f64_i32_7:1427; CHECK-GI: // %bb.0:1428; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x40600000000000001429; CHECK-GI-NEXT: fmov d1, x81430; CHECK-GI-NEXT: fmul d0, d0, d11431; CHECK-GI-NEXT: fcvtzu w0, d01432; CHECK-GI-NEXT: ret1433 %fix = fmul double %dbl, 128.01434 %cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)1435 ret i32 %cvt1436}1437 1438define i32 @fcvtzu_sat_f64_i32_32(double %dbl) {1439; CHECK-SD-LABEL: fcvtzu_sat_f64_i32_32:1440; CHECK-SD: // %bb.0:1441; CHECK-SD-NEXT: fcvtzu w0, d0, #321442; CHECK-SD-NEXT: ret1443;1444; CHECK-GI-LABEL: fcvtzu_sat_f64_i32_32:1445; CHECK-GI: // %bb.0:1446; CHECK-GI-NEXT: mov x8, #4751297606875873280 // =0x41f00000000000001447; CHECK-GI-NEXT: fmov d1, x81448; CHECK-GI-NEXT: fmul d0, d0, d11449; CHECK-GI-NEXT: fcvtzu w0, d01450; CHECK-GI-NEXT: ret1451 %fix = fmul double %dbl, 4294967296.01452 %cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)1453 ret i32 %cvt1454}1455 1456define i64 @fcvtzu_sat_f64_i64_7(double %dbl) {1457; CHECK-SD-LABEL: fcvtzu_sat_f64_i64_7:1458; CHECK-SD: // %bb.0:1459; CHECK-SD-NEXT: fcvtzu x0, d0, #71460; CHECK-SD-NEXT: ret1461;1462; CHECK-GI-LABEL: fcvtzu_sat_f64_i64_7:1463; CHECK-GI: // %bb.0:1464; CHECK-GI-NEXT: mov x8, #4638707616191610880 // =0x40600000000000001465; CHECK-GI-NEXT: fmov d1, x81466; CHECK-GI-NEXT: fmul d0, d0, d11467; CHECK-GI-NEXT: fcvtzu x0, d01468; CHECK-GI-NEXT: ret1469 %fix = fmul double %dbl, 128.01470 %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)1471 ret i64 %cvt1472}1473 1474define i64 @fcvtzu_sat_f64_i64_64(double %dbl) {1475; CHECK-SD-LABEL: fcvtzu_sat_f64_i64_64:1476; CHECK-SD: // %bb.0:1477; CHECK-SD-NEXT: fcvtzu x0, d0, #641478; CHECK-SD-NEXT: ret1479;1480; CHECK-GI-LABEL: fcvtzu_sat_f64_i64_64:1481; CHECK-GI: // %bb.0:1482; CHECK-GI-NEXT: mov x8, #4895412794951729152 // =0x43f00000000000001483; CHECK-GI-NEXT: fmov d1, x81484; CHECK-GI-NEXT: fmul d0, d0, d11485; CHECK-GI-NEXT: fcvtzu x0, d01486; CHECK-GI-NEXT: ret1487 %fix = fmul double %dbl, 18446744073709551616.01488 %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)1489 ret i64 %cvt1490}1491 1492define i32 @fcvtzu_sat_f16_i32_7(half %dbl) {1493; CHECK-NO16-LABEL: fcvtzu_sat_f16_i32_7:1494; CHECK-NO16: // %bb.0:1495; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #241496; CHECK-NO16-NEXT: fcvt s0, h01497; CHECK-NO16-NEXT: fmul s0, s0, s11498; CHECK-NO16-NEXT: fcvt h0, s01499; CHECK-NO16-NEXT: fcvt s0, h01500; CHECK-NO16-NEXT: fcvtzu w0, s01501; CHECK-NO16-NEXT: ret1502;1503; CHECK-SD-FP16-LABEL: fcvtzu_sat_f16_i32_7:1504; CHECK-SD-FP16: // %bb.0:1505; CHECK-SD-FP16-NEXT: fcvtzu w0, h0, #71506; CHECK-SD-FP16-NEXT: ret1507;1508; CHECK-GI-FP16-LABEL: fcvtzu_sat_f16_i32_7:1509; CHECK-GI-FP16: // %bb.0:1510; CHECK-GI-FP16-NEXT: adrp x8, .LCPI66_01511; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI66_0]1512; CHECK-GI-FP16-NEXT: fmul h0, h0, h11513; CHECK-GI-FP16-NEXT: fcvtzu w0, h01514; CHECK-GI-FP16-NEXT: ret1515 %fix = fmul half %dbl, 128.01516 %cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)1517 ret i32 %cvt1518}1519 1520define i32 @fcvtzu_sat_f16_i32_15(half %dbl) {1521; CHECK-NO16-LABEL: fcvtzu_sat_f16_i32_15:1522; CHECK-NO16: // %bb.0:1523; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #241524; CHECK-NO16-NEXT: fcvt s0, h01525; CHECK-NO16-NEXT: fmul s0, s0, s11526; CHECK-NO16-NEXT: fcvt h0, s01527; CHECK-NO16-NEXT: fcvt s0, h01528; CHECK-NO16-NEXT: fcvtzu w0, s01529; CHECK-NO16-NEXT: ret1530;1531; CHECK-SD-FP16-LABEL: fcvtzu_sat_f16_i32_15:1532; CHECK-SD-FP16: // %bb.0:1533; CHECK-SD-FP16-NEXT: fcvtzu w0, h0, #151534; CHECK-SD-FP16-NEXT: ret1535;1536; CHECK-GI-FP16-LABEL: fcvtzu_sat_f16_i32_15:1537; CHECK-GI-FP16: // %bb.0:1538; CHECK-GI-FP16-NEXT: adrp x8, .LCPI67_01539; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI67_0]1540; CHECK-GI-FP16-NEXT: fmul h0, h0, h11541; CHECK-GI-FP16-NEXT: fcvtzu w0, h01542; CHECK-GI-FP16-NEXT: ret1543 %fix = fmul half %dbl, 32768.01544 %cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)1545 ret i32 %cvt1546}1547 1548define i64 @fcvtzu_sat_f16_i64_7(half %dbl) {1549; CHECK-NO16-LABEL: fcvtzu_sat_f16_i64_7:1550; CHECK-NO16: // %bb.0:1551; CHECK-NO16-NEXT: movi v1.2s, #67, lsl #241552; CHECK-NO16-NEXT: fcvt s0, h01553; CHECK-NO16-NEXT: fmul s0, s0, s11554; CHECK-NO16-NEXT: fcvt h0, s01555; CHECK-NO16-NEXT: fcvt s0, h01556; CHECK-NO16-NEXT: fcvtzu x0, s01557; CHECK-NO16-NEXT: ret1558;1559; CHECK-SD-FP16-LABEL: fcvtzu_sat_f16_i64_7:1560; CHECK-SD-FP16: // %bb.0:1561; CHECK-SD-FP16-NEXT: fcvtzu x0, h0, #71562; CHECK-SD-FP16-NEXT: ret1563;1564; CHECK-GI-FP16-LABEL: fcvtzu_sat_f16_i64_7:1565; CHECK-GI-FP16: // %bb.0:1566; CHECK-GI-FP16-NEXT: adrp x8, .LCPI68_01567; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI68_0]1568; CHECK-GI-FP16-NEXT: fmul h0, h0, h11569; CHECK-GI-FP16-NEXT: fcvtzu x0, h01570; CHECK-GI-FP16-NEXT: ret1571 %fix = fmul half %dbl, 128.01572 %cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)1573 ret i64 %cvt1574}1575 1576define i64 @fcvtzu_sat_f16_i64_15(half %dbl) {1577; CHECK-NO16-LABEL: fcvtzu_sat_f16_i64_15:1578; CHECK-NO16: // %bb.0:1579; CHECK-NO16-NEXT: movi v1.2s, #71, lsl #241580; CHECK-NO16-NEXT: fcvt s0, h01581; CHECK-NO16-NEXT: fmul s0, s0, s11582; CHECK-NO16-NEXT: fcvt h0, s01583; CHECK-NO16-NEXT: fcvt s0, h01584; CHECK-NO16-NEXT: fcvtzu x0, s01585; CHECK-NO16-NEXT: ret1586;1587; CHECK-SD-FP16-LABEL: fcvtzu_sat_f16_i64_15:1588; CHECK-SD-FP16: // %bb.0:1589; CHECK-SD-FP16-NEXT: fcvtzu x0, h0, #151590; CHECK-SD-FP16-NEXT: ret1591;1592; CHECK-GI-FP16-LABEL: fcvtzu_sat_f16_i64_15:1593; CHECK-GI-FP16: // %bb.0:1594; CHECK-GI-FP16-NEXT: adrp x8, .LCPI69_01595; CHECK-GI-FP16-NEXT: ldr h1, [x8, :lo12:.LCPI69_0]1596; CHECK-GI-FP16-NEXT: fmul h0, h0, h11597; CHECK-GI-FP16-NEXT: fcvtzu x0, h01598; CHECK-GI-FP16-NEXT: ret1599 %fix = fmul half %dbl, 32768.01600 %cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)1601 ret i64 %cvt1602}1603;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1604; CHECK: {{.*}}1605; CHECK-FP16: {{.*}}1606