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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s | FileCheck %s3 4target triple = "aarch64"5 6; First some corner cases7define <4 x float> @f_v4_s0(<4 x i32> %u) {8; CHECK-LABEL: f_v4_s0:9; CHECK: // %bb.0:10; CHECK-NEXT: scvtf v0.4s, v0.4s11; CHECK-NEXT: ret12 %s = ashr exact <4 x i32> %u, <i32 0, i32 0, i32 0, i32 0>13 %v = sitofp <4 x i32> %s to <4 x float>14 ret <4 x float> %v15}16 17define <4 x float> @f_v4_s1(<4 x i32> %u) {18; CHECK-LABEL: f_v4_s1:19; CHECK: // %bb.0:20; CHECK-NEXT: scvtf v0.4s, v0.4s, #121; CHECK-NEXT: ret22 %s = ashr exact <4 x i32> %u, <i32 1, i32 1, i32 1, i32 1>23 %v = sitofp <4 x i32> %s to <4 x float>24 ret <4 x float> %v25}26 27define <4 x float> @f_v4_s24_inexact(<4 x i32> %u) {28; CHECK-LABEL: f_v4_s24_inexact:29; CHECK: // %bb.0:30; CHECK-NEXT: sshr v0.4s, v0.4s, #2431; CHECK-NEXT: scvtf v0.4s, v0.4s32; CHECK-NEXT: ret33 %s = ashr <4 x i32> %u, <i32 24, i32 24, i32 24, i32 24>34 %v = sitofp <4 x i32> %s to <4 x float>35 ret <4 x float> %v36}37 38define <4 x float> @f_v4_s31(<4 x i32> %u) {39; CHECK-LABEL: f_v4_s31:40; CHECK: // %bb.0:41; CHECK-NEXT: cmlt v0.4s, v0.4s, #042; CHECK-NEXT: scvtf v0.4s, v0.4s43; CHECK-NEXT: ret44 %s = ashr <4 x i32> %u, <i32 31, i32 31, i32 31, i32 31>45 %v = sitofp <4 x i32> %s to <4 x float>46 ret <4 x float> %v47}48 49; Common cases for conversion from signed integer to floating point types50define <2 x float> @f_v2_s24(<2 x i32> %u) {51; CHECK-LABEL: f_v2_s24:52; CHECK: // %bb.0:53; CHECK-NEXT: scvtf v0.2s, v0.2s, #2454; CHECK-NEXT: ret55 %s = ashr exact <2 x i32> %u, <i32 24, i32 24>56 %v = sitofp <2 x i32> %s to <2 x float>57 ret <2 x float> %v58}59 60define <4 x float> @f_v4_s24(<4 x i32> %u) {61; CHECK-LABEL: f_v4_s24:62; CHECK: // %bb.0:63; CHECK-NEXT: scvtf v0.4s, v0.4s, #2464; CHECK-NEXT: ret65 %s = ashr exact <4 x i32> %u, <i32 24, i32 24, i32 24, i32 24>66 %v = sitofp <4 x i32> %s to <4 x float>67 ret <4 x float> %v68}69 70; Check legalisation to <2 x f64> does not get in the way71define <8 x double> @d_v8_s64(<8 x i64> %u) {72; CHECK-LABEL: d_v8_s64:73; CHECK: // %bb.0:74; CHECK-NEXT: scvtf v0.2d, v0.2d, #5675; CHECK-NEXT: scvtf v1.2d, v1.2d, #5676; CHECK-NEXT: scvtf v2.2d, v2.2d, #5677; CHECK-NEXT: scvtf v3.2d, v3.2d, #5678; CHECK-NEXT: ret79 %s = ashr exact <8 x i64> %u, <i64 56, i64 56, i64 56, i64 56, i64 56, i64 56, i64 56, i64 56>80 %v = sitofp <8 x i64> %s to <8 x double>81 ret <8 x double> %v82}83 84define <4 x half> @h_v4_s8(<4 x i16> %u) #0 {85; CHECK-LABEL: h_v4_s8:86; CHECK: // %bb.0:87; CHECK-NEXT: scvtf v0.4h, v0.4h, #888; CHECK-NEXT: ret89 %s = ashr exact <4 x i16> %u, <i16 8, i16 8, i16 8, i16 8>90 %v = sitofp <4 x i16> %s to <4 x half>91 ret <4 x half> %v92}93 94define <8 x half> @h_v8_s8(<8 x i16> %u) #0 {95; CHECK-LABEL: h_v8_s8:96; CHECK: // %bb.0:97; CHECK-NEXT: scvtf v0.8h, v0.8h, #898; CHECK-NEXT: ret99 %s = ashr exact <8 x i16> %u, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>100 %v = sitofp <8 x i16> %s to <8 x half>101 ret <8 x half> %v102}103 104; int-to-fp conversion of element in lane 0 should apply105; cvtf on vector subregister to avoid fpr->gpr trip106define float @l0_extract_f_v2s(<2 x i32> %u) {107; CHECK-LABEL: l0_extract_f_v2s:108; CHECK: // %bb.0:109; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0110; CHECK-NEXT: scvtf s0, s0111; CHECK-NEXT: ret112 %i = extractelement <2 x i32> %u, i64 0113 %f = sitofp i32 %i to float114 ret float %f115}116 117; cvtf to use ssub for bottom 32-bits from v2i32118define float @l0_extract_f_v2u(<2 x i32> %u) {119; CHECK-LABEL: l0_extract_f_v2u:120; CHECK: // %bb.0:121; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0122; CHECK-NEXT: ucvtf s0, s0123; CHECK-NEXT: ret124 %i = extractelement <2 x i32> %u, i64 0125 %f = uitofp i32 %i to float126 ret float %f127}128 129; Pattern should only apply when it is known to be lane 0130define float @ln_extract_f_v2s(<2 x i32> %u, i64 %n) {131; CHECK-LABEL: ln_extract_f_v2s:132; CHECK: // %bb.0:133; CHECK-NEXT: sub sp, sp, #16134; CHECK-NEXT: .cfi_def_cfa_offset 16135; CHECK-NEXT: add x8, sp, #8136; CHECK-NEXT: str d0, [sp, #8]137; CHECK-NEXT: bfi x8, x0, #2, #1138; CHECK-NEXT: ldr s0, [x8]139; CHECK-NEXT: scvtf s0, s0140; CHECK-NEXT: add sp, sp, #16141; CHECK-NEXT: ret142 %i = extractelement <2 x i32> %u, i64 %n143 %f = sitofp i32 %i to float144 ret float %f145}146 147; cvtf to use ssub for bottom 32-bits from v4i32148define float @l0_extract_f_v4s(<4 x i32> %u) {149; CHECK-LABEL: l0_extract_f_v4s:150; CHECK: // %bb.0:151; CHECK-NEXT: scvtf s0, s0152; CHECK-NEXT: ret153 %i = extractelement <4 x i32> %u, i64 0154 %f = sitofp i32 %i to float155 ret float %f156}157 158define float @l0_extract_f_v4u(<4 x i32> %u) {159; CHECK-LABEL: l0_extract_f_v4u:160; CHECK: // %bb.0:161; CHECK-NEXT: ucvtf s0, s0162; CHECK-NEXT: ret163 %i = extractelement <4 x i32> %u, i64 0164 %f = uitofp i32 %i to float165 ret float %f166}167 168define float @ln_extract_f_v4s(<4 x i32> %u, i64 %n) {169; CHECK-LABEL: ln_extract_f_v4s:170; CHECK: // %bb.0:171; CHECK-NEXT: sub sp, sp, #16172; CHECK-NEXT: .cfi_def_cfa_offset 16173; CHECK-NEXT: mov x8, sp174; CHECK-NEXT: str q0, [sp]175; CHECK-NEXT: bfi x8, x0, #2, #2176; CHECK-NEXT: ldr s0, [x8]177; CHECK-NEXT: scvtf s0, s0178; CHECK-NEXT: add sp, sp, #16179; CHECK-NEXT: ret180 %i = extractelement <4 x i32> %u, i64 %n181 %f = sitofp i32 %i to float182 ret float %f183}184 185; cvtf to use dsub for bottom 64-bits from v2i64186define double @l0_extract_d_v2s(<2 x i64> %u) {187; CHECK-LABEL: l0_extract_d_v2s:188; CHECK: // %bb.0:189; CHECK-NEXT: scvtf d0, d0190; CHECK-NEXT: ret191 %i = extractelement <2 x i64> %u, i64 0192 %f = sitofp i64 %i to double193 ret double %f194}195 196define double @l0_extract_d_v2u(<2 x i64> %u) {197; CHECK-LABEL: l0_extract_d_v2u:198; CHECK: // %bb.0:199; CHECK-NEXT: ucvtf d0, d0200; CHECK-NEXT: ret201 %i = extractelement <2 x i64> %u, i64 0202 %f = uitofp i64 %i to double203 ret double %f204}205 206define double @ln_extract_d_v2s(<2 x i64> %u, i64 %n) {207; CHECK-LABEL: ln_extract_d_v2s:208; CHECK: // %bb.0:209; CHECK-NEXT: sub sp, sp, #16210; CHECK-NEXT: .cfi_def_cfa_offset 16211; CHECK-NEXT: mov x8, sp212; CHECK-NEXT: str q0, [sp]213; CHECK-NEXT: bfi x8, x0, #3, #1214; CHECK-NEXT: ldr d0, [x8]215; CHECK-NEXT: scvtf d0, d0216; CHECK-NEXT: add sp, sp, #16217; CHECK-NEXT: ret218 %i = extractelement <2 x i64> %u, i64 %n219 %f = sitofp i64 %i to double220 ret double %f221}222 223; (fullfp16) cvtf to use hsub for bottom 16-bits from v8i16224define half @l0_extract_h_v8s(<8 x i16> %u) #0 {225; CHECK-LABEL: l0_extract_h_v8s:226; CHECK: // %bb.0:227; CHECK-NEXT: scvtf h0, h0228; CHECK-NEXT: ret229 %i = extractelement <8 x i16> %u, i32 0230 %f = sitofp i16 %i to half231 ret half %f232}233 234define half @l0_extract_h_v8u(<8 x i16> %u) #0 {235; CHECK-LABEL: l0_extract_h_v8u:236; CHECK: // %bb.0:237; CHECK-NEXT: ucvtf h0, h0238; CHECK-NEXT: ret239 %i = extractelement <8 x i16> %u, i32 0240 %f = uitofp i16 %i to half241 ret half %f242}243 244define half @ln_extract_h_v8u(<8 x i16> %u, i32 %n) #0 {245; CHECK-LABEL: ln_extract_h_v8u:246; CHECK: // %bb.0:247; CHECK-NEXT: sub sp, sp, #16248; CHECK-NEXT: .cfi_def_cfa_offset 16249; CHECK-NEXT: mov x8, sp250; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0251; CHECK-NEXT: str q0, [sp]252; CHECK-NEXT: bfi x8, x0, #1, #3253; CHECK-NEXT: ldrh w8, [x8]254; CHECK-NEXT: ucvtf h0, w8255; CHECK-NEXT: add sp, sp, #16256; CHECK-NEXT: ret257 %i = extractelement <8 x i16> %u, i32 %n258 %f = uitofp i16 %i to half259 ret half %f260}261 262attributes #0 = { "target-features"="+fullfp16"}263