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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 -verify-machineinstrs -o - %s | FileCheck %s3 4; LLVM should be able to cope with multiple uses of the same flag-setting5; instruction at different points of a routine. Either by rematerializing the6; compare or by saving and restoring the flag register.7 8declare void @bar()9 10@var = global i32 011 12define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) {13; CHECK-LABEL: test_multiflag:14; CHECK: // %bb.0:15; CHECK-NEXT: str x30, [sp, #-32]! // 8-byte Folded Spill16; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill17; CHECK-NEXT: .cfi_def_cfa_offset 3218; CHECK-NEXT: .cfi_offset w19, -819; CHECK-NEXT: .cfi_offset w20, -1620; CHECK-NEXT: .cfi_offset w30, -3221; CHECK-NEXT: adrp x8, :got:var22; CHECK-NEXT: cmp w0, w123; CHECK-NEXT: mov w19, w124; CHECK-NEXT: ldr x8, [x8, :got_lo12:var]25; CHECK-NEXT: cset w9, ne26; CHECK-NEXT: mov w20, w027; CHECK-NEXT: str w9, [x8]28; CHECK-NEXT: bl bar29; CHECK-NEXT: cmp w20, w1930; CHECK-NEXT: b.eq .LBB0_231; CHECK-NEXT: // %bb.1: // %iftrue32; CHECK-NEXT: mov w0, #42 // =0x2a33; CHECK-NEXT: b .LBB0_334; CHECK-NEXT: .LBB0_2: // %iffalse35; CHECK-NEXT: mov w0, wzr36; CHECK-NEXT: .LBB0_3: // %iftrue37; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload38; CHECK-NEXT: ldr x30, [sp], #32 // 8-byte Folded Reload39; CHECK-NEXT: ret40 41 %test = icmp ne i32 %n, %m42 43 %val = zext i1 %test to i3244 45 46 store i32 %val, ptr @var47 48 call void @bar()49 50 ; Currently, the comparison is emitted again. An MSR/MRS pair would also be51 ; acceptable, but assuming the call preserves NZCV is not.52 br i1 %test, label %iftrue, label %iffalse53 54iftrue:55 ret i32 4256iffalse:57 ret i32 058}59