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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=aarch64 -mattr=+fp16fml -verify-machineinstrs %s -o - 2>&1 | FileCheck %s3 4; This tests that the fmlal/fmlal2 instructions only accept lo registers for5; the index operand, using inline asm to force the available registers.6 7define <4 x float> @test(ptr %lhs_panel, ptr %rhs_panel, <4 x float> %a) {8; CHECK-LABEL: test:9; CHECK: // %bb.0: // %entry10; CHECK-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill11; CHECK-NEXT: .cfi_def_cfa_offset 1612; CHECK-NEXT: .cfi_offset b8, -1613; CHECK-NEXT: fmov x8, d014; CHECK-NEXT: ldr q16, [x1]15; CHECK-NEXT: ldr q8, [x0]16; CHECK-NEXT: lsr x9, x8, #3217; CHECK-NEXT: //APP18; CHECK-NEXT: nop19; CHECK-NEXT: //NO_APP20; CHECK-NEXT: mov w8, w821; CHECK-NEXT: orr x8, x8, x9, lsl #3222; CHECK-NEXT: fmov d0, x823; CHECK-NEXT: fmlal v0.4s, v16.4h, v8.h[0]24; CHECK-NEXT: mov v1.16b, v0.16b25; CHECK-NEXT: fmlal2 v1.4s, v16.4h, v8.h[0]26; CHECK-NEXT: fadd v0.4s, v0.4s, v1.4s27; CHECK-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload28; CHECK-NEXT: ret29entry:30 %0 = load <8 x half>, ptr %lhs_panel, align 231 %1 = load <8 x half>, ptr %rhs_panel, align 232 %vecinit91 = shufflevector <8 x half> %0, <8 x half> undef, <8 x i32> zeroinitializer33 %b = call <4 x float> asm sideeffect "nop", "=r,r,~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7}"(<4 x float> %a) nounwind34 %vfmlal_low3.i = tail call <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float> %b, <8 x half> %1, <8 x half> %vecinit91)35 %vfmlal_high3.i = tail call <4 x float> @llvm.aarch64.neon.fmlal2.v4f32.v8f16(<4 x float> %vfmlal_low3.i, <8 x half> %1, <8 x half> %vecinit91)36 %z = fadd <4 x float> %vfmlal_low3.i, %vfmlal_high3.i37 ret <4 x float> %z38}39 40define void @loop(ptr %out_tile, ptr %lhs_panel, ptr %rhs_panel, i32 noundef %K, i32 noundef %flags) {41; CHECK-LABEL: loop:42; CHECK: // %bb.0: // %entry43; CHECK-NEXT: movi v0.2d, #000000000000000044; CHECK-NEXT: movi v1.2d, #000000000000000045; CHECK-NEXT: mov w8, w346; CHECK-NEXT: .LBB1_1: // %for.body47; CHECK-NEXT: // =>This Inner Loop Header: Depth=148; CHECK-NEXT: ldr q2, [x1], #249; CHECK-NEXT: subs x8, x8, #150; CHECK-NEXT: ldr q3, [x2], #251; CHECK-NEXT: fmlal v0.4s, v3.4h, v2.h[0]52; CHECK-NEXT: fmlal2 v1.4s, v3.4h, v2.h[0]53; CHECK-NEXT: b.ne .LBB1_154; CHECK-NEXT: // %bb.2: // %for.cond.cleanup55; CHECK-NEXT: stp q0, q1, [x0]56; CHECK-NEXT: ret57entry:58 %wide.trip.count = zext i32 %K to i6459 br label %for.body60 61for.cond.cleanup: ; preds = %for.body62 store <4 x float> %vfmlal_low3.i, ptr %out_tile, align 463 %add.ptr1399 = getelementptr inbounds float, ptr %out_tile, i64 464 store <4 x float> %vfmlal_high3.i, ptr %add.ptr1399, align 465 ret void66 67for.body: ; preds = %entry, %for.body68 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]69 %acc0.01714 = phi <4 x float> [ zeroinitializer, %entry ], [ %vfmlal_low3.i, %for.body ]70 %acc1.01713 = phi <4 x float> [ zeroinitializer, %entry ], [ %vfmlal_high3.i, %for.body ]71 %add.ptr = getelementptr inbounds half, ptr %lhs_panel, i64 %indvars.iv72 %0 = load <8 x half>, ptr %add.ptr, align 273 %add.ptr19 = getelementptr inbounds half, ptr %rhs_panel, i64 %indvars.iv74 %1 = load <8 x half>, ptr %add.ptr19, align 275 %vecinit93 = shufflevector <8 x half> %0, <8 x half> undef, <8 x i32> zeroinitializer76 %vfmlal_low3.i = tail call <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float> %acc0.01714, <8 x half> %1, <8 x half> %vecinit93)77 %vfmlal_high3.i = tail call <4 x float> @llvm.aarch64.neon.fmlal2.v4f32.v8f16(<4 x float> %acc1.01713, <8 x half> %1, <8 x half> %vecinit93)78 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 179 %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count80 br i1 %exitcond.not, label %for.cond.cleanup, label %for.body81}82 83define void @sink(ptr %out_tile, ptr %lhs_panel, ptr %rhs_panel, i32 noundef %K, i32 noundef %flags, <8 x half> noundef %lhs) {84; CHECK-LABEL: sink:85; CHECK: // %bb.0: // %entry86; CHECK-NEXT: movi v1.2d, #000000000000000087; CHECK-NEXT: movi v2.2d, #000000000000000088; CHECK-NEXT: mov w8, w389; CHECK-NEXT: .LBB2_1: // %for.body90; CHECK-NEXT: // =>This Inner Loop Header: Depth=191; CHECK-NEXT: ldr q3, [x2], #292; CHECK-NEXT: subs x8, x8, #193; CHECK-NEXT: fmlal v1.4s, v3.4h, v0.h[0]94; CHECK-NEXT: fmlal2 v2.4s, v3.4h, v0.h[0]95; CHECK-NEXT: b.ne .LBB2_196; CHECK-NEXT: // %bb.2: // %for.cond.cleanup97; CHECK-NEXT: stp q1, q2, [x0]98; CHECK-NEXT: ret99entry:100 %vecinit89 = shufflevector <8 x half> %lhs, <8 x half> undef, <8 x i32> zeroinitializer101 %wide.trip.count = zext i32 %K to i64102 br label %for.body103 104for.cond.cleanup: ; preds = %for.body105 store <4 x float> %vfmlal_low3.i, ptr %out_tile, align 4106 %add.ptr1395 = getelementptr inbounds float, ptr %out_tile, i64 4107 store <4 x float> %vfmlal_high3.i, ptr %add.ptr1395, align 4108 ret void109 110for.body: ; preds = %entry, %for.body111 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]112 %acc0.01702 = phi <4 x float> [ zeroinitializer, %entry ], [ %vfmlal_low3.i, %for.body ]113 %acc1.01701 = phi <4 x float> [ zeroinitializer, %entry ], [ %vfmlal_high3.i, %for.body ]114 %add.ptr = getelementptr inbounds half, ptr %rhs_panel, i64 %indvars.iv115 %0 = load <8 x half>, ptr %add.ptr, align 2116 %vfmlal_low3.i = tail call <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float> %acc0.01702, <8 x half> %0, <8 x half> %vecinit89)117 %vfmlal_high3.i = tail call <4 x float> @llvm.aarch64.neon.fmlal2.v4f32.v8f16(<4 x float> %acc1.01701, <8 x half> %0, <8 x half> %vecinit89)118 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1119 %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count120 br i1 %exitcond.not, label %for.cond.cleanup, label %for.body121}122 123 124declare <4 x float> @llvm.aarch64.neon.fmlal.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #2125declare <4 x float> @llvm.aarch64.neon.fmlal2.v4f32.v8f16(<4 x float>, <8 x half>, <8 x half>) #2126 127