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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc --disable-replace-with-vec-lib --vector-library=ArmPL < %s -o - | FileCheck --check-prefix=ARMPL %s3; RUN: llc --disable-replace-with-vec-lib --vector-library=sleefgnuabi < %s -o - | FileCheck --check-prefix=SLEEF %s4 5target triple = "aarch64-unknown-linux-gnu"6 7define <2 x double> @frem_v2f64(<2 x double> %unused, <2 x double> %a, <2 x double> %b) #0 {8; ARMPL-LABEL: frem_v2f64:9; ARMPL: // %bb.0:10; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill11; ARMPL-NEXT: .cfi_def_cfa_offset 1612; ARMPL-NEXT: .cfi_offset w30, -1613; ARMPL-NEXT: mov v0.16b, v1.16b14; ARMPL-NEXT: mov v1.16b, v2.16b15; ARMPL-NEXT: bl armpl_vfmodq_f6416; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload17; ARMPL-NEXT: ret18;19; SLEEF-LABEL: frem_v2f64:20; SLEEF: // %bb.0:21; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill22; SLEEF-NEXT: .cfi_def_cfa_offset 1623; SLEEF-NEXT: .cfi_offset w30, -1624; SLEEF-NEXT: mov v0.16b, v1.16b25; SLEEF-NEXT: mov v1.16b, v2.16b26; SLEEF-NEXT: bl _ZGVnN2vv_fmod27; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload28; SLEEF-NEXT: ret29 %res = frem <2 x double> %a, %b30 ret <2 x double> %res31}32 33define <4 x float> @frem_strict_v4f32(<4 x float> %unused, <4 x float> %a, <4 x float> %b) #1 {34; ARMPL-LABEL: frem_strict_v4f32:35; ARMPL: // %bb.0:36; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill37; ARMPL-NEXT: .cfi_def_cfa_offset 1638; ARMPL-NEXT: .cfi_offset w30, -1639; ARMPL-NEXT: mov v0.16b, v1.16b40; ARMPL-NEXT: mov v1.16b, v2.16b41; ARMPL-NEXT: bl armpl_vfmodq_f3242; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload43; ARMPL-NEXT: ret44;45; SLEEF-LABEL: frem_strict_v4f32:46; SLEEF: // %bb.0:47; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill48; SLEEF-NEXT: .cfi_def_cfa_offset 1649; SLEEF-NEXT: .cfi_offset w30, -1650; SLEEF-NEXT: mov v0.16b, v1.16b51; SLEEF-NEXT: mov v1.16b, v2.16b52; SLEEF-NEXT: bl _ZGVnN4vv_fmodf53; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload54; SLEEF-NEXT: ret55 %res = frem <4 x float> %a, %b56 ret <4 x float> %res57}58 59define <vscale x 4 x float> @frem_nxv4f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {60; ARMPL-LABEL: frem_nxv4f32:61; ARMPL: // %bb.0:62; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill63; ARMPL-NEXT: .cfi_def_cfa_offset 1664; ARMPL-NEXT: .cfi_offset w30, -1665; ARMPL-NEXT: mov z0.d, z1.d66; ARMPL-NEXT: mov z1.d, z2.d67; ARMPL-NEXT: ptrue p0.s68; ARMPL-NEXT: bl armpl_svfmod_f32_x69; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload70; ARMPL-NEXT: ret71;72; SLEEF-LABEL: frem_nxv4f32:73; SLEEF: // %bb.0:74; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill75; SLEEF-NEXT: .cfi_def_cfa_offset 1676; SLEEF-NEXT: .cfi_offset w30, -1677; SLEEF-NEXT: mov z0.d, z1.d78; SLEEF-NEXT: mov z1.d, z2.d79; SLEEF-NEXT: ptrue p0.s80; SLEEF-NEXT: bl _ZGVsMxvv_fmodf81; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload82; SLEEF-NEXT: ret83 %res = frem <vscale x 4 x float> %a, %b84 ret <vscale x 4 x float> %res85}86 87define <vscale x 2 x double> @frem_strict_nxv2f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %a, <vscale x 2 x double> %b) #1 {88; ARMPL-LABEL: frem_strict_nxv2f64:89; ARMPL: // %bb.0:90; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill91; ARMPL-NEXT: .cfi_def_cfa_offset 1692; ARMPL-NEXT: .cfi_offset w30, -1693; ARMPL-NEXT: mov z0.d, z1.d94; ARMPL-NEXT: mov z1.d, z2.d95; ARMPL-NEXT: ptrue p0.d96; ARMPL-NEXT: bl armpl_svfmod_f64_x97; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload98; ARMPL-NEXT: ret99;100; SLEEF-LABEL: frem_strict_nxv2f64:101; SLEEF: // %bb.0:102; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill103; SLEEF-NEXT: .cfi_def_cfa_offset 16104; SLEEF-NEXT: .cfi_offset w30, -16105; SLEEF-NEXT: mov z0.d, z1.d106; SLEEF-NEXT: mov z1.d, z2.d107; SLEEF-NEXT: ptrue p0.d108; SLEEF-NEXT: bl _ZGVsMxvv_fmod109; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload110; SLEEF-NEXT: ret111 %res = frem <vscale x 2 x double> %a, %b112 ret <vscale x 2 x double> %res113}114 115attributes #0 = { "target-features"="+sve" }116attributes #1 = { "target-features"="+sve" strictfp }117