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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=aarch64 -mattr=-fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT,CHECK-CVT-SD3; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-SD4; RUN: llc < %s -mtriple=aarch64 -mattr=-fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-CVT,CHECK-CVT-GI5; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-GI6 7define <4 x half> @add_h(<4 x half> %a, <4 x half> %b) {8; CHECK-CVT-SD-LABEL: add_h:9; CHECK-CVT-SD: // %bb.0: // %entry10; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h11; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h12; CHECK-CVT-SD-NEXT: fadd v0.4s, v0.4s, v1.4s13; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v0.4s14; CHECK-CVT-SD-NEXT: ret15;16; CHECK-FP16-LABEL: add_h:17; CHECK-FP16: // %bb.0: // %entry18; CHECK-FP16-NEXT: fadd v0.4h, v0.4h, v1.4h19; CHECK-FP16-NEXT: ret20;21; CHECK-CVT-GI-LABEL: add_h:22; CHECK-CVT-GI: // %bb.0: // %entry23; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h24; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h25; CHECK-CVT-GI-NEXT: fadd v0.4s, v0.4s, v1.4s26; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v0.4s27; CHECK-CVT-GI-NEXT: ret28entry:29 30 %0 = fadd <4 x half> %a, %b31 ret <4 x half> %032}33 34define <4 x half> @build_h4(<4 x half> %a) {35; CHECK-CVT-SD-LABEL: build_h4:36; CHECK-CVT-SD: // %bb.0: // %entry37; CHECK-CVT-SD-NEXT: mov w8, #15565 // =0x3ccd38; CHECK-CVT-SD-NEXT: dup v0.4h, w839; CHECK-CVT-SD-NEXT: ret40;41; CHECK-FP16-SD-LABEL: build_h4:42; CHECK-FP16-SD: // %bb.0: // %entry43; CHECK-FP16-SD-NEXT: mov w8, #15565 // =0x3ccd44; CHECK-FP16-SD-NEXT: dup v0.4h, w845; CHECK-FP16-SD-NEXT: ret46;47; CHECK-CVT-GI-LABEL: build_h4:48; CHECK-CVT-GI: // %bb.0: // %entry49; CHECK-CVT-GI-NEXT: adrp x8, .LCPI1_050; CHECK-CVT-GI-NEXT: ldr d0, [x8, :lo12:.LCPI1_0]51; CHECK-CVT-GI-NEXT: ret52;53; CHECK-FP16-GI-LABEL: build_h4:54; CHECK-FP16-GI: // %bb.0: // %entry55; CHECK-FP16-GI-NEXT: adrp x8, .LCPI1_056; CHECK-FP16-GI-NEXT: ldr d0, [x8, :lo12:.LCPI1_0]57; CHECK-FP16-GI-NEXT: ret58entry:59 ret <4 x half> <half 0xH3CCD, half 0xH3CCD, half 0xH3CCD, half 0xH3CCD>60}61 62define <4 x half> @sub_h(<4 x half> %a, <4 x half> %b) {63; CHECK-CVT-SD-LABEL: sub_h:64; CHECK-CVT-SD: // %bb.0: // %entry65; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h66; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h67; CHECK-CVT-SD-NEXT: fsub v0.4s, v0.4s, v1.4s68; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v0.4s69; CHECK-CVT-SD-NEXT: ret70;71; CHECK-FP16-LABEL: sub_h:72; CHECK-FP16: // %bb.0: // %entry73; CHECK-FP16-NEXT: fsub v0.4h, v0.4h, v1.4h74; CHECK-FP16-NEXT: ret75;76; CHECK-CVT-GI-LABEL: sub_h:77; CHECK-CVT-GI: // %bb.0: // %entry78; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h79; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h80; CHECK-CVT-GI-NEXT: fsub v0.4s, v0.4s, v1.4s81; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v0.4s82; CHECK-CVT-GI-NEXT: ret83entry:84 85 %0 = fsub <4 x half> %a, %b86 ret <4 x half> %087}88 89define <4 x half> @mul_h(<4 x half> %a, <4 x half> %b) {90; CHECK-CVT-SD-LABEL: mul_h:91; CHECK-CVT-SD: // %bb.0: // %entry92; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h93; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h94; CHECK-CVT-SD-NEXT: fmul v0.4s, v0.4s, v1.4s95; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v0.4s96; CHECK-CVT-SD-NEXT: ret97;98; CHECK-FP16-LABEL: mul_h:99; CHECK-FP16: // %bb.0: // %entry100; CHECK-FP16-NEXT: fmul v0.4h, v0.4h, v1.4h101; CHECK-FP16-NEXT: ret102;103; CHECK-CVT-GI-LABEL: mul_h:104; CHECK-CVT-GI: // %bb.0: // %entry105; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h106; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h107; CHECK-CVT-GI-NEXT: fmul v0.4s, v0.4s, v1.4s108; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v0.4s109; CHECK-CVT-GI-NEXT: ret110entry:111 112 %0 = fmul <4 x half> %a, %b113 ret <4 x half> %0114}115 116define <4 x half> @div_h(<4 x half> %a, <4 x half> %b) {117; CHECK-CVT-SD-LABEL: div_h:118; CHECK-CVT-SD: // %bb.0: // %entry119; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h120; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h121; CHECK-CVT-SD-NEXT: fdiv v0.4s, v0.4s, v1.4s122; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v0.4s123; CHECK-CVT-SD-NEXT: ret124;125; CHECK-FP16-LABEL: div_h:126; CHECK-FP16: // %bb.0: // %entry127; CHECK-FP16-NEXT: fdiv v0.4h, v0.4h, v1.4h128; CHECK-FP16-NEXT: ret129;130; CHECK-CVT-GI-LABEL: div_h:131; CHECK-CVT-GI: // %bb.0: // %entry132; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h133; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h134; CHECK-CVT-GI-NEXT: fdiv v0.4s, v0.4s, v1.4s135; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v0.4s136; CHECK-CVT-GI-NEXT: ret137entry:138 139 %0 = fdiv <4 x half> %a, %b140 ret <4 x half> %0141}142 143define <4 x half> @load_h(ptr %a) {144; CHECK-LABEL: load_h:145; CHECK: // %bb.0: // %entry146; CHECK-NEXT: ldr d0, [x0]147; CHECK-NEXT: ret148entry:149 %0 = load <4 x half>, ptr %a, align 4150 ret <4 x half> %0151}152 153define void @store_h(ptr %a, <4 x half> %b) {154; CHECK-LABEL: store_h:155; CHECK: // %bb.0: // %entry156; CHECK-NEXT: str d0, [x0]157; CHECK-NEXT: ret158entry:159 store <4 x half> %b, ptr %a, align 4160 ret void161}162 163define <4 x half> @s_to_h(<4 x float> %a) {164; CHECK-LABEL: s_to_h:165; CHECK: // %bb.0:166; CHECK-NEXT: fcvtn v0.4h, v0.4s167; CHECK-NEXT: ret168 %1 = fptrunc <4 x float> %a to <4 x half>169 ret <4 x half> %1170}171 172define <4 x half> @d_to_h(<4 x double> %a) {173; CHECK-LABEL: d_to_h:174; CHECK: // %bb.0:175; CHECK-NEXT: fcvtxn v0.2s, v0.2d176; CHECK-NEXT: fcvtxn2 v0.4s, v1.2d177; CHECK-NEXT: fcvtn v0.4h, v0.4s178; CHECK-NEXT: ret179 %1 = fptrunc <4 x double> %a to <4 x half>180 ret <4 x half> %1181}182 183define <4 x float> @h_to_s(<4 x half> %a) {184; CHECK-LABEL: h_to_s:185; CHECK: // %bb.0:186; CHECK-NEXT: fcvtl v0.4s, v0.4h187; CHECK-NEXT: ret188 %1 = fpext <4 x half> %a to <4 x float>189 ret <4 x float> %1190}191 192define <4 x double> @h_to_d(<4 x half> %a) {193; CHECK-CVT-SD-LABEL: h_to_d:194; CHECK-CVT-SD: // %bb.0:195; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h196; CHECK-CVT-SD-NEXT: fcvtl2 v1.2d, v0.4s197; CHECK-CVT-SD-NEXT: fcvtl v0.2d, v0.2s198; CHECK-CVT-SD-NEXT: ret199;200; CHECK-FP16-SD-LABEL: h_to_d:201; CHECK-FP16-SD: // %bb.0:202; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h203; CHECK-FP16-SD-NEXT: fcvtl2 v1.2d, v0.4s204; CHECK-FP16-SD-NEXT: fcvtl v0.2d, v0.2s205; CHECK-FP16-SD-NEXT: ret206;207; CHECK-CVT-GI-LABEL: h_to_d:208; CHECK-CVT-GI: // %bb.0:209; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v0.4h210; CHECK-CVT-GI-NEXT: fcvtl v0.2d, v1.2s211; CHECK-CVT-GI-NEXT: fcvtl2 v1.2d, v1.4s212; CHECK-CVT-GI-NEXT: ret213;214; CHECK-FP16-GI-LABEL: h_to_d:215; CHECK-FP16-GI: // %bb.0:216; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h217; CHECK-FP16-GI-NEXT: fcvtl v0.2d, v1.2s218; CHECK-FP16-GI-NEXT: fcvtl2 v1.2d, v1.4s219; CHECK-FP16-GI-NEXT: ret220 %1 = fpext <4 x half> %a to <4 x double>221 ret <4 x double> %1222}223 224define <4 x half> @bitcast_i_to_h(float, <4 x i16> %a) {225; CHECK-LABEL: bitcast_i_to_h:226; CHECK: // %bb.0:227; CHECK-NEXT: fmov d0, d1228; CHECK-NEXT: ret229 %2 = bitcast <4 x i16> %a to <4 x half>230 ret <4 x half> %2231}232 233define <4 x i16> @bitcast_h_to_i(float, <4 x half> %a) {234; CHECK-LABEL: bitcast_h_to_i:235; CHECK: // %bb.0:236; CHECK-NEXT: fmov d0, d1237; CHECK-NEXT: ret238 %2 = bitcast <4 x half> %a to <4 x i16>239 ret <4 x i16> %2240}241 242define <4 x half> @sitofp_i8(<4 x i8> %a) #0 {243; CHECK-CVT-SD-LABEL: sitofp_i8:244; CHECK-CVT-SD: // %bb.0:245; CHECK-CVT-SD-NEXT: shl v0.4h, v0.4h, #8246; CHECK-CVT-SD-NEXT: sshr v0.4h, v0.4h, #8247; CHECK-CVT-SD-NEXT: sshll v0.4s, v0.4h, #0248; CHECK-CVT-SD-NEXT: scvtf v0.4s, v0.4s249; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v0.4s250; CHECK-CVT-SD-NEXT: ret251;252; CHECK-FP16-LABEL: sitofp_i8:253; CHECK-FP16: // %bb.0:254; CHECK-FP16-NEXT: shl v0.4h, v0.4h, #8255; CHECK-FP16-NEXT: sshr v0.4h, v0.4h, #8256; CHECK-FP16-NEXT: scvtf v0.4h, v0.4h257; CHECK-FP16-NEXT: ret258;259; CHECK-CVT-GI-LABEL: sitofp_i8:260; CHECK-CVT-GI: // %bb.0:261; CHECK-CVT-GI-NEXT: ushll v0.4s, v0.4h, #0262; CHECK-CVT-GI-NEXT: shl v0.4s, v0.4s, #24263; CHECK-CVT-GI-NEXT: sshr v0.4s, v0.4s, #24264; CHECK-CVT-GI-NEXT: scvtf v0.4s, v0.4s265; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v0.4s266; CHECK-CVT-GI-NEXT: ret267 %1 = sitofp <4 x i8> %a to <4 x half>268 ret <4 x half> %1269}270 271define <4 x half> @sitofp_i16(<4 x i16> %a) #0 {272; CHECK-CVT-LABEL: sitofp_i16:273; CHECK-CVT: // %bb.0:274; CHECK-CVT-NEXT: sshll v0.4s, v0.4h, #0275; CHECK-CVT-NEXT: scvtf v0.4s, v0.4s276; CHECK-CVT-NEXT: fcvtn v0.4h, v0.4s277; CHECK-CVT-NEXT: ret278;279; CHECK-FP16-LABEL: sitofp_i16:280; CHECK-FP16: // %bb.0:281; CHECK-FP16-NEXT: scvtf v0.4h, v0.4h282; CHECK-FP16-NEXT: ret283 %1 = sitofp <4 x i16> %a to <4 x half>284 ret <4 x half> %1285}286 287 288define <4 x half> @sitofp_i32(<4 x i32> %a) #0 {289; CHECK-LABEL: sitofp_i32:290; CHECK: // %bb.0:291; CHECK-NEXT: scvtf v0.4s, v0.4s292; CHECK-NEXT: fcvtn v0.4h, v0.4s293; CHECK-NEXT: ret294 %1 = sitofp <4 x i32> %a to <4 x half>295 ret <4 x half> %1296}297 298 299define <4 x half> @sitofp_i64(<4 x i64> %a) #0 {300; CHECK-LABEL: sitofp_i64:301; CHECK: // %bb.0:302; CHECK-NEXT: scvtf v0.2d, v0.2d303; CHECK-NEXT: scvtf v1.2d, v1.2d304; CHECK-NEXT: fcvtn v0.2s, v0.2d305; CHECK-NEXT: fcvtn2 v0.4s, v1.2d306; CHECK-NEXT: fcvtn v0.4h, v0.4s307; CHECK-NEXT: ret308 %1 = sitofp <4 x i64> %a to <4 x half>309 ret <4 x half> %1310}311 312define <4 x half> @uitofp_i8(<4 x i8> %a) #0 {313; CHECK-CVT-SD-LABEL: uitofp_i8:314; CHECK-CVT-SD: // %bb.0:315; CHECK-CVT-SD-NEXT: bic v0.4h, #255, lsl #8316; CHECK-CVT-SD-NEXT: ushll v0.4s, v0.4h, #0317; CHECK-CVT-SD-NEXT: ucvtf v0.4s, v0.4s318; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v0.4s319; CHECK-CVT-SD-NEXT: ret320;321; CHECK-FP16-SD-LABEL: uitofp_i8:322; CHECK-FP16-SD: // %bb.0:323; CHECK-FP16-SD-NEXT: bic v0.4h, #255, lsl #8324; CHECK-FP16-SD-NEXT: ucvtf v0.4h, v0.4h325; CHECK-FP16-SD-NEXT: ret326;327; CHECK-CVT-GI-LABEL: uitofp_i8:328; CHECK-CVT-GI: // %bb.0:329; CHECK-CVT-GI-NEXT: movi v1.2d, #0x0000ff000000ff330; CHECK-CVT-GI-NEXT: ushll v0.4s, v0.4h, #0331; CHECK-CVT-GI-NEXT: and v0.16b, v0.16b, v1.16b332; CHECK-CVT-GI-NEXT: ucvtf v0.4s, v0.4s333; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v0.4s334; CHECK-CVT-GI-NEXT: ret335;336; CHECK-FP16-GI-LABEL: uitofp_i8:337; CHECK-FP16-GI: // %bb.0:338; CHECK-FP16-GI-NEXT: movi d1, #0xff00ff00ff00ff339; CHECK-FP16-GI-NEXT: and v0.8b, v0.8b, v1.8b340; CHECK-FP16-GI-NEXT: ucvtf v0.4h, v0.4h341; CHECK-FP16-GI-NEXT: ret342 %1 = uitofp <4 x i8> %a to <4 x half>343 ret <4 x half> %1344}345 346 347define <4 x half> @uitofp_i16(<4 x i16> %a) #0 {348; CHECK-CVT-LABEL: uitofp_i16:349; CHECK-CVT: // %bb.0:350; CHECK-CVT-NEXT: ushll v0.4s, v0.4h, #0351; CHECK-CVT-NEXT: ucvtf v0.4s, v0.4s352; CHECK-CVT-NEXT: fcvtn v0.4h, v0.4s353; CHECK-CVT-NEXT: ret354;355; CHECK-FP16-LABEL: uitofp_i16:356; CHECK-FP16: // %bb.0:357; CHECK-FP16-NEXT: ucvtf v0.4h, v0.4h358; CHECK-FP16-NEXT: ret359 %1 = uitofp <4 x i16> %a to <4 x half>360 ret <4 x half> %1361}362 363 364define <4 x half> @uitofp_i32(<4 x i32> %a) #0 {365; CHECK-LABEL: uitofp_i32:366; CHECK: // %bb.0:367; CHECK-NEXT: ucvtf v0.4s, v0.4s368; CHECK-NEXT: fcvtn v0.4h, v0.4s369; CHECK-NEXT: ret370 %1 = uitofp <4 x i32> %a to <4 x half>371 ret <4 x half> %1372}373 374 375define <4 x half> @uitofp_i64(<4 x i64> %a) #0 {376; CHECK-LABEL: uitofp_i64:377; CHECK: // %bb.0:378; CHECK-NEXT: ucvtf v0.2d, v0.2d379; CHECK-NEXT: ucvtf v1.2d, v1.2d380; CHECK-NEXT: fcvtn v0.2s, v0.2d381; CHECK-NEXT: fcvtn2 v0.4s, v1.2d382; CHECK-NEXT: fcvtn v0.4h, v0.4s383; CHECK-NEXT: ret384 %1 = uitofp <4 x i64> %a to <4 x half>385 ret <4 x half> %1386}387 388define void @test_insert_at_zero(half %a, ptr %b) #0 {389; CHECK-LABEL: test_insert_at_zero:390; CHECK: // %bb.0:391; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0392; CHECK-NEXT: str d0, [x0]393; CHECK-NEXT: ret394 %1 = insertelement <4 x half> undef, half %a, i64 0395 store <4 x half> %1, ptr %b, align 4396 ret void397}398 399define <4 x i8> @fptosi_i8(<4 x half> %a) #0 {400; CHECK-CVT-LABEL: fptosi_i8:401; CHECK-CVT: // %bb.0:402; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h403; CHECK-CVT-NEXT: fcvtzs v0.4s, v0.4s404; CHECK-CVT-NEXT: xtn v0.4h, v0.4s405; CHECK-CVT-NEXT: ret406;407; CHECK-FP16-LABEL: fptosi_i8:408; CHECK-FP16: // %bb.0:409; CHECK-FP16-NEXT: fcvtzs v0.4h, v0.4h410; CHECK-FP16-NEXT: ret411 %1 = fptosi<4 x half> %a to <4 x i8>412 ret <4 x i8> %1413}414 415define <4 x i16> @fptosi_i16(<4 x half> %a) #0 {416; CHECK-CVT-LABEL: fptosi_i16:417; CHECK-CVT: // %bb.0:418; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h419; CHECK-CVT-NEXT: fcvtzs v0.4s, v0.4s420; CHECK-CVT-NEXT: xtn v0.4h, v0.4s421; CHECK-CVT-NEXT: ret422;423; CHECK-FP16-LABEL: fptosi_i16:424; CHECK-FP16: // %bb.0:425; CHECK-FP16-NEXT: fcvtzs v0.4h, v0.4h426; CHECK-FP16-NEXT: ret427 %1 = fptosi<4 x half> %a to <4 x i16>428 ret <4 x i16> %1429}430 431define <4 x i8> @fptoui_i8(<4 x half> %a) #0 {432; CHECK-CVT-SD-LABEL: fptoui_i8:433; CHECK-CVT-SD: // %bb.0:434; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h435; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s436; CHECK-CVT-SD-NEXT: xtn v0.4h, v0.4s437; CHECK-CVT-SD-NEXT: ret438;439; CHECK-FP16-SD-LABEL: fptoui_i8:440; CHECK-FP16-SD: // %bb.0:441; CHECK-FP16-SD-NEXT: fcvtzs v0.4h, v0.4h442; CHECK-FP16-SD-NEXT: ret443;444; CHECK-CVT-GI-LABEL: fptoui_i8:445; CHECK-CVT-GI: // %bb.0:446; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h447; CHECK-CVT-GI-NEXT: fcvtzu v0.4s, v0.4s448; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s449; CHECK-CVT-GI-NEXT: ret450;451; CHECK-FP16-GI-LABEL: fptoui_i8:452; CHECK-FP16-GI: // %bb.0:453; CHECK-FP16-GI-NEXT: fcvtzu v0.4h, v0.4h454; CHECK-FP16-GI-NEXT: ret455; NOTE: fcvtzs selected here because the xtn shaves the sign bit456 %1 = fptoui<4 x half> %a to <4 x i8>457 ret <4 x i8> %1458}459 460define <4 x i16> @fptoui_i16(<4 x half> %a) #0 {461; CHECK-CVT-LABEL: fptoui_i16:462; CHECK-CVT: // %bb.0:463; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h464; CHECK-CVT-NEXT: fcvtzu v0.4s, v0.4s465; CHECK-CVT-NEXT: xtn v0.4h, v0.4s466; CHECK-CVT-NEXT: ret467;468; CHECK-FP16-LABEL: fptoui_i16:469; CHECK-FP16: // %bb.0:470; CHECK-FP16-NEXT: fcvtzu v0.4h, v0.4h471; CHECK-FP16-NEXT: ret472 %1 = fptoui<4 x half> %a to <4 x i16>473 ret <4 x i16> %1474}475 476define <4 x i1> @test_fcmp_une(<4 x half> %a, <4 x half> %b) #0 {477; CHECK-CVT-SD-LABEL: test_fcmp_une:478; CHECK-CVT-SD: // %bb.0:479; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h480; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h481; CHECK-CVT-SD-NEXT: fcmeq v0.4s, v0.4s, v1.4s482; CHECK-CVT-SD-NEXT: mvn v0.16b, v0.16b483; CHECK-CVT-SD-NEXT: xtn v0.4h, v0.4s484; CHECK-CVT-SD-NEXT: ret485;486; CHECK-FP16-LABEL: test_fcmp_une:487; CHECK-FP16: // %bb.0:488; CHECK-FP16-NEXT: fcmeq v0.4h, v0.4h, v1.4h489; CHECK-FP16-NEXT: mvn v0.8b, v0.8b490; CHECK-FP16-NEXT: ret491;492; CHECK-CVT-GI-LABEL: test_fcmp_une:493; CHECK-CVT-GI: // %bb.0:494; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h495; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h496; CHECK-CVT-GI-NEXT: fcmeq v0.4s, v0.4s, v1.4s497; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b498; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s499; CHECK-CVT-GI-NEXT: ret500 501 %1 = fcmp une <4 x half> %a, %b502 ret <4 x i1> %1503}504 505define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 {506; CHECK-CVT-SD-LABEL: test_fcmp_ueq:507; CHECK-CVT-SD: // %bb.0:508; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h509; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h510; CHECK-CVT-SD-NEXT: fcmgt v2.4s, v0.4s, v1.4s511; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s512; CHECK-CVT-SD-NEXT: orr v0.16b, v0.16b, v2.16b513; CHECK-CVT-SD-NEXT: xtn v0.4h, v0.4s514; CHECK-CVT-SD-NEXT: mvn v0.8b, v0.8b515; CHECK-CVT-SD-NEXT: ret516;517; CHECK-FP16-LABEL: test_fcmp_ueq:518; CHECK-FP16: // %bb.0:519; CHECK-FP16-NEXT: fcmgt v2.4h, v0.4h, v1.4h520; CHECK-FP16-NEXT: fcmgt v0.4h, v1.4h, v0.4h521; CHECK-FP16-NEXT: orr v0.8b, v0.8b, v2.8b522; CHECK-FP16-NEXT: mvn v0.8b, v0.8b523; CHECK-FP16-NEXT: ret524;525; CHECK-CVT-GI-LABEL: test_fcmp_ueq:526; CHECK-CVT-GI: // %bb.0:527; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h528; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h529; CHECK-CVT-GI-NEXT: fcmgt v2.4s, v0.4s, v1.4s530; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s531; CHECK-CVT-GI-NEXT: orr v0.16b, v0.16b, v2.16b532; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b533; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s534; CHECK-CVT-GI-NEXT: ret535 536 %1 = fcmp ueq <4 x half> %a, %b537 ret <4 x i1> %1538}539 540define <4 x i1> @test_fcmp_ugt(<4 x half> %a, <4 x half> %b) #0 {541; CHECK-CVT-SD-LABEL: test_fcmp_ugt:542; CHECK-CVT-SD: // %bb.0:543; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h544; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h545; CHECK-CVT-SD-NEXT: fcmge v0.4s, v1.4s, v0.4s546; CHECK-CVT-SD-NEXT: xtn v0.4h, v0.4s547; CHECK-CVT-SD-NEXT: mvn v0.8b, v0.8b548; CHECK-CVT-SD-NEXT: ret549;550; CHECK-FP16-LABEL: test_fcmp_ugt:551; CHECK-FP16: // %bb.0:552; CHECK-FP16-NEXT: fcmge v0.4h, v1.4h, v0.4h553; CHECK-FP16-NEXT: mvn v0.8b, v0.8b554; CHECK-FP16-NEXT: ret555;556; CHECK-CVT-GI-LABEL: test_fcmp_ugt:557; CHECK-CVT-GI: // %bb.0:558; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h559; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h560; CHECK-CVT-GI-NEXT: fcmge v0.4s, v1.4s, v0.4s561; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b562; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s563; CHECK-CVT-GI-NEXT: ret564 565 %1 = fcmp ugt <4 x half> %a, %b566 ret <4 x i1> %1567}568 569define <4 x i1> @test_fcmp_uge(<4 x half> %a, <4 x half> %b) #0 {570; CHECK-CVT-SD-LABEL: test_fcmp_uge:571; CHECK-CVT-SD: // %bb.0:572; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h573; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h574; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s575; CHECK-CVT-SD-NEXT: xtn v0.4h, v0.4s576; CHECK-CVT-SD-NEXT: mvn v0.8b, v0.8b577; CHECK-CVT-SD-NEXT: ret578;579; CHECK-FP16-LABEL: test_fcmp_uge:580; CHECK-FP16: // %bb.0:581; CHECK-FP16-NEXT: fcmgt v0.4h, v1.4h, v0.4h582; CHECK-FP16-NEXT: mvn v0.8b, v0.8b583; CHECK-FP16-NEXT: ret584;585; CHECK-CVT-GI-LABEL: test_fcmp_uge:586; CHECK-CVT-GI: // %bb.0:587; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h588; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h589; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s590; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b591; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s592; CHECK-CVT-GI-NEXT: ret593 594 %1 = fcmp uge <4 x half> %a, %b595 ret <4 x i1> %1596}597 598define <4 x i1> @test_fcmp_ult(<4 x half> %a, <4 x half> %b) #0 {599; CHECK-CVT-SD-LABEL: test_fcmp_ult:600; CHECK-CVT-SD: // %bb.0:601; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h602; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h603; CHECK-CVT-SD-NEXT: fcmge v0.4s, v0.4s, v1.4s604; CHECK-CVT-SD-NEXT: xtn v0.4h, v0.4s605; CHECK-CVT-SD-NEXT: mvn v0.8b, v0.8b606; CHECK-CVT-SD-NEXT: ret607;608; CHECK-FP16-LABEL: test_fcmp_ult:609; CHECK-FP16: // %bb.0:610; CHECK-FP16-NEXT: fcmge v0.4h, v0.4h, v1.4h611; CHECK-FP16-NEXT: mvn v0.8b, v0.8b612; CHECK-FP16-NEXT: ret613;614; CHECK-CVT-GI-LABEL: test_fcmp_ult:615; CHECK-CVT-GI: // %bb.0:616; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h617; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h618; CHECK-CVT-GI-NEXT: fcmge v0.4s, v0.4s, v1.4s619; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b620; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s621; CHECK-CVT-GI-NEXT: ret622 623 %1 = fcmp ult <4 x half> %a, %b624 ret <4 x i1> %1625}626 627define <4 x i1> @test_fcmp_ule(<4 x half> %a, <4 x half> %b) #0 {628; CHECK-CVT-SD-LABEL: test_fcmp_ule:629; CHECK-CVT-SD: // %bb.0:630; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h631; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h632; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v0.4s, v1.4s633; CHECK-CVT-SD-NEXT: xtn v0.4h, v0.4s634; CHECK-CVT-SD-NEXT: mvn v0.8b, v0.8b635; CHECK-CVT-SD-NEXT: ret636;637; CHECK-FP16-LABEL: test_fcmp_ule:638; CHECK-FP16: // %bb.0:639; CHECK-FP16-NEXT: fcmgt v0.4h, v0.4h, v1.4h640; CHECK-FP16-NEXT: mvn v0.8b, v0.8b641; CHECK-FP16-NEXT: ret642;643; CHECK-CVT-GI-LABEL: test_fcmp_ule:644; CHECK-CVT-GI: // %bb.0:645; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h646; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h647; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v0.4s, v1.4s648; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b649; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s650; CHECK-CVT-GI-NEXT: ret651 652 %1 = fcmp ule <4 x half> %a, %b653 ret <4 x i1> %1654}655 656define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 {657; CHECK-CVT-SD-LABEL: test_fcmp_uno:658; CHECK-CVT-SD: // %bb.0:659; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h660; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h661; CHECK-CVT-SD-NEXT: fcmge v2.4s, v0.4s, v1.4s662; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s663; CHECK-CVT-SD-NEXT: orr v0.16b, v0.16b, v2.16b664; CHECK-CVT-SD-NEXT: xtn v0.4h, v0.4s665; CHECK-CVT-SD-NEXT: mvn v0.8b, v0.8b666; CHECK-CVT-SD-NEXT: ret667;668; CHECK-FP16-LABEL: test_fcmp_uno:669; CHECK-FP16: // %bb.0:670; CHECK-FP16-NEXT: fcmge v2.4h, v0.4h, v1.4h671; CHECK-FP16-NEXT: fcmgt v0.4h, v1.4h, v0.4h672; CHECK-FP16-NEXT: orr v0.8b, v0.8b, v2.8b673; CHECK-FP16-NEXT: mvn v0.8b, v0.8b674; CHECK-FP16-NEXT: ret675;676; CHECK-CVT-GI-LABEL: test_fcmp_uno:677; CHECK-CVT-GI: // %bb.0:678; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h679; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h680; CHECK-CVT-GI-NEXT: fcmge v2.4s, v0.4s, v1.4s681; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s682; CHECK-CVT-GI-NEXT: orr v0.16b, v0.16b, v2.16b683; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b684; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s685; CHECK-CVT-GI-NEXT: ret686 687 %1 = fcmp uno <4 x half> %a, %b688 ret <4 x i1> %1689}690 691define <4 x i1> @test_fcmp_one(<4 x half> %a, <4 x half> %b) #0 {692; CHECK-CVT-SD-LABEL: test_fcmp_one:693; CHECK-CVT-SD: // %bb.0:694; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h695; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h696; CHECK-CVT-SD-NEXT: fcmgt v2.4s, v0.4s, v1.4s697; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s698; CHECK-CVT-SD-NEXT: orr v0.16b, v0.16b, v2.16b699; CHECK-CVT-SD-NEXT: xtn v0.4h, v0.4s700; CHECK-CVT-SD-NEXT: ret701;702; CHECK-FP16-LABEL: test_fcmp_one:703; CHECK-FP16: // %bb.0:704; CHECK-FP16-NEXT: fcmgt v2.4h, v0.4h, v1.4h705; CHECK-FP16-NEXT: fcmgt v0.4h, v1.4h, v0.4h706; CHECK-FP16-NEXT: orr v0.8b, v0.8b, v2.8b707; CHECK-FP16-NEXT: ret708;709; CHECK-CVT-GI-LABEL: test_fcmp_one:710; CHECK-CVT-GI: // %bb.0:711; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h712; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h713; CHECK-CVT-GI-NEXT: fcmgt v2.4s, v0.4s, v1.4s714; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s715; CHECK-CVT-GI-NEXT: orr v0.16b, v0.16b, v2.16b716; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s717; CHECK-CVT-GI-NEXT: ret718 719 %1 = fcmp one <4 x half> %a, %b720 ret <4 x i1> %1721}722 723define <4 x i1> @test_fcmp_oeq(<4 x half> %a, <4 x half> %b) #0 {724; CHECK-CVT-SD-LABEL: test_fcmp_oeq:725; CHECK-CVT-SD: // %bb.0:726; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h727; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h728; CHECK-CVT-SD-NEXT: fcmeq v0.4s, v0.4s, v1.4s729; CHECK-CVT-SD-NEXT: xtn v0.4h, v0.4s730; CHECK-CVT-SD-NEXT: ret731;732; CHECK-FP16-LABEL: test_fcmp_oeq:733; CHECK-FP16: // %bb.0:734; CHECK-FP16-NEXT: fcmeq v0.4h, v0.4h, v1.4h735; CHECK-FP16-NEXT: ret736;737; CHECK-CVT-GI-LABEL: test_fcmp_oeq:738; CHECK-CVT-GI: // %bb.0:739; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h740; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h741; CHECK-CVT-GI-NEXT: fcmeq v0.4s, v0.4s, v1.4s742; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s743; CHECK-CVT-GI-NEXT: ret744 745 %1 = fcmp oeq <4 x half> %a, %b746 ret <4 x i1> %1747}748 749define <4 x i1> @test_fcmp_ogt(<4 x half> %a, <4 x half> %b) #0 {750; CHECK-CVT-SD-LABEL: test_fcmp_ogt:751; CHECK-CVT-SD: // %bb.0:752; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h753; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h754; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v0.4s, v1.4s755; CHECK-CVT-SD-NEXT: xtn v0.4h, v0.4s756; CHECK-CVT-SD-NEXT: ret757;758; CHECK-FP16-LABEL: test_fcmp_ogt:759; CHECK-FP16: // %bb.0:760; CHECK-FP16-NEXT: fcmgt v0.4h, v0.4h, v1.4h761; CHECK-FP16-NEXT: ret762;763; CHECK-CVT-GI-LABEL: test_fcmp_ogt:764; CHECK-CVT-GI: // %bb.0:765; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h766; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h767; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v0.4s, v1.4s768; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s769; CHECK-CVT-GI-NEXT: ret770 771 %1 = fcmp ogt <4 x half> %a, %b772 ret <4 x i1> %1773}774 775define <4 x i1> @test_fcmp_oge(<4 x half> %a, <4 x half> %b) #0 {776; CHECK-CVT-SD-LABEL: test_fcmp_oge:777; CHECK-CVT-SD: // %bb.0:778; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h779; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h780; CHECK-CVT-SD-NEXT: fcmge v0.4s, v0.4s, v1.4s781; CHECK-CVT-SD-NEXT: xtn v0.4h, v0.4s782; CHECK-CVT-SD-NEXT: ret783;784; CHECK-FP16-LABEL: test_fcmp_oge:785; CHECK-FP16: // %bb.0:786; CHECK-FP16-NEXT: fcmge v0.4h, v0.4h, v1.4h787; CHECK-FP16-NEXT: ret788;789; CHECK-CVT-GI-LABEL: test_fcmp_oge:790; CHECK-CVT-GI: // %bb.0:791; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h792; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h793; CHECK-CVT-GI-NEXT: fcmge v0.4s, v0.4s, v1.4s794; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s795; CHECK-CVT-GI-NEXT: ret796 797 %1 = fcmp oge <4 x half> %a, %b798 ret <4 x i1> %1799}800 801define <4 x i1> @test_fcmp_olt(<4 x half> %a, <4 x half> %b) #0 {802; CHECK-CVT-LABEL: test_fcmp_olt:803; CHECK-CVT: // %bb.0:804; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h805; CHECK-CVT-NEXT: fcvtl v1.4s, v1.4h806; CHECK-CVT-NEXT: fcmgt v0.4s, v1.4s, v0.4s807; CHECK-CVT-NEXT: xtn v0.4h, v0.4s808; CHECK-CVT-NEXT: ret809;810; CHECK-FP16-LABEL: test_fcmp_olt:811; CHECK-FP16: // %bb.0:812; CHECK-FP16-NEXT: fcmgt v0.4h, v1.4h, v0.4h813; CHECK-FP16-NEXT: ret814 815 %1 = fcmp olt <4 x half> %a, %b816 ret <4 x i1> %1817}818 819define <4 x i1> @test_fcmp_ole(<4 x half> %a, <4 x half> %b) #0 {820; CHECK-CVT-LABEL: test_fcmp_ole:821; CHECK-CVT: // %bb.0:822; CHECK-CVT-NEXT: fcvtl v0.4s, v0.4h823; CHECK-CVT-NEXT: fcvtl v1.4s, v1.4h824; CHECK-CVT-NEXT: fcmge v0.4s, v1.4s, v0.4s825; CHECK-CVT-NEXT: xtn v0.4h, v0.4s826; CHECK-CVT-NEXT: ret827;828; CHECK-FP16-LABEL: test_fcmp_ole:829; CHECK-FP16: // %bb.0:830; CHECK-FP16-NEXT: fcmge v0.4h, v1.4h, v0.4h831; CHECK-FP16-NEXT: ret832 833 %1 = fcmp ole <4 x half> %a, %b834 ret <4 x i1> %1835}836 837define <4 x i1> @test_fcmp_ord(<4 x half> %a, <4 x half> %b) #0 {838; CHECK-CVT-SD-LABEL: test_fcmp_ord:839; CHECK-CVT-SD: // %bb.0:840; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h841; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h842; CHECK-CVT-SD-NEXT: fcmge v2.4s, v0.4s, v1.4s843; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s844; CHECK-CVT-SD-NEXT: orr v0.16b, v0.16b, v2.16b845; CHECK-CVT-SD-NEXT: xtn v0.4h, v0.4s846; CHECK-CVT-SD-NEXT: ret847;848; CHECK-FP16-LABEL: test_fcmp_ord:849; CHECK-FP16: // %bb.0:850; CHECK-FP16-NEXT: fcmge v2.4h, v0.4h, v1.4h851; CHECK-FP16-NEXT: fcmgt v0.4h, v1.4h, v0.4h852; CHECK-FP16-NEXT: orr v0.8b, v0.8b, v2.8b853; CHECK-FP16-NEXT: ret854;855; CHECK-CVT-GI-LABEL: test_fcmp_ord:856; CHECK-CVT-GI: // %bb.0:857; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h858; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v1.4h859; CHECK-CVT-GI-NEXT: fcmge v2.4s, v0.4s, v1.4s860; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s861; CHECK-CVT-GI-NEXT: orr v0.16b, v0.16b, v2.16b862; CHECK-CVT-GI-NEXT: xtn v0.4h, v0.4s863; CHECK-CVT-GI-NEXT: ret864 865 %1 = fcmp ord <4 x half> %a, %b866 ret <4 x i1> %1867}868 869attributes #0 = { nounwind }870