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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 -mattr=-fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT,CHECK-CVT-SD3; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-SD4; RUN: llc < %s -mtriple=aarch64 -mattr=-fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-CVT,CHECK-CVT-GI5; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-GI6 7define <8 x half> @add_h(<8 x half> %a, <8 x half> %b) {8; CHECK-CVT-SD-LABEL: add_h:9; CHECK-CVT-SD: // %bb.0: // %entry10; CHECK-CVT-SD-NEXT: fcvtl v2.4s, v1.4h11; CHECK-CVT-SD-NEXT: fcvtl v3.4s, v0.4h12; CHECK-CVT-SD-NEXT: fcvtl2 v1.4s, v1.8h13; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h14; CHECK-CVT-SD-NEXT: fadd v2.4s, v3.4s, v2.4s15; CHECK-CVT-SD-NEXT: fadd v1.4s, v0.4s, v1.4s16; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v2.4s17; CHECK-CVT-SD-NEXT: fcvtn2 v0.8h, v1.4s18; CHECK-CVT-SD-NEXT: ret19;20; CHECK-FP16-LABEL: add_h:21; CHECK-FP16: // %bb.0: // %entry22; CHECK-FP16-NEXT: fadd v0.8h, v0.8h, v1.8h23; CHECK-FP16-NEXT: ret24;25; CHECK-CVT-GI-LABEL: add_h:26; CHECK-CVT-GI: // %bb.0: // %entry27; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h28; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h29; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h30; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h31; CHECK-CVT-GI-NEXT: fadd v2.4s, v2.4s, v3.4s32; CHECK-CVT-GI-NEXT: fadd v1.4s, v0.4s, v1.4s33; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v2.4s34; CHECK-CVT-GI-NEXT: fcvtn2 v0.8h, v1.4s35; CHECK-CVT-GI-NEXT: ret36entry:37 %0 = fadd <8 x half> %a, %b38 ret <8 x half> %039}40 41 42define <8 x half> @sub_h(<8 x half> %a, <8 x half> %b) {43; CHECK-CVT-SD-LABEL: sub_h:44; CHECK-CVT-SD: // %bb.0: // %entry45; CHECK-CVT-SD-NEXT: fcvtl v2.4s, v1.4h46; CHECK-CVT-SD-NEXT: fcvtl v3.4s, v0.4h47; CHECK-CVT-SD-NEXT: fcvtl2 v1.4s, v1.8h48; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h49; CHECK-CVT-SD-NEXT: fsub v2.4s, v3.4s, v2.4s50; CHECK-CVT-SD-NEXT: fsub v1.4s, v0.4s, v1.4s51; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v2.4s52; CHECK-CVT-SD-NEXT: fcvtn2 v0.8h, v1.4s53; CHECK-CVT-SD-NEXT: ret54;55; CHECK-FP16-LABEL: sub_h:56; CHECK-FP16: // %bb.0: // %entry57; CHECK-FP16-NEXT: fsub v0.8h, v0.8h, v1.8h58; CHECK-FP16-NEXT: ret59;60; CHECK-CVT-GI-LABEL: sub_h:61; CHECK-CVT-GI: // %bb.0: // %entry62; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h63; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h64; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h65; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h66; CHECK-CVT-GI-NEXT: fsub v2.4s, v2.4s, v3.4s67; CHECK-CVT-GI-NEXT: fsub v1.4s, v0.4s, v1.4s68; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v2.4s69; CHECK-CVT-GI-NEXT: fcvtn2 v0.8h, v1.4s70; CHECK-CVT-GI-NEXT: ret71entry:72 %0 = fsub <8 x half> %a, %b73 ret <8 x half> %074}75 76 77define <8 x half> @mul_h(<8 x half> %a, <8 x half> %b) {78; CHECK-CVT-SD-LABEL: mul_h:79; CHECK-CVT-SD: // %bb.0: // %entry80; CHECK-CVT-SD-NEXT: fcvtl v2.4s, v1.4h81; CHECK-CVT-SD-NEXT: fcvtl v3.4s, v0.4h82; CHECK-CVT-SD-NEXT: fcvtl2 v1.4s, v1.8h83; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h84; CHECK-CVT-SD-NEXT: fmul v2.4s, v3.4s, v2.4s85; CHECK-CVT-SD-NEXT: fmul v1.4s, v0.4s, v1.4s86; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v2.4s87; CHECK-CVT-SD-NEXT: fcvtn2 v0.8h, v1.4s88; CHECK-CVT-SD-NEXT: ret89;90; CHECK-FP16-LABEL: mul_h:91; CHECK-FP16: // %bb.0: // %entry92; CHECK-FP16-NEXT: fmul v0.8h, v0.8h, v1.8h93; CHECK-FP16-NEXT: ret94;95; CHECK-CVT-GI-LABEL: mul_h:96; CHECK-CVT-GI: // %bb.0: // %entry97; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h98; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h99; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h100; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h101; CHECK-CVT-GI-NEXT: fmul v2.4s, v2.4s, v3.4s102; CHECK-CVT-GI-NEXT: fmul v1.4s, v0.4s, v1.4s103; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v2.4s104; CHECK-CVT-GI-NEXT: fcvtn2 v0.8h, v1.4s105; CHECK-CVT-GI-NEXT: ret106entry:107 %0 = fmul <8 x half> %a, %b108 ret <8 x half> %0109}110 111 112define <8 x half> @div_h(<8 x half> %a, <8 x half> %b) {113; CHECK-CVT-SD-LABEL: div_h:114; CHECK-CVT-SD: // %bb.0: // %entry115; CHECK-CVT-SD-NEXT: fcvtl v2.4s, v1.4h116; CHECK-CVT-SD-NEXT: fcvtl v3.4s, v0.4h117; CHECK-CVT-SD-NEXT: fcvtl2 v1.4s, v1.8h118; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h119; CHECK-CVT-SD-NEXT: fdiv v2.4s, v3.4s, v2.4s120; CHECK-CVT-SD-NEXT: fdiv v1.4s, v0.4s, v1.4s121; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v2.4s122; CHECK-CVT-SD-NEXT: fcvtn2 v0.8h, v1.4s123; CHECK-CVT-SD-NEXT: ret124;125; CHECK-FP16-LABEL: div_h:126; CHECK-FP16: // %bb.0: // %entry127; CHECK-FP16-NEXT: fdiv v0.8h, v0.8h, v1.8h128; CHECK-FP16-NEXT: ret129;130; CHECK-CVT-GI-LABEL: div_h:131; CHECK-CVT-GI: // %bb.0: // %entry132; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h133; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h134; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h135; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h136; CHECK-CVT-GI-NEXT: fdiv v2.4s, v2.4s, v3.4s137; CHECK-CVT-GI-NEXT: fdiv v1.4s, v0.4s, v1.4s138; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v2.4s139; CHECK-CVT-GI-NEXT: fcvtn2 v0.8h, v1.4s140; CHECK-CVT-GI-NEXT: ret141entry:142 %0 = fdiv <8 x half> %a, %b143 ret <8 x half> %0144}145 146 147define <8 x half> @load_h(ptr %a) {148; CHECK-LABEL: load_h:149; CHECK: // %bb.0: // %entry150; CHECK-NEXT: ldr q0, [x0]151; CHECK-NEXT: ret152entry:153 %0 = load <8 x half>, ptr %a, align 4154 ret <8 x half> %0155}156 157 158define void @store_h(ptr %a, <8 x half> %b) {159; CHECK-LABEL: store_h:160; CHECK: // %bb.0: // %entry161; CHECK-NEXT: str q0, [x0]162; CHECK-NEXT: ret163entry:164 store <8 x half> %b, ptr %a, align 4165 ret void166}167 168define <8 x half> @s_to_h(<8 x float> %a) {169; CHECK-LABEL: s_to_h:170; CHECK: // %bb.0:171; CHECK-NEXT: fcvtn v0.4h, v0.4s172; CHECK-NEXT: fcvtn2 v0.8h, v1.4s173; CHECK-NEXT: ret174 %1 = fptrunc <8 x float> %a to <8 x half>175 ret <8 x half> %1176}177 178define <8 x half> @d_to_h(<8 x double> %a) {179; CHECK-LABEL: d_to_h:180; CHECK: // %bb.0:181; CHECK-NEXT: fcvtxn v0.2s, v0.2d182; CHECK-NEXT: fcvtxn v2.2s, v2.2d183; CHECK-NEXT: fcvtxn2 v0.4s, v1.2d184; CHECK-NEXT: fcvtxn2 v2.4s, v3.2d185; CHECK-NEXT: fcvtn v0.4h, v0.4s186; CHECK-NEXT: fcvtn2 v0.8h, v2.4s187; CHECK-NEXT: ret188 %1 = fptrunc <8 x double> %a to <8 x half>189 ret <8 x half> %1190}191 192define <8 x float> @h_to_s(<8 x half> %a) {193; CHECK-CVT-SD-LABEL: h_to_s:194; CHECK-CVT-SD: // %bb.0:195; CHECK-CVT-SD-NEXT: fcvtl2 v1.4s, v0.8h196; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h197; CHECK-CVT-SD-NEXT: ret198;199; CHECK-FP16-SD-LABEL: h_to_s:200; CHECK-FP16-SD: // %bb.0:201; CHECK-FP16-SD-NEXT: fcvtl2 v1.4s, v0.8h202; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h203; CHECK-FP16-SD-NEXT: ret204;205; CHECK-CVT-GI-LABEL: h_to_s:206; CHECK-CVT-GI: // %bb.0:207; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h208; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v0.8h209; CHECK-CVT-GI-NEXT: mov v0.16b, v2.16b210; CHECK-CVT-GI-NEXT: ret211;212; CHECK-FP16-GI-LABEL: h_to_s:213; CHECK-FP16-GI: // %bb.0:214; CHECK-FP16-GI-NEXT: fcvtl v2.4s, v0.4h215; CHECK-FP16-GI-NEXT: fcvtl2 v1.4s, v0.8h216; CHECK-FP16-GI-NEXT: mov v0.16b, v2.16b217; CHECK-FP16-GI-NEXT: ret218 %1 = fpext <8 x half> %a to <8 x float>219 ret <8 x float> %1220}221 222define <8 x double> @h_to_d(<8 x half> %a) {223; CHECK-CVT-SD-LABEL: h_to_d:224; CHECK-CVT-SD: // %bb.0:225; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h226; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v0.8h227; CHECK-CVT-SD-NEXT: fcvtl v0.2d, v1.2s228; CHECK-CVT-SD-NEXT: fcvtl2 v3.2d, v2.4s229; CHECK-CVT-SD-NEXT: fcvtl2 v1.2d, v1.4s230; CHECK-CVT-SD-NEXT: fcvtl v2.2d, v2.2s231; CHECK-CVT-SD-NEXT: ret232;233; CHECK-FP16-SD-LABEL: h_to_d:234; CHECK-FP16-SD: // %bb.0:235; CHECK-FP16-SD-NEXT: fcvtl v1.4s, v0.4h236; CHECK-FP16-SD-NEXT: fcvtl2 v2.4s, v0.8h237; CHECK-FP16-SD-NEXT: fcvtl v0.2d, v1.2s238; CHECK-FP16-SD-NEXT: fcvtl2 v3.2d, v2.4s239; CHECK-FP16-SD-NEXT: fcvtl2 v1.2d, v1.4s240; CHECK-FP16-SD-NEXT: fcvtl v2.2d, v2.2s241; CHECK-FP16-SD-NEXT: ret242;243; CHECK-CVT-GI-LABEL: h_to_d:244; CHECK-CVT-GI: // %bb.0:245; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v0.4h246; CHECK-CVT-GI-NEXT: fcvtl2 v3.4s, v0.8h247; CHECK-CVT-GI-NEXT: fcvtl v0.2d, v1.2s248; CHECK-CVT-GI-NEXT: fcvtl2 v1.2d, v1.4s249; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v3.2s250; CHECK-CVT-GI-NEXT: fcvtl2 v3.2d, v3.4s251; CHECK-CVT-GI-NEXT: ret252;253; CHECK-FP16-GI-LABEL: h_to_d:254; CHECK-FP16-GI: // %bb.0:255; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h256; CHECK-FP16-GI-NEXT: fcvtl2 v3.4s, v0.8h257; CHECK-FP16-GI-NEXT: fcvtl v0.2d, v1.2s258; CHECK-FP16-GI-NEXT: fcvtl2 v1.2d, v1.4s259; CHECK-FP16-GI-NEXT: fcvtl v2.2d, v3.2s260; CHECK-FP16-GI-NEXT: fcvtl2 v3.2d, v3.4s261; CHECK-FP16-GI-NEXT: ret262 %1 = fpext <8 x half> %a to <8 x double>263 ret <8 x double> %1264}265 266 267define <8 x half> @bitcast_i_to_h(float, <8 x i16> %a) {268; CHECK-LABEL: bitcast_i_to_h:269; CHECK: // %bb.0:270; CHECK-NEXT: mov v0.16b, v1.16b271; CHECK-NEXT: ret272 %2 = bitcast <8 x i16> %a to <8 x half>273 ret <8 x half> %2274}275 276define <8 x i16> @bitcast_h_to_i(float, <8 x half> %a) {277; CHECK-LABEL: bitcast_h_to_i:278; CHECK: // %bb.0:279; CHECK-NEXT: mov v0.16b, v1.16b280; CHECK-NEXT: ret281 %2 = bitcast <8 x half> %a to <8 x i16>282 ret <8 x i16> %2283}284 285define <4 x half> @sitofp_v4i8(<4 x i8> %a) #0 {286; CHECK-CVT-SD-LABEL: sitofp_v4i8:287; CHECK-CVT-SD: // %bb.0:288; CHECK-CVT-SD-NEXT: shl v0.4h, v0.4h, #8289; CHECK-CVT-SD-NEXT: sshr v0.4h, v0.4h, #8290; CHECK-CVT-SD-NEXT: sshll v0.4s, v0.4h, #0291; CHECK-CVT-SD-NEXT: scvtf v0.4s, v0.4s292; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v0.4s293; CHECK-CVT-SD-NEXT: ret294;295; CHECK-FP16-LABEL: sitofp_v4i8:296; CHECK-FP16: // %bb.0:297; CHECK-FP16-NEXT: shl v0.4h, v0.4h, #8298; CHECK-FP16-NEXT: sshr v0.4h, v0.4h, #8299; CHECK-FP16-NEXT: scvtf v0.4h, v0.4h300; CHECK-FP16-NEXT: ret301;302; CHECK-CVT-GI-LABEL: sitofp_v4i8:303; CHECK-CVT-GI: // %bb.0:304; CHECK-CVT-GI-NEXT: ushll v0.4s, v0.4h, #0305; CHECK-CVT-GI-NEXT: shl v0.4s, v0.4s, #24306; CHECK-CVT-GI-NEXT: sshr v0.4s, v0.4s, #24307; CHECK-CVT-GI-NEXT: scvtf v0.4s, v0.4s308; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v0.4s309; CHECK-CVT-GI-NEXT: ret310 %1 = sitofp <4 x i8> %a to <4 x half>311 ret <4 x half> %1312}313 314define <8 x half> @sitofp_v8i8(<8 x i8> %a) #0 {315; CHECK-CVT-SD-LABEL: sitofp_v8i8:316; CHECK-CVT-SD: // %bb.0:317; CHECK-CVT-SD-NEXT: sshll v0.8h, v0.8b, #0318; CHECK-CVT-SD-NEXT: sshll v1.4s, v0.4h, #0319; CHECK-CVT-SD-NEXT: sshll2 v2.4s, v0.8h, #0320; CHECK-CVT-SD-NEXT: scvtf v1.4s, v1.4s321; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v1.4s322; CHECK-CVT-SD-NEXT: scvtf v1.4s, v2.4s323; CHECK-CVT-SD-NEXT: fcvtn2 v0.8h, v1.4s324; CHECK-CVT-SD-NEXT: ret325;326; CHECK-FP16-LABEL: sitofp_v8i8:327; CHECK-FP16: // %bb.0:328; CHECK-FP16-NEXT: sshll v0.8h, v0.8b, #0329; CHECK-FP16-NEXT: scvtf v0.8h, v0.8h330; CHECK-FP16-NEXT: ret331;332; CHECK-CVT-GI-LABEL: sitofp_v8i8:333; CHECK-CVT-GI: // %bb.0:334; CHECK-CVT-GI-NEXT: sshll v0.8h, v0.8b, #0335; CHECK-CVT-GI-NEXT: sshll v1.4s, v0.4h, #0336; CHECK-CVT-GI-NEXT: sshll2 v0.4s, v0.8h, #0337; CHECK-CVT-GI-NEXT: scvtf v1.4s, v1.4s338; CHECK-CVT-GI-NEXT: scvtf v2.4s, v0.4s339; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v1.4s340; CHECK-CVT-GI-NEXT: fcvtn2 v0.8h, v2.4s341; CHECK-CVT-GI-NEXT: ret342 %1 = sitofp <8 x i8> %a to <8 x half>343 ret <8 x half> %1344}345 346define <16 x half> @sitofp_v16i8(<16 x i8> %a) #0 {347; CHECK-CVT-SD-LABEL: sitofp_v16i8:348; CHECK-CVT-SD: // %bb.0:349; CHECK-CVT-SD-NEXT: sshll2 v1.8h, v0.16b, #0350; CHECK-CVT-SD-NEXT: sshll v0.8h, v0.8b, #0351; CHECK-CVT-SD-NEXT: sshll v2.4s, v1.4h, #0352; CHECK-CVT-SD-NEXT: sshll v3.4s, v0.4h, #0353; CHECK-CVT-SD-NEXT: sshll2 v4.4s, v1.8h, #0354; CHECK-CVT-SD-NEXT: sshll2 v5.4s, v0.8h, #0355; CHECK-CVT-SD-NEXT: scvtf v2.4s, v2.4s356; CHECK-CVT-SD-NEXT: scvtf v3.4s, v3.4s357; CHECK-CVT-SD-NEXT: fcvtn v1.4h, v2.4s358; CHECK-CVT-SD-NEXT: scvtf v2.4s, v4.4s359; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v3.4s360; CHECK-CVT-SD-NEXT: scvtf v3.4s, v5.4s361; CHECK-CVT-SD-NEXT: fcvtn2 v1.8h, v2.4s362; CHECK-CVT-SD-NEXT: fcvtn2 v0.8h, v3.4s363; CHECK-CVT-SD-NEXT: ret364;365; CHECK-FP16-SD-LABEL: sitofp_v16i8:366; CHECK-FP16-SD: // %bb.0:367; CHECK-FP16-SD-NEXT: sshll2 v1.8h, v0.16b, #0368; CHECK-FP16-SD-NEXT: sshll v0.8h, v0.8b, #0369; CHECK-FP16-SD-NEXT: scvtf v1.8h, v1.8h370; CHECK-FP16-SD-NEXT: scvtf v0.8h, v0.8h371; CHECK-FP16-SD-NEXT: ret372;373; CHECK-CVT-GI-LABEL: sitofp_v16i8:374; CHECK-CVT-GI: // %bb.0:375; CHECK-CVT-GI-NEXT: sshll v1.8h, v0.8b, #0376; CHECK-CVT-GI-NEXT: sshll2 v0.8h, v0.16b, #0377; CHECK-CVT-GI-NEXT: sshll v2.4s, v1.4h, #0378; CHECK-CVT-GI-NEXT: sshll v3.4s, v0.4h, #0379; CHECK-CVT-GI-NEXT: sshll2 v1.4s, v1.8h, #0380; CHECK-CVT-GI-NEXT: sshll2 v0.4s, v0.8h, #0381; CHECK-CVT-GI-NEXT: scvtf v2.4s, v2.4s382; CHECK-CVT-GI-NEXT: scvtf v3.4s, v3.4s383; CHECK-CVT-GI-NEXT: scvtf v4.4s, v1.4s384; CHECK-CVT-GI-NEXT: scvtf v5.4s, v0.4s385; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v2.4s386; CHECK-CVT-GI-NEXT: fcvtn v1.4h, v3.4s387; CHECK-CVT-GI-NEXT: fcvtn2 v0.8h, v4.4s388; CHECK-CVT-GI-NEXT: fcvtn2 v1.8h, v5.4s389; CHECK-CVT-GI-NEXT: ret390;391; CHECK-FP16-GI-LABEL: sitofp_v16i8:392; CHECK-FP16-GI: // %bb.0:393; CHECK-FP16-GI-NEXT: sshll v1.8h, v0.8b, #0394; CHECK-FP16-GI-NEXT: sshll2 v2.8h, v0.16b, #0395; CHECK-FP16-GI-NEXT: scvtf v0.8h, v1.8h396; CHECK-FP16-GI-NEXT: scvtf v1.8h, v2.8h397; CHECK-FP16-GI-NEXT: ret398 %1 = sitofp <16 x i8> %a to <16 x half>399 ret <16 x half> %1400}401 402define <8 x half> @sitofp_i16(<8 x i16> %a) #0 {403; CHECK-CVT-SD-LABEL: sitofp_i16:404; CHECK-CVT-SD: // %bb.0:405; CHECK-CVT-SD-NEXT: sshll v1.4s, v0.4h, #0406; CHECK-CVT-SD-NEXT: sshll2 v2.4s, v0.8h, #0407; CHECK-CVT-SD-NEXT: scvtf v1.4s, v1.4s408; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v1.4s409; CHECK-CVT-SD-NEXT: scvtf v1.4s, v2.4s410; CHECK-CVT-SD-NEXT: fcvtn2 v0.8h, v1.4s411; CHECK-CVT-SD-NEXT: ret412;413; CHECK-FP16-LABEL: sitofp_i16:414; CHECK-FP16: // %bb.0:415; CHECK-FP16-NEXT: scvtf v0.8h, v0.8h416; CHECK-FP16-NEXT: ret417;418; CHECK-CVT-GI-LABEL: sitofp_i16:419; CHECK-CVT-GI: // %bb.0:420; CHECK-CVT-GI-NEXT: sshll v1.4s, v0.4h, #0421; CHECK-CVT-GI-NEXT: sshll2 v0.4s, v0.8h, #0422; CHECK-CVT-GI-NEXT: scvtf v1.4s, v1.4s423; CHECK-CVT-GI-NEXT: scvtf v2.4s, v0.4s424; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v1.4s425; CHECK-CVT-GI-NEXT: fcvtn2 v0.8h, v2.4s426; CHECK-CVT-GI-NEXT: ret427 %1 = sitofp <8 x i16> %a to <8 x half>428 ret <8 x half> %1429}430 431define <8 x half> @sitofp_i32(<8 x i32> %a) #0 {432; CHECK-LABEL: sitofp_i32:433; CHECK: // %bb.0:434; CHECK-NEXT: scvtf v0.4s, v0.4s435; CHECK-NEXT: scvtf v1.4s, v1.4s436; CHECK-NEXT: fcvtn v0.4h, v0.4s437; CHECK-NEXT: fcvtn2 v0.8h, v1.4s438; CHECK-NEXT: ret439 %1 = sitofp <8 x i32> %a to <8 x half>440 ret <8 x half> %1441}442 443 444define <8 x half> @sitofp_i64(<8 x i64> %a) #0 {445; CHECK-CVT-SD-LABEL: sitofp_i64:446; CHECK-CVT-SD: // %bb.0:447; CHECK-CVT-SD-NEXT: scvtf v0.2d, v0.2d448; CHECK-CVT-SD-NEXT: scvtf v2.2d, v2.2d449; CHECK-CVT-SD-NEXT: scvtf v1.2d, v1.2d450; CHECK-CVT-SD-NEXT: scvtf v3.2d, v3.2d451; CHECK-CVT-SD-NEXT: fcvtn v0.2s, v0.2d452; CHECK-CVT-SD-NEXT: fcvtn v2.2s, v2.2d453; CHECK-CVT-SD-NEXT: fcvtn2 v0.4s, v1.2d454; CHECK-CVT-SD-NEXT: fcvtn2 v2.4s, v3.2d455; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v0.4s456; CHECK-CVT-SD-NEXT: fcvtn2 v0.8h, v2.4s457; CHECK-CVT-SD-NEXT: ret458;459; CHECK-FP16-SD-LABEL: sitofp_i64:460; CHECK-FP16-SD: // %bb.0:461; CHECK-FP16-SD-NEXT: scvtf v0.2d, v0.2d462; CHECK-FP16-SD-NEXT: scvtf v2.2d, v2.2d463; CHECK-FP16-SD-NEXT: scvtf v1.2d, v1.2d464; CHECK-FP16-SD-NEXT: scvtf v3.2d, v3.2d465; CHECK-FP16-SD-NEXT: fcvtn v0.2s, v0.2d466; CHECK-FP16-SD-NEXT: fcvtn v2.2s, v2.2d467; CHECK-FP16-SD-NEXT: fcvtn2 v0.4s, v1.2d468; CHECK-FP16-SD-NEXT: fcvtn2 v2.4s, v3.2d469; CHECK-FP16-SD-NEXT: fcvtn v0.4h, v0.4s470; CHECK-FP16-SD-NEXT: fcvtn2 v0.8h, v2.4s471; CHECK-FP16-SD-NEXT: ret472;473; CHECK-CVT-GI-LABEL: sitofp_i64:474; CHECK-CVT-GI: // %bb.0:475; CHECK-CVT-GI-NEXT: scvtf v0.2d, v0.2d476; CHECK-CVT-GI-NEXT: scvtf v1.2d, v1.2d477; CHECK-CVT-GI-NEXT: scvtf v2.2d, v2.2d478; CHECK-CVT-GI-NEXT: scvtf v3.2d, v3.2d479; CHECK-CVT-GI-NEXT: fcvtn v0.2s, v0.2d480; CHECK-CVT-GI-NEXT: fcvtn v2.2s, v2.2d481; CHECK-CVT-GI-NEXT: fcvtn2 v0.4s, v1.2d482; CHECK-CVT-GI-NEXT: fcvtn2 v2.4s, v3.2d483; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v0.4s484; CHECK-CVT-GI-NEXT: fcvtn2 v0.8h, v2.4s485; CHECK-CVT-GI-NEXT: ret486;487; CHECK-FP16-GI-LABEL: sitofp_i64:488; CHECK-FP16-GI: // %bb.0:489; CHECK-FP16-GI-NEXT: scvtf v0.2d, v0.2d490; CHECK-FP16-GI-NEXT: scvtf v1.2d, v1.2d491; CHECK-FP16-GI-NEXT: scvtf v2.2d, v2.2d492; CHECK-FP16-GI-NEXT: scvtf v3.2d, v3.2d493; CHECK-FP16-GI-NEXT: fcvtn v0.2s, v0.2d494; CHECK-FP16-GI-NEXT: fcvtn v2.2s, v2.2d495; CHECK-FP16-GI-NEXT: fcvtn2 v0.4s, v1.2d496; CHECK-FP16-GI-NEXT: fcvtn2 v2.4s, v3.2d497; CHECK-FP16-GI-NEXT: fcvtn v0.4h, v0.4s498; CHECK-FP16-GI-NEXT: fcvtn2 v0.8h, v2.4s499; CHECK-FP16-GI-NEXT: ret500 %1 = sitofp <8 x i64> %a to <8 x half>501 ret <8 x half> %1502}503 504define <4 x half> @uitofp_v4i8(<4 x i8> %a) #0 {505; CHECK-CVT-SD-LABEL: uitofp_v4i8:506; CHECK-CVT-SD: // %bb.0:507; CHECK-CVT-SD-NEXT: bic v0.4h, #255, lsl #8508; CHECK-CVT-SD-NEXT: ushll v0.4s, v0.4h, #0509; CHECK-CVT-SD-NEXT: ucvtf v0.4s, v0.4s510; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v0.4s511; CHECK-CVT-SD-NEXT: ret512;513; CHECK-FP16-SD-LABEL: uitofp_v4i8:514; CHECK-FP16-SD: // %bb.0:515; CHECK-FP16-SD-NEXT: bic v0.4h, #255, lsl #8516; CHECK-FP16-SD-NEXT: ucvtf v0.4h, v0.4h517; CHECK-FP16-SD-NEXT: ret518;519; CHECK-CVT-GI-LABEL: uitofp_v4i8:520; CHECK-CVT-GI: // %bb.0:521; CHECK-CVT-GI-NEXT: movi v1.2d, #0x0000ff000000ff522; CHECK-CVT-GI-NEXT: ushll v0.4s, v0.4h, #0523; CHECK-CVT-GI-NEXT: and v0.16b, v0.16b, v1.16b524; CHECK-CVT-GI-NEXT: ucvtf v0.4s, v0.4s525; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v0.4s526; CHECK-CVT-GI-NEXT: ret527;528; CHECK-FP16-GI-LABEL: uitofp_v4i8:529; CHECK-FP16-GI: // %bb.0:530; CHECK-FP16-GI-NEXT: movi d1, #0xff00ff00ff00ff531; CHECK-FP16-GI-NEXT: and v0.8b, v0.8b, v1.8b532; CHECK-FP16-GI-NEXT: ucvtf v0.4h, v0.4h533; CHECK-FP16-GI-NEXT: ret534 %1 = uitofp <4 x i8> %a to <4 x half>535 ret <4 x half> %1536}537 538define <8 x half> @uitofp_v8i8(<8 x i8> %a) #0 {539; CHECK-CVT-SD-LABEL: uitofp_v8i8:540; CHECK-CVT-SD: // %bb.0:541; CHECK-CVT-SD-NEXT: ushll v0.8h, v0.8b, #0542; CHECK-CVT-SD-NEXT: ushll v1.4s, v0.4h, #0543; CHECK-CVT-SD-NEXT: ushll2 v2.4s, v0.8h, #0544; CHECK-CVT-SD-NEXT: ucvtf v1.4s, v1.4s545; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v1.4s546; CHECK-CVT-SD-NEXT: ucvtf v1.4s, v2.4s547; CHECK-CVT-SD-NEXT: fcvtn2 v0.8h, v1.4s548; CHECK-CVT-SD-NEXT: ret549;550; CHECK-FP16-LABEL: uitofp_v8i8:551; CHECK-FP16: // %bb.0:552; CHECK-FP16-NEXT: ushll v0.8h, v0.8b, #0553; CHECK-FP16-NEXT: ucvtf v0.8h, v0.8h554; CHECK-FP16-NEXT: ret555;556; CHECK-CVT-GI-LABEL: uitofp_v8i8:557; CHECK-CVT-GI: // %bb.0:558; CHECK-CVT-GI-NEXT: ushll v0.8h, v0.8b, #0559; CHECK-CVT-GI-NEXT: ushll v1.4s, v0.4h, #0560; CHECK-CVT-GI-NEXT: ushll2 v0.4s, v0.8h, #0561; CHECK-CVT-GI-NEXT: ucvtf v1.4s, v1.4s562; CHECK-CVT-GI-NEXT: ucvtf v2.4s, v0.4s563; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v1.4s564; CHECK-CVT-GI-NEXT: fcvtn2 v0.8h, v2.4s565; CHECK-CVT-GI-NEXT: ret566 %1 = uitofp <8 x i8> %a to <8 x half>567 ret <8 x half> %1568}569 570define <16 x half> @uitofp_v16i8(<16 x i8> %a) #0 {571; CHECK-CVT-SD-LABEL: uitofp_v16i8:572; CHECK-CVT-SD: // %bb.0:573; CHECK-CVT-SD-NEXT: ushll2 v1.8h, v0.16b, #0574; CHECK-CVT-SD-NEXT: ushll v0.8h, v0.8b, #0575; CHECK-CVT-SD-NEXT: ushll v2.4s, v1.4h, #0576; CHECK-CVT-SD-NEXT: ushll v3.4s, v0.4h, #0577; CHECK-CVT-SD-NEXT: ushll2 v4.4s, v1.8h, #0578; CHECK-CVT-SD-NEXT: ushll2 v5.4s, v0.8h, #0579; CHECK-CVT-SD-NEXT: ucvtf v2.4s, v2.4s580; CHECK-CVT-SD-NEXT: ucvtf v3.4s, v3.4s581; CHECK-CVT-SD-NEXT: fcvtn v1.4h, v2.4s582; CHECK-CVT-SD-NEXT: ucvtf v2.4s, v4.4s583; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v3.4s584; CHECK-CVT-SD-NEXT: ucvtf v3.4s, v5.4s585; CHECK-CVT-SD-NEXT: fcvtn2 v1.8h, v2.4s586; CHECK-CVT-SD-NEXT: fcvtn2 v0.8h, v3.4s587; CHECK-CVT-SD-NEXT: ret588;589; CHECK-FP16-SD-LABEL: uitofp_v16i8:590; CHECK-FP16-SD: // %bb.0:591; CHECK-FP16-SD-NEXT: ushll2 v1.8h, v0.16b, #0592; CHECK-FP16-SD-NEXT: ushll v0.8h, v0.8b, #0593; CHECK-FP16-SD-NEXT: ucvtf v1.8h, v1.8h594; CHECK-FP16-SD-NEXT: ucvtf v0.8h, v0.8h595; CHECK-FP16-SD-NEXT: ret596;597; CHECK-CVT-GI-LABEL: uitofp_v16i8:598; CHECK-CVT-GI: // %bb.0:599; CHECK-CVT-GI-NEXT: ushll v1.8h, v0.8b, #0600; CHECK-CVT-GI-NEXT: ushll2 v0.8h, v0.16b, #0601; CHECK-CVT-GI-NEXT: ushll v2.4s, v1.4h, #0602; CHECK-CVT-GI-NEXT: ushll v3.4s, v0.4h, #0603; CHECK-CVT-GI-NEXT: ushll2 v1.4s, v1.8h, #0604; CHECK-CVT-GI-NEXT: ushll2 v0.4s, v0.8h, #0605; CHECK-CVT-GI-NEXT: ucvtf v2.4s, v2.4s606; CHECK-CVT-GI-NEXT: ucvtf v3.4s, v3.4s607; CHECK-CVT-GI-NEXT: ucvtf v4.4s, v1.4s608; CHECK-CVT-GI-NEXT: ucvtf v5.4s, v0.4s609; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v2.4s610; CHECK-CVT-GI-NEXT: fcvtn v1.4h, v3.4s611; CHECK-CVT-GI-NEXT: fcvtn2 v0.8h, v4.4s612; CHECK-CVT-GI-NEXT: fcvtn2 v1.8h, v5.4s613; CHECK-CVT-GI-NEXT: ret614;615; CHECK-FP16-GI-LABEL: uitofp_v16i8:616; CHECK-FP16-GI: // %bb.0:617; CHECK-FP16-GI-NEXT: ushll v1.8h, v0.8b, #0618; CHECK-FP16-GI-NEXT: ushll2 v2.8h, v0.16b, #0619; CHECK-FP16-GI-NEXT: ucvtf v0.8h, v1.8h620; CHECK-FP16-GI-NEXT: ucvtf v1.8h, v2.8h621; CHECK-FP16-GI-NEXT: ret622 %1 = uitofp <16 x i8> %a to <16 x half>623 ret <16 x half> %1624}625 626 627define <8 x half> @uitofp_i16(<8 x i16> %a) #0 {628; CHECK-CVT-SD-LABEL: uitofp_i16:629; CHECK-CVT-SD: // %bb.0:630; CHECK-CVT-SD-NEXT: ushll v1.4s, v0.4h, #0631; CHECK-CVT-SD-NEXT: ushll2 v2.4s, v0.8h, #0632; CHECK-CVT-SD-NEXT: ucvtf v1.4s, v1.4s633; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v1.4s634; CHECK-CVT-SD-NEXT: ucvtf v1.4s, v2.4s635; CHECK-CVT-SD-NEXT: fcvtn2 v0.8h, v1.4s636; CHECK-CVT-SD-NEXT: ret637;638; CHECK-FP16-LABEL: uitofp_i16:639; CHECK-FP16: // %bb.0:640; CHECK-FP16-NEXT: ucvtf v0.8h, v0.8h641; CHECK-FP16-NEXT: ret642;643; CHECK-CVT-GI-LABEL: uitofp_i16:644; CHECK-CVT-GI: // %bb.0:645; CHECK-CVT-GI-NEXT: ushll v1.4s, v0.4h, #0646; CHECK-CVT-GI-NEXT: ushll2 v0.4s, v0.8h, #0647; CHECK-CVT-GI-NEXT: ucvtf v1.4s, v1.4s648; CHECK-CVT-GI-NEXT: ucvtf v2.4s, v0.4s649; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v1.4s650; CHECK-CVT-GI-NEXT: fcvtn2 v0.8h, v2.4s651; CHECK-CVT-GI-NEXT: ret652 %1 = uitofp <8 x i16> %a to <8 x half>653 ret <8 x half> %1654}655 656 657define <8 x half> @uitofp_i32(<8 x i32> %a) #0 {658; CHECK-LABEL: uitofp_i32:659; CHECK: // %bb.0:660; CHECK-NEXT: ucvtf v0.4s, v0.4s661; CHECK-NEXT: ucvtf v1.4s, v1.4s662; CHECK-NEXT: fcvtn v0.4h, v0.4s663; CHECK-NEXT: fcvtn2 v0.8h, v1.4s664; CHECK-NEXT: ret665 %1 = uitofp <8 x i32> %a to <8 x half>666 ret <8 x half> %1667}668 669 670define <8 x half> @uitofp_i64(<8 x i64> %a) #0 {671; CHECK-CVT-SD-LABEL: uitofp_i64:672; CHECK-CVT-SD: // %bb.0:673; CHECK-CVT-SD-NEXT: ucvtf v0.2d, v0.2d674; CHECK-CVT-SD-NEXT: ucvtf v2.2d, v2.2d675; CHECK-CVT-SD-NEXT: ucvtf v1.2d, v1.2d676; CHECK-CVT-SD-NEXT: ucvtf v3.2d, v3.2d677; CHECK-CVT-SD-NEXT: fcvtn v0.2s, v0.2d678; CHECK-CVT-SD-NEXT: fcvtn v2.2s, v2.2d679; CHECK-CVT-SD-NEXT: fcvtn2 v0.4s, v1.2d680; CHECK-CVT-SD-NEXT: fcvtn2 v2.4s, v3.2d681; CHECK-CVT-SD-NEXT: fcvtn v0.4h, v0.4s682; CHECK-CVT-SD-NEXT: fcvtn2 v0.8h, v2.4s683; CHECK-CVT-SD-NEXT: ret684;685; CHECK-FP16-SD-LABEL: uitofp_i64:686; CHECK-FP16-SD: // %bb.0:687; CHECK-FP16-SD-NEXT: ucvtf v0.2d, v0.2d688; CHECK-FP16-SD-NEXT: ucvtf v2.2d, v2.2d689; CHECK-FP16-SD-NEXT: ucvtf v1.2d, v1.2d690; CHECK-FP16-SD-NEXT: ucvtf v3.2d, v3.2d691; CHECK-FP16-SD-NEXT: fcvtn v0.2s, v0.2d692; CHECK-FP16-SD-NEXT: fcvtn v2.2s, v2.2d693; CHECK-FP16-SD-NEXT: fcvtn2 v0.4s, v1.2d694; CHECK-FP16-SD-NEXT: fcvtn2 v2.4s, v3.2d695; CHECK-FP16-SD-NEXT: fcvtn v0.4h, v0.4s696; CHECK-FP16-SD-NEXT: fcvtn2 v0.8h, v2.4s697; CHECK-FP16-SD-NEXT: ret698;699; CHECK-CVT-GI-LABEL: uitofp_i64:700; CHECK-CVT-GI: // %bb.0:701; CHECK-CVT-GI-NEXT: ucvtf v0.2d, v0.2d702; CHECK-CVT-GI-NEXT: ucvtf v1.2d, v1.2d703; CHECK-CVT-GI-NEXT: ucvtf v2.2d, v2.2d704; CHECK-CVT-GI-NEXT: ucvtf v3.2d, v3.2d705; CHECK-CVT-GI-NEXT: fcvtn v0.2s, v0.2d706; CHECK-CVT-GI-NEXT: fcvtn v2.2s, v2.2d707; CHECK-CVT-GI-NEXT: fcvtn2 v0.4s, v1.2d708; CHECK-CVT-GI-NEXT: fcvtn2 v2.4s, v3.2d709; CHECK-CVT-GI-NEXT: fcvtn v0.4h, v0.4s710; CHECK-CVT-GI-NEXT: fcvtn2 v0.8h, v2.4s711; CHECK-CVT-GI-NEXT: ret712;713; CHECK-FP16-GI-LABEL: uitofp_i64:714; CHECK-FP16-GI: // %bb.0:715; CHECK-FP16-GI-NEXT: ucvtf v0.2d, v0.2d716; CHECK-FP16-GI-NEXT: ucvtf v1.2d, v1.2d717; CHECK-FP16-GI-NEXT: ucvtf v2.2d, v2.2d718; CHECK-FP16-GI-NEXT: ucvtf v3.2d, v3.2d719; CHECK-FP16-GI-NEXT: fcvtn v0.2s, v0.2d720; CHECK-FP16-GI-NEXT: fcvtn v2.2s, v2.2d721; CHECK-FP16-GI-NEXT: fcvtn2 v0.4s, v1.2d722; CHECK-FP16-GI-NEXT: fcvtn2 v2.4s, v3.2d723; CHECK-FP16-GI-NEXT: fcvtn v0.4h, v0.4s724; CHECK-FP16-GI-NEXT: fcvtn2 v0.8h, v2.4s725; CHECK-FP16-GI-NEXT: ret726 %1 = uitofp <8 x i64> %a to <8 x half>727 ret <8 x half> %1728}729 730define void @test_insert_at_zero(half %a, ptr %b) #0 {731; CHECK-LABEL: test_insert_at_zero:732; CHECK: // %bb.0:733; CHECK-NEXT: // kill: def $h0 killed $h0 def $q0734; CHECK-NEXT: str q0, [x0]735; CHECK-NEXT: ret736 %1 = insertelement <8 x half> undef, half %a, i64 0737 store <8 x half> %1, ptr %b, align 4738 ret void739}740 741define <8 x i8> @fptosi_i8(<8 x half> %a) #0 {742; CHECK-CVT-SD-LABEL: fptosi_i8:743; CHECK-CVT-SD: // %bb.0:744; CHECK-CVT-SD-NEXT: fcvtl2 v1.4s, v0.8h745; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h746; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s747; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s748; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v1.8h749; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h750; CHECK-CVT-SD-NEXT: ret751;752; CHECK-FP16-LABEL: fptosi_i8:753; CHECK-FP16: // %bb.0:754; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h755; CHECK-FP16-NEXT: xtn v0.8b, v0.8h756; CHECK-FP16-NEXT: ret757;758; CHECK-CVT-GI-LABEL: fptosi_i8:759; CHECK-CVT-GI: // %bb.0:760; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v0.4h761; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h762; CHECK-CVT-GI-NEXT: fcvtzs v1.4s, v1.4s763; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s764; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h765; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h766; CHECK-CVT-GI-NEXT: ret767 %1 = fptosi<8 x half> %a to <8 x i8>768 ret <8 x i8> %1769}770 771define <8 x i16> @fptosi_i16(<8 x half> %a) #0 {772; CHECK-CVT-SD-LABEL: fptosi_i16:773; CHECK-CVT-SD: // %bb.0:774; CHECK-CVT-SD-NEXT: fcvtl2 v1.4s, v0.8h775; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h776; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s777; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s778; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v1.8h779; CHECK-CVT-SD-NEXT: ret780;781; CHECK-FP16-LABEL: fptosi_i16:782; CHECK-FP16: // %bb.0:783; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h784; CHECK-FP16-NEXT: ret785;786; CHECK-CVT-GI-LABEL: fptosi_i16:787; CHECK-CVT-GI: // %bb.0:788; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v0.4h789; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h790; CHECK-CVT-GI-NEXT: fcvtzs v1.4s, v1.4s791; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s792; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h793; CHECK-CVT-GI-NEXT: ret794 %1 = fptosi<8 x half> %a to <8 x i16>795 ret <8 x i16> %1796}797 798define <8 x i8> @fptoui_i8(<8 x half> %a) #0 {799; CHECK-CVT-SD-LABEL: fptoui_i8:800; CHECK-CVT-SD: // %bb.0:801; CHECK-CVT-SD-NEXT: fcvtl2 v1.4s, v0.8h802; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h803; CHECK-CVT-SD-NEXT: fcvtzu v1.4s, v1.4s804; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s805; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v1.8h806; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h807; CHECK-CVT-SD-NEXT: ret808;809; CHECK-FP16-LABEL: fptoui_i8:810; CHECK-FP16: // %bb.0:811; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h812; CHECK-FP16-NEXT: xtn v0.8b, v0.8h813; CHECK-FP16-NEXT: ret814;815; CHECK-CVT-GI-LABEL: fptoui_i8:816; CHECK-CVT-GI: // %bb.0:817; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v0.4h818; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h819; CHECK-CVT-GI-NEXT: fcvtzu v1.4s, v1.4s820; CHECK-CVT-GI-NEXT: fcvtzu v0.4s, v0.4s821; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h822; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h823; CHECK-CVT-GI-NEXT: ret824 %1 = fptoui<8 x half> %a to <8 x i8>825 ret <8 x i8> %1826}827 828define <8 x i16> @fptoui_i16(<8 x half> %a) #0 {829; CHECK-CVT-SD-LABEL: fptoui_i16:830; CHECK-CVT-SD: // %bb.0:831; CHECK-CVT-SD-NEXT: fcvtl2 v1.4s, v0.8h832; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h833; CHECK-CVT-SD-NEXT: fcvtzu v1.4s, v1.4s834; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s835; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v1.8h836; CHECK-CVT-SD-NEXT: ret837;838; CHECK-FP16-LABEL: fptoui_i16:839; CHECK-FP16: // %bb.0:840; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h841; CHECK-FP16-NEXT: ret842;843; CHECK-CVT-GI-LABEL: fptoui_i16:844; CHECK-CVT-GI: // %bb.0:845; CHECK-CVT-GI-NEXT: fcvtl v1.4s, v0.4h846; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h847; CHECK-CVT-GI-NEXT: fcvtzu v1.4s, v1.4s848; CHECK-CVT-GI-NEXT: fcvtzu v0.4s, v0.4s849; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h850; CHECK-CVT-GI-NEXT: ret851 %1 = fptoui<8 x half> %a to <8 x i16>852 ret <8 x i16> %1853}854 855define <8 x i1> @test_fcmp_une(<8 x half> %a, <8 x half> %b) #0 {856; CHECK-CVT-SD-LABEL: test_fcmp_une:857; CHECK-CVT-SD: // %bb.0:858; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v1.8h859; CHECK-CVT-SD-NEXT: fcvtl2 v3.4s, v0.8h860; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h861; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h862; CHECK-CVT-SD-NEXT: fcmeq v2.4s, v3.4s, v2.4s863; CHECK-CVT-SD-NEXT: fcmeq v0.4s, v0.4s, v1.4s864; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v2.8h865; CHECK-CVT-SD-NEXT: mvn v0.16b, v0.16b866; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h867; CHECK-CVT-SD-NEXT: ret868;869; CHECK-FP16-LABEL: test_fcmp_une:870; CHECK-FP16: // %bb.0:871; CHECK-FP16-NEXT: fcmeq v0.8h, v0.8h, v1.8h872; CHECK-FP16-NEXT: mvn v0.16b, v0.16b873; CHECK-FP16-NEXT: xtn v0.8b, v0.8h874; CHECK-FP16-NEXT: ret875;876; CHECK-CVT-GI-LABEL: test_fcmp_une:877; CHECK-CVT-GI: // %bb.0:878; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h879; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h880; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h881; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h882; CHECK-CVT-GI-NEXT: fcmeq v2.4s, v2.4s, v3.4s883; CHECK-CVT-GI-NEXT: fcmeq v0.4s, v0.4s, v1.4s884; CHECK-CVT-GI-NEXT: mvn v1.16b, v2.16b885; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b886; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h887; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h888; CHECK-CVT-GI-NEXT: ret889 %1 = fcmp une <8 x half> %a, %b890 ret <8 x i1> %1891}892 893define <8 x i1> @test_fcmp_ueq(<8 x half> %a, <8 x half> %b) #0 {894; CHECK-CVT-SD-LABEL: test_fcmp_ueq:895; CHECK-CVT-SD: // %bb.0:896; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v1.8h897; CHECK-CVT-SD-NEXT: fcvtl2 v3.4s, v0.8h898; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h899; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h900; CHECK-CVT-SD-NEXT: fcmgt v4.4s, v3.4s, v2.4s901; CHECK-CVT-SD-NEXT: fcmgt v2.4s, v2.4s, v3.4s902; CHECK-CVT-SD-NEXT: fcmgt v3.4s, v0.4s, v1.4s903; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s904; CHECK-CVT-SD-NEXT: orr v1.16b, v2.16b, v4.16b905; CHECK-CVT-SD-NEXT: orr v0.16b, v0.16b, v3.16b906; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v1.8h907; CHECK-CVT-SD-NEXT: mvn v0.16b, v0.16b908; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h909; CHECK-CVT-SD-NEXT: ret910;911; CHECK-FP16-LABEL: test_fcmp_ueq:912; CHECK-FP16: // %bb.0:913; CHECK-FP16-NEXT: fcmgt v2.8h, v0.8h, v1.8h914; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h915; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b916; CHECK-FP16-NEXT: mvn v0.16b, v0.16b917; CHECK-FP16-NEXT: xtn v0.8b, v0.8h918; CHECK-FP16-NEXT: ret919;920; CHECK-CVT-GI-LABEL: test_fcmp_ueq:921; CHECK-CVT-GI: // %bb.0:922; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h923; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h924; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h925; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h926; CHECK-CVT-GI-NEXT: fcmgt v4.4s, v2.4s, v3.4s927; CHECK-CVT-GI-NEXT: fcmgt v2.4s, v3.4s, v2.4s928; CHECK-CVT-GI-NEXT: fcmgt v3.4s, v0.4s, v1.4s929; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s930; CHECK-CVT-GI-NEXT: orr v1.16b, v2.16b, v4.16b931; CHECK-CVT-GI-NEXT: orr v0.16b, v0.16b, v3.16b932; CHECK-CVT-GI-NEXT: mvn v1.16b, v1.16b933; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b934; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h935; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h936; CHECK-CVT-GI-NEXT: ret937 %1 = fcmp ueq <8 x half> %a, %b938 ret <8 x i1> %1939}940 941define <8 x i1> @test_fcmp_ugt(<8 x half> %a, <8 x half> %b) #0 {942; CHECK-CVT-SD-LABEL: test_fcmp_ugt:943; CHECK-CVT-SD: // %bb.0:944; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v0.8h945; CHECK-CVT-SD-NEXT: fcvtl2 v3.4s, v1.8h946; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h947; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h948; CHECK-CVT-SD-NEXT: fcmge v2.4s, v3.4s, v2.4s949; CHECK-CVT-SD-NEXT: fcmge v0.4s, v1.4s, v0.4s950; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v2.8h951; CHECK-CVT-SD-NEXT: mvn v0.16b, v0.16b952; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h953; CHECK-CVT-SD-NEXT: ret954;955; CHECK-FP16-LABEL: test_fcmp_ugt:956; CHECK-FP16: // %bb.0:957; CHECK-FP16-NEXT: fcmge v0.8h, v1.8h, v0.8h958; CHECK-FP16-NEXT: mvn v0.16b, v0.16b959; CHECK-FP16-NEXT: xtn v0.8b, v0.8h960; CHECK-FP16-NEXT: ret961;962; CHECK-CVT-GI-LABEL: test_fcmp_ugt:963; CHECK-CVT-GI: // %bb.0:964; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h965; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h966; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h967; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h968; CHECK-CVT-GI-NEXT: fcmge v2.4s, v3.4s, v2.4s969; CHECK-CVT-GI-NEXT: fcmge v0.4s, v1.4s, v0.4s970; CHECK-CVT-GI-NEXT: mvn v1.16b, v2.16b971; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b972; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h973; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h974; CHECK-CVT-GI-NEXT: ret975 %1 = fcmp ugt <8 x half> %a, %b976 ret <8 x i1> %1977}978 979define <8 x i1> @test_fcmp_uge(<8 x half> %a, <8 x half> %b) #0 {980; CHECK-CVT-SD-LABEL: test_fcmp_uge:981; CHECK-CVT-SD: // %bb.0:982; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v0.8h983; CHECK-CVT-SD-NEXT: fcvtl2 v3.4s, v1.8h984; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h985; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h986; CHECK-CVT-SD-NEXT: fcmgt v2.4s, v3.4s, v2.4s987; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s988; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v2.8h989; CHECK-CVT-SD-NEXT: mvn v0.16b, v0.16b990; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h991; CHECK-CVT-SD-NEXT: ret992;993; CHECK-FP16-LABEL: test_fcmp_uge:994; CHECK-FP16: // %bb.0:995; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h996; CHECK-FP16-NEXT: mvn v0.16b, v0.16b997; CHECK-FP16-NEXT: xtn v0.8b, v0.8h998; CHECK-FP16-NEXT: ret999;1000; CHECK-CVT-GI-LABEL: test_fcmp_uge:1001; CHECK-CVT-GI: // %bb.0:1002; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h1003; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h1004; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h1005; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h1006; CHECK-CVT-GI-NEXT: fcmgt v2.4s, v3.4s, v2.4s1007; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s1008; CHECK-CVT-GI-NEXT: mvn v1.16b, v2.16b1009; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b1010; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h1011; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h1012; CHECK-CVT-GI-NEXT: ret1013 %1 = fcmp uge <8 x half> %a, %b1014 ret <8 x i1> %11015}1016 1017define <8 x i1> @test_fcmp_ult(<8 x half> %a, <8 x half> %b) #0 {1018; CHECK-CVT-SD-LABEL: test_fcmp_ult:1019; CHECK-CVT-SD: // %bb.0:1020; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v1.8h1021; CHECK-CVT-SD-NEXT: fcvtl2 v3.4s, v0.8h1022; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h1023; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h1024; CHECK-CVT-SD-NEXT: fcmge v2.4s, v3.4s, v2.4s1025; CHECK-CVT-SD-NEXT: fcmge v0.4s, v0.4s, v1.4s1026; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v2.8h1027; CHECK-CVT-SD-NEXT: mvn v0.16b, v0.16b1028; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h1029; CHECK-CVT-SD-NEXT: ret1030;1031; CHECK-FP16-LABEL: test_fcmp_ult:1032; CHECK-FP16: // %bb.0:1033; CHECK-FP16-NEXT: fcmge v0.8h, v0.8h, v1.8h1034; CHECK-FP16-NEXT: mvn v0.16b, v0.16b1035; CHECK-FP16-NEXT: xtn v0.8b, v0.8h1036; CHECK-FP16-NEXT: ret1037;1038; CHECK-CVT-GI-LABEL: test_fcmp_ult:1039; CHECK-CVT-GI: // %bb.0:1040; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h1041; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h1042; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h1043; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h1044; CHECK-CVT-GI-NEXT: fcmge v2.4s, v2.4s, v3.4s1045; CHECK-CVT-GI-NEXT: fcmge v0.4s, v0.4s, v1.4s1046; CHECK-CVT-GI-NEXT: mvn v1.16b, v2.16b1047; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b1048; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h1049; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h1050; CHECK-CVT-GI-NEXT: ret1051 %1 = fcmp ult <8 x half> %a, %b1052 ret <8 x i1> %11053}1054 1055define <8 x i1> @test_fcmp_ule(<8 x half> %a, <8 x half> %b) #0 {1056; CHECK-CVT-SD-LABEL: test_fcmp_ule:1057; CHECK-CVT-SD: // %bb.0:1058; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v1.8h1059; CHECK-CVT-SD-NEXT: fcvtl2 v3.4s, v0.8h1060; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h1061; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h1062; CHECK-CVT-SD-NEXT: fcmgt v2.4s, v3.4s, v2.4s1063; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v0.4s, v1.4s1064; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v2.8h1065; CHECK-CVT-SD-NEXT: mvn v0.16b, v0.16b1066; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h1067; CHECK-CVT-SD-NEXT: ret1068;1069; CHECK-FP16-LABEL: test_fcmp_ule:1070; CHECK-FP16: // %bb.0:1071; CHECK-FP16-NEXT: fcmgt v0.8h, v0.8h, v1.8h1072; CHECK-FP16-NEXT: mvn v0.16b, v0.16b1073; CHECK-FP16-NEXT: xtn v0.8b, v0.8h1074; CHECK-FP16-NEXT: ret1075;1076; CHECK-CVT-GI-LABEL: test_fcmp_ule:1077; CHECK-CVT-GI: // %bb.0:1078; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h1079; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h1080; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h1081; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h1082; CHECK-CVT-GI-NEXT: fcmgt v2.4s, v2.4s, v3.4s1083; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v0.4s, v1.4s1084; CHECK-CVT-GI-NEXT: mvn v1.16b, v2.16b1085; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b1086; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h1087; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h1088; CHECK-CVT-GI-NEXT: ret1089 %1 = fcmp ule <8 x half> %a, %b1090 ret <8 x i1> %11091}1092 1093define <8 x i1> @test_fcmp_uno(<8 x half> %a, <8 x half> %b) #0 {1094; CHECK-CVT-SD-LABEL: test_fcmp_uno:1095; CHECK-CVT-SD: // %bb.0:1096; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v1.8h1097; CHECK-CVT-SD-NEXT: fcvtl2 v3.4s, v0.8h1098; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h1099; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h1100; CHECK-CVT-SD-NEXT: fcmge v4.4s, v3.4s, v2.4s1101; CHECK-CVT-SD-NEXT: fcmgt v2.4s, v2.4s, v3.4s1102; CHECK-CVT-SD-NEXT: fcmge v3.4s, v0.4s, v1.4s1103; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s1104; CHECK-CVT-SD-NEXT: orr v1.16b, v2.16b, v4.16b1105; CHECK-CVT-SD-NEXT: orr v0.16b, v0.16b, v3.16b1106; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v1.8h1107; CHECK-CVT-SD-NEXT: mvn v0.16b, v0.16b1108; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h1109; CHECK-CVT-SD-NEXT: ret1110;1111; CHECK-FP16-LABEL: test_fcmp_uno:1112; CHECK-FP16: // %bb.0:1113; CHECK-FP16-NEXT: fcmge v2.8h, v0.8h, v1.8h1114; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h1115; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b1116; CHECK-FP16-NEXT: mvn v0.16b, v0.16b1117; CHECK-FP16-NEXT: xtn v0.8b, v0.8h1118; CHECK-FP16-NEXT: ret1119;1120; CHECK-CVT-GI-LABEL: test_fcmp_uno:1121; CHECK-CVT-GI: // %bb.0:1122; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h1123; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h1124; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h1125; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h1126; CHECK-CVT-GI-NEXT: fcmge v4.4s, v2.4s, v3.4s1127; CHECK-CVT-GI-NEXT: fcmgt v2.4s, v3.4s, v2.4s1128; CHECK-CVT-GI-NEXT: fcmge v3.4s, v0.4s, v1.4s1129; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s1130; CHECK-CVT-GI-NEXT: orr v1.16b, v2.16b, v4.16b1131; CHECK-CVT-GI-NEXT: orr v0.16b, v0.16b, v3.16b1132; CHECK-CVT-GI-NEXT: mvn v1.16b, v1.16b1133; CHECK-CVT-GI-NEXT: mvn v0.16b, v0.16b1134; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h1135; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h1136; CHECK-CVT-GI-NEXT: ret1137 %1 = fcmp uno <8 x half> %a, %b1138 ret <8 x i1> %11139}1140 1141define <8 x i1> @test_fcmp_one(<8 x half> %a, <8 x half> %b) #0 {1142; CHECK-CVT-SD-LABEL: test_fcmp_one:1143; CHECK-CVT-SD: // %bb.0:1144; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v1.8h1145; CHECK-CVT-SD-NEXT: fcvtl2 v3.4s, v0.8h1146; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h1147; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h1148; CHECK-CVT-SD-NEXT: fcmgt v4.4s, v3.4s, v2.4s1149; CHECK-CVT-SD-NEXT: fcmgt v2.4s, v2.4s, v3.4s1150; CHECK-CVT-SD-NEXT: fcmgt v3.4s, v0.4s, v1.4s1151; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s1152; CHECK-CVT-SD-NEXT: orr v1.16b, v2.16b, v4.16b1153; CHECK-CVT-SD-NEXT: orr v0.16b, v0.16b, v3.16b1154; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v1.8h1155; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h1156; CHECK-CVT-SD-NEXT: ret1157;1158; CHECK-FP16-LABEL: test_fcmp_one:1159; CHECK-FP16: // %bb.0:1160; CHECK-FP16-NEXT: fcmgt v2.8h, v0.8h, v1.8h1161; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h1162; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b1163; CHECK-FP16-NEXT: xtn v0.8b, v0.8h1164; CHECK-FP16-NEXT: ret1165;1166; CHECK-CVT-GI-LABEL: test_fcmp_one:1167; CHECK-CVT-GI: // %bb.0:1168; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h1169; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h1170; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h1171; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h1172; CHECK-CVT-GI-NEXT: fcmgt v4.4s, v2.4s, v3.4s1173; CHECK-CVT-GI-NEXT: fcmgt v2.4s, v3.4s, v2.4s1174; CHECK-CVT-GI-NEXT: fcmgt v3.4s, v0.4s, v1.4s1175; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s1176; CHECK-CVT-GI-NEXT: orr v1.16b, v2.16b, v4.16b1177; CHECK-CVT-GI-NEXT: orr v0.16b, v0.16b, v3.16b1178; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h1179; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h1180; CHECK-CVT-GI-NEXT: ret1181 %1 = fcmp one <8 x half> %a, %b1182 ret <8 x i1> %11183}1184 1185define <8 x i1> @test_fcmp_oeq(<8 x half> %a, <8 x half> %b) #0 {1186; CHECK-CVT-SD-LABEL: test_fcmp_oeq:1187; CHECK-CVT-SD: // %bb.0:1188; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v1.8h1189; CHECK-CVT-SD-NEXT: fcvtl2 v3.4s, v0.8h1190; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h1191; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h1192; CHECK-CVT-SD-NEXT: fcmeq v2.4s, v3.4s, v2.4s1193; CHECK-CVT-SD-NEXT: fcmeq v0.4s, v0.4s, v1.4s1194; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v2.8h1195; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h1196; CHECK-CVT-SD-NEXT: ret1197;1198; CHECK-FP16-LABEL: test_fcmp_oeq:1199; CHECK-FP16: // %bb.0:1200; CHECK-FP16-NEXT: fcmeq v0.8h, v0.8h, v1.8h1201; CHECK-FP16-NEXT: xtn v0.8b, v0.8h1202; CHECK-FP16-NEXT: ret1203;1204; CHECK-CVT-GI-LABEL: test_fcmp_oeq:1205; CHECK-CVT-GI: // %bb.0:1206; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h1207; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h1208; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h1209; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h1210; CHECK-CVT-GI-NEXT: fcmeq v2.4s, v2.4s, v3.4s1211; CHECK-CVT-GI-NEXT: fcmeq v0.4s, v0.4s, v1.4s1212; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h1213; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h1214; CHECK-CVT-GI-NEXT: ret1215 %1 = fcmp oeq <8 x half> %a, %b1216 ret <8 x i1> %11217}1218 1219define <8 x i1> @test_fcmp_ogt(<8 x half> %a, <8 x half> %b) #0 {1220; CHECK-CVT-SD-LABEL: test_fcmp_ogt:1221; CHECK-CVT-SD: // %bb.0:1222; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v1.8h1223; CHECK-CVT-SD-NEXT: fcvtl2 v3.4s, v0.8h1224; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h1225; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h1226; CHECK-CVT-SD-NEXT: fcmgt v2.4s, v3.4s, v2.4s1227; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v0.4s, v1.4s1228; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v2.8h1229; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h1230; CHECK-CVT-SD-NEXT: ret1231;1232; CHECK-FP16-LABEL: test_fcmp_ogt:1233; CHECK-FP16: // %bb.0:1234; CHECK-FP16-NEXT: fcmgt v0.8h, v0.8h, v1.8h1235; CHECK-FP16-NEXT: xtn v0.8b, v0.8h1236; CHECK-FP16-NEXT: ret1237;1238; CHECK-CVT-GI-LABEL: test_fcmp_ogt:1239; CHECK-CVT-GI: // %bb.0:1240; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h1241; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h1242; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h1243; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h1244; CHECK-CVT-GI-NEXT: fcmgt v2.4s, v2.4s, v3.4s1245; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v0.4s, v1.4s1246; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h1247; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h1248; CHECK-CVT-GI-NEXT: ret1249 %1 = fcmp ogt <8 x half> %a, %b1250 ret <8 x i1> %11251}1252 1253define <8 x i1> @test_fcmp_oge(<8 x half> %a, <8 x half> %b) #0 {1254; CHECK-CVT-SD-LABEL: test_fcmp_oge:1255; CHECK-CVT-SD: // %bb.0:1256; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v1.8h1257; CHECK-CVT-SD-NEXT: fcvtl2 v3.4s, v0.8h1258; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h1259; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h1260; CHECK-CVT-SD-NEXT: fcmge v2.4s, v3.4s, v2.4s1261; CHECK-CVT-SD-NEXT: fcmge v0.4s, v0.4s, v1.4s1262; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v2.8h1263; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h1264; CHECK-CVT-SD-NEXT: ret1265;1266; CHECK-FP16-LABEL: test_fcmp_oge:1267; CHECK-FP16: // %bb.0:1268; CHECK-FP16-NEXT: fcmge v0.8h, v0.8h, v1.8h1269; CHECK-FP16-NEXT: xtn v0.8b, v0.8h1270; CHECK-FP16-NEXT: ret1271;1272; CHECK-CVT-GI-LABEL: test_fcmp_oge:1273; CHECK-CVT-GI: // %bb.0:1274; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h1275; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h1276; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h1277; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h1278; CHECK-CVT-GI-NEXT: fcmge v2.4s, v2.4s, v3.4s1279; CHECK-CVT-GI-NEXT: fcmge v0.4s, v0.4s, v1.4s1280; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h1281; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h1282; CHECK-CVT-GI-NEXT: ret1283 %1 = fcmp oge <8 x half> %a, %b1284 ret <8 x i1> %11285}1286 1287define <8 x i1> @test_fcmp_olt(<8 x half> %a, <8 x half> %b) #0 {1288; CHECK-CVT-SD-LABEL: test_fcmp_olt:1289; CHECK-CVT-SD: // %bb.0:1290; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v0.8h1291; CHECK-CVT-SD-NEXT: fcvtl2 v3.4s, v1.8h1292; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h1293; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h1294; CHECK-CVT-SD-NEXT: fcmgt v2.4s, v3.4s, v2.4s1295; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s1296; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v2.8h1297; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h1298; CHECK-CVT-SD-NEXT: ret1299;1300; CHECK-FP16-LABEL: test_fcmp_olt:1301; CHECK-FP16: // %bb.0:1302; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h1303; CHECK-FP16-NEXT: xtn v0.8b, v0.8h1304; CHECK-FP16-NEXT: ret1305;1306; CHECK-CVT-GI-LABEL: test_fcmp_olt:1307; CHECK-CVT-GI: // %bb.0:1308; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h1309; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h1310; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h1311; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h1312; CHECK-CVT-GI-NEXT: fcmgt v2.4s, v3.4s, v2.4s1313; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s1314; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h1315; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h1316; CHECK-CVT-GI-NEXT: ret1317 %1 = fcmp olt <8 x half> %a, %b1318 ret <8 x i1> %11319}1320 1321define <8 x i1> @test_fcmp_ole(<8 x half> %a, <8 x half> %b) #0 {1322; CHECK-CVT-SD-LABEL: test_fcmp_ole:1323; CHECK-CVT-SD: // %bb.0:1324; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v0.8h1325; CHECK-CVT-SD-NEXT: fcvtl2 v3.4s, v1.8h1326; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h1327; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h1328; CHECK-CVT-SD-NEXT: fcmge v2.4s, v3.4s, v2.4s1329; CHECK-CVT-SD-NEXT: fcmge v0.4s, v1.4s, v0.4s1330; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v2.8h1331; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h1332; CHECK-CVT-SD-NEXT: ret1333;1334; CHECK-FP16-LABEL: test_fcmp_ole:1335; CHECK-FP16: // %bb.0:1336; CHECK-FP16-NEXT: fcmge v0.8h, v1.8h, v0.8h1337; CHECK-FP16-NEXT: xtn v0.8b, v0.8h1338; CHECK-FP16-NEXT: ret1339;1340; CHECK-CVT-GI-LABEL: test_fcmp_ole:1341; CHECK-CVT-GI: // %bb.0:1342; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h1343; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h1344; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h1345; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h1346; CHECK-CVT-GI-NEXT: fcmge v2.4s, v3.4s, v2.4s1347; CHECK-CVT-GI-NEXT: fcmge v0.4s, v1.4s, v0.4s1348; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v2.8h, v0.8h1349; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h1350; CHECK-CVT-GI-NEXT: ret1351 %1 = fcmp ole <8 x half> %a, %b1352 ret <8 x i1> %11353}1354 1355define <8 x i1> @test_fcmp_ord(<8 x half> %a, <8 x half> %b) #0 {1356; CHECK-CVT-SD-LABEL: test_fcmp_ord:1357; CHECK-CVT-SD: // %bb.0:1358; CHECK-CVT-SD-NEXT: fcvtl2 v2.4s, v1.8h1359; CHECK-CVT-SD-NEXT: fcvtl2 v3.4s, v0.8h1360; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v1.4h1361; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h1362; CHECK-CVT-SD-NEXT: fcmge v4.4s, v3.4s, v2.4s1363; CHECK-CVT-SD-NEXT: fcmgt v2.4s, v2.4s, v3.4s1364; CHECK-CVT-SD-NEXT: fcmge v3.4s, v0.4s, v1.4s1365; CHECK-CVT-SD-NEXT: fcmgt v0.4s, v1.4s, v0.4s1366; CHECK-CVT-SD-NEXT: orr v1.16b, v2.16b, v4.16b1367; CHECK-CVT-SD-NEXT: orr v0.16b, v0.16b, v3.16b1368; CHECK-CVT-SD-NEXT: uzp1 v0.8h, v0.8h, v1.8h1369; CHECK-CVT-SD-NEXT: xtn v0.8b, v0.8h1370; CHECK-CVT-SD-NEXT: ret1371;1372; CHECK-FP16-LABEL: test_fcmp_ord:1373; CHECK-FP16: // %bb.0:1374; CHECK-FP16-NEXT: fcmge v2.8h, v0.8h, v1.8h1375; CHECK-FP16-NEXT: fcmgt v0.8h, v1.8h, v0.8h1376; CHECK-FP16-NEXT: orr v0.16b, v0.16b, v2.16b1377; CHECK-FP16-NEXT: xtn v0.8b, v0.8h1378; CHECK-FP16-NEXT: ret1379;1380; CHECK-CVT-GI-LABEL: test_fcmp_ord:1381; CHECK-CVT-GI: // %bb.0:1382; CHECK-CVT-GI-NEXT: fcvtl v2.4s, v0.4h1383; CHECK-CVT-GI-NEXT: fcvtl v3.4s, v1.4h1384; CHECK-CVT-GI-NEXT: fcvtl2 v0.4s, v0.8h1385; CHECK-CVT-GI-NEXT: fcvtl2 v1.4s, v1.8h1386; CHECK-CVT-GI-NEXT: fcmge v4.4s, v2.4s, v3.4s1387; CHECK-CVT-GI-NEXT: fcmgt v2.4s, v3.4s, v2.4s1388; CHECK-CVT-GI-NEXT: fcmge v3.4s, v0.4s, v1.4s1389; CHECK-CVT-GI-NEXT: fcmgt v0.4s, v1.4s, v0.4s1390; CHECK-CVT-GI-NEXT: orr v1.16b, v2.16b, v4.16b1391; CHECK-CVT-GI-NEXT: orr v0.16b, v0.16b, v3.16b1392; CHECK-CVT-GI-NEXT: uzp1 v0.8h, v1.8h, v0.8h1393; CHECK-CVT-GI-NEXT: xtn v0.8b, v0.8h1394; CHECK-CVT-GI-NEXT: ret1395 %1 = fcmp ord <8 x half> %a, %b1396 ret <8 x i1> %11397}1398 1399attributes #0 = { nounwind }1400 1401;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1402; CHECK-CVT: {{.*}}1403