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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s3 4define <4 x i16> @v4f16_to_v4i16(float, <4 x half> %a) #0 {5; CHECK-LABEL: v4f16_to_v4i16:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: fmov d0, d18; CHECK-NEXT: ret9entry:10 %1 = bitcast <4 x half> %a to <4 x i16>11 ret <4 x i16> %112}13 14define <2 x i32> @v4f16_to_v2i32(float, <4 x half> %a) #0 {15; CHECK-LABEL: v4f16_to_v2i32:16; CHECK: // %bb.0: // %entry17; CHECK-NEXT: fmov d0, d118; CHECK-NEXT: ret19entry:20 %1 = bitcast <4 x half> %a to <2 x i32>21 ret <2 x i32> %122}23 24define <1 x i64> @v4f16_to_v1i64(float, <4 x half> %a) #0 {25; CHECK-LABEL: v4f16_to_v1i64:26; CHECK: // %bb.0: // %entry27; CHECK-NEXT: fmov d0, d128; CHECK-NEXT: ret29entry:30 %1 = bitcast <4 x half> %a to <1 x i64>31 ret <1 x i64> %132}33 34define i64 @v4f16_to_i64(float, <4 x half> %a) #0 {35; CHECK-LABEL: v4f16_to_i64:36; CHECK: // %bb.0: // %entry37; CHECK-NEXT: fmov x0, d138; CHECK-NEXT: ret39entry:40 %1 = bitcast <4 x half> %a to i6441 ret i64 %142}43 44define <2 x float> @v4f16_to_v2float(float, <4 x half> %a) #0 {45; CHECK-LABEL: v4f16_to_v2float:46; CHECK: // %bb.0: // %entry47; CHECK-NEXT: fmov d0, d148; CHECK-NEXT: ret49entry:50 %1 = bitcast <4 x half> %a to <2 x float>51 ret <2 x float> %152}53 54define <1 x double> @v4f16_to_v1double(float, <4 x half> %a) #0 {55; CHECK-LABEL: v4f16_to_v1double:56; CHECK: // %bb.0: // %entry57; CHECK-NEXT: fmov d0, d158; CHECK-NEXT: ret59entry:60 %1 = bitcast <4 x half> %a to <1 x double>61 ret <1 x double> %162}63 64define double @v4f16_to_double(float, <4 x half> %a) #0 {65; CHECK-LABEL: v4f16_to_double:66; CHECK: // %bb.0: // %entry67; CHECK-NEXT: fmov d0, d168; CHECK-NEXT: ret69entry:70 %1 = bitcast <4 x half> %a to double71 ret double %172}73 74 75define <4 x half> @v4i16_to_v4f16(float, <4 x i16> %a) #0 {76; CHECK-LABEL: v4i16_to_v4f16:77; CHECK: // %bb.0: // %entry78; CHECK-NEXT: fmov d0, d179; CHECK-NEXT: ret80entry:81 %1 = bitcast <4 x i16> %a to <4 x half>82 ret <4 x half> %183}84 85define <4 x half> @v2i32_to_v4f16(float, <2 x i32> %a) #0 {86; CHECK-LABEL: v2i32_to_v4f16:87; CHECK: // %bb.0: // %entry88; CHECK-NEXT: fmov d0, d189; CHECK-NEXT: ret90entry:91 %1 = bitcast <2 x i32> %a to <4 x half>92 ret <4 x half> %193}94 95define <4 x half> @v1i64_to_v4f16(float, <1 x i64> %a) #0 {96; CHECK-LABEL: v1i64_to_v4f16:97; CHECK: // %bb.0: // %entry98; CHECK-NEXT: fmov d0, d199; CHECK-NEXT: ret100entry:101 %1 = bitcast <1 x i64> %a to <4 x half>102 ret <4 x half> %1103}104 105define <4 x half> @i64_to_v4f16(float, i64 %a) #0 {106; CHECK-LABEL: i64_to_v4f16:107; CHECK: // %bb.0: // %entry108; CHECK-NEXT: fmov d0, x0109; CHECK-NEXT: ret110entry:111 %1 = bitcast i64 %a to <4 x half>112 ret <4 x half> %1113}114 115define <4 x half> @v2float_to_v4f16(float, <2 x float> %a) #0 {116; CHECK-LABEL: v2float_to_v4f16:117; CHECK: // %bb.0: // %entry118; CHECK-NEXT: fmov d0, d1119; CHECK-NEXT: ret120entry:121 %1 = bitcast <2 x float> %a to <4 x half>122 ret <4 x half> %1123}124 125define <4 x half> @v1double_to_v4f16(float, <1 x double> %a) #0 {126; CHECK-LABEL: v1double_to_v4f16:127; CHECK: // %bb.0: // %entry128; CHECK-NEXT: fmov d0, d1129; CHECK-NEXT: ret130entry:131 %1 = bitcast <1 x double> %a to <4 x half>132 ret <4 x half> %1133}134 135define <4 x half> @double_to_v4f16(float, double %a) #0 {136; CHECK-LABEL: double_to_v4f16:137; CHECK: // %bb.0: // %entry138; CHECK-NEXT: fmov d0, d1139; CHECK-NEXT: ret140entry:141 %1 = bitcast double %a to <4 x half>142 ret <4 x half> %1143}144 145 146 147 148 149 150 151 152 153 154define <8 x i16> @v8f16_to_v8i16(float, <8 x half> %a) #0 {155; CHECK-LABEL: v8f16_to_v8i16:156; CHECK: // %bb.0: // %entry157; CHECK-NEXT: mov v0.16b, v1.16b158; CHECK-NEXT: ret159entry:160 %1 = bitcast <8 x half> %a to <8 x i16>161 ret <8 x i16> %1162}163 164define <4 x i32> @v8f16_to_v4i32(float, <8 x half> %a) #0 {165; CHECK-LABEL: v8f16_to_v4i32:166; CHECK: // %bb.0: // %entry167; CHECK-NEXT: mov v0.16b, v1.16b168; CHECK-NEXT: ret169entry:170 %1 = bitcast <8 x half> %a to <4 x i32>171 ret <4 x i32> %1172}173 174define <2 x i64> @v8f16_to_v2i64(float, <8 x half> %a) #0 {175; CHECK-LABEL: v8f16_to_v2i64:176; CHECK: // %bb.0: // %entry177; CHECK-NEXT: mov v0.16b, v1.16b178; CHECK-NEXT: ret179entry:180 %1 = bitcast <8 x half> %a to <2 x i64>181 ret <2 x i64> %1182}183 184define <4 x float> @v8f16_to_v4float(float, <8 x half> %a) #0 {185; CHECK-LABEL: v8f16_to_v4float:186; CHECK: // %bb.0: // %entry187; CHECK-NEXT: mov v0.16b, v1.16b188; CHECK-NEXT: ret189entry:190 %1 = bitcast <8 x half> %a to <4 x float>191 ret <4 x float> %1192}193 194define <2 x double> @v8f16_to_v2double(float, <8 x half> %a) #0 {195; CHECK-LABEL: v8f16_to_v2double:196; CHECK: // %bb.0: // %entry197; CHECK-NEXT: mov v0.16b, v1.16b198; CHECK-NEXT: ret199entry:200 %1 = bitcast <8 x half> %a to <2 x double>201 ret <2 x double> %1202}203 204define <8 x half> @v8i16_to_v8f16(float, <8 x i16> %a) #0 {205; CHECK-LABEL: v8i16_to_v8f16:206; CHECK: // %bb.0: // %entry207; CHECK-NEXT: mov v0.16b, v1.16b208; CHECK-NEXT: ret209entry:210 %1 = bitcast <8 x i16> %a to <8 x half>211 ret <8 x half> %1212}213 214define <8 x half> @v4i32_to_v8f16(float, <4 x i32> %a) #0 {215; CHECK-LABEL: v4i32_to_v8f16:216; CHECK: // %bb.0: // %entry217; CHECK-NEXT: mov v0.16b, v1.16b218; CHECK-NEXT: ret219entry:220 %1 = bitcast <4 x i32> %a to <8 x half>221 ret <8 x half> %1222}223 224define <8 x half> @v2i64_to_v8f16(float, <2 x i64> %a) #0 {225; CHECK-LABEL: v2i64_to_v8f16:226; CHECK: // %bb.0: // %entry227; CHECK-NEXT: mov v0.16b, v1.16b228; CHECK-NEXT: ret229entry:230 %1 = bitcast <2 x i64> %a to <8 x half>231 ret <8 x half> %1232}233 234define <8 x half> @v4float_to_v8f16(float, <4 x float> %a) #0 {235; CHECK-LABEL: v4float_to_v8f16:236; CHECK: // %bb.0: // %entry237; CHECK-NEXT: mov v0.16b, v1.16b238; CHECK-NEXT: ret239entry:240 %1 = bitcast <4 x float> %a to <8 x half>241 ret <8 x half> %1242}243 244define <8 x half> @v2double_to_v8f16(float, <2 x double> %a) #0 {245; CHECK-LABEL: v2double_to_v8f16:246; CHECK: // %bb.0: // %entry247; CHECK-NEXT: mov v0.16b, v1.16b248; CHECK-NEXT: ret249entry:250 %1 = bitcast <2 x double> %a to <8 x half>251 ret <8 x half> %1252}253