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1; RUN: llc < %s -mtriple=aarch64 | FileCheck %s2 3; Simple load of v4i164define <4 x half> @load_64(ptr nocapture readonly %a) #0 {5; CHECK-LABEL: load_64:6; CHECK: ldr d0, [x0]7entry:8 %0 = load <4 x half>, ptr %a, align 89 ret <4 x half> %010}11 12; Simple load of v8i1613define <8 x half> @load_128(ptr nocapture readonly %a) #0 {14; CHECK-LABEL: load_128:15; CHECK: ldr q0, [x0]16entry:17 %0 = load <8 x half>, ptr %a, align 1618 ret <8 x half> %019}20 21; Duplicating load to v4i1622define <4 x half> @load_dup_64(ptr nocapture readonly %a) #0 {23; CHECK-LABEL: load_dup_64:24; CHECK: ld1r { v0.4h }, [x0]25entry:26 %0 = load half, ptr %a, align 227 %1 = insertelement <4 x half> undef, half %0, i32 028 %2 = shufflevector <4 x half> %1, <4 x half> undef, <4 x i32> zeroinitializer29 ret <4 x half> %230}31 32; Duplicating load to v8i1633define <8 x half> @load_dup_128(ptr nocapture readonly %a) #0 {34; CHECK-LABEL: load_dup_128:35; CHECK: ld1r { v0.8h }, [x0]36entry:37 %0 = load half, ptr %a, align 238 %1 = insertelement <8 x half> undef, half %0, i32 039 %2 = shufflevector <8 x half> %1, <8 x half> undef, <8 x i32> zeroinitializer40 ret <8 x half> %241}42 43; Load to one lane of v4f1644define <4 x half> @load_lane_64(ptr nocapture readonly %a, <4 x half> %b) #0 {45; CHECK-LABEL: load_lane_64:46; CHECK: ld1 { v0.h }[2], [x0]47entry:48 %0 = load half, ptr %a, align 249 %1 = insertelement <4 x half> %b, half %0, i32 250 ret <4 x half> %151}52 53; Load to one lane of v8f1654define <8 x half> @load_lane_128(ptr nocapture readonly %a, <8 x half> %b) #0 {55; CHECK-LABEL: load_lane_128:56; CHECK: ld1 { v0.h }[5], [x0]57entry:58 %0 = load half, ptr %a, align 259 %1 = insertelement <8 x half> %b, half %0, i32 560 ret <8 x half> %161}62 63; Simple store of v4f1664define void @store_64(ptr nocapture %a, <4 x half> %b) #1 {65; CHECK-LABEL: store_64:66; CHECK: str d0, [x0]67entry:68 store <4 x half> %b, ptr %a, align 869 ret void70}71 72; Simple store of v8f1673define void @store_128(ptr nocapture %a, <8 x half> %b) #1 {74; CHECK-LABEL: store_128:75; CHECK: str q0, [x0]76entry:77 store <8 x half> %b, ptr %a, align 1678 ret void79}80 81; Store from one lane of v4f1682define void @store_lane_64(ptr nocapture %a, <4 x half> %b) #1 {83; CHECK-LABEL: store_lane_64:84; CHECK: st1 { v0.h }[2], [x0]85entry:86 %0 = extractelement <4 x half> %b, i32 287 store half %0, ptr %a, align 288 ret void89}90 91define void @store_lane0_64(ptr nocapture %a, <4 x half> %b) #1 {92; CHECK-LABEL: store_lane0_64:93; CHECK: str h0, [x0]94entry:95 %0 = extractelement <4 x half> %b, i32 096 store half %0, ptr %a, align 297 ret void98}99 100define void @storeu_lane0_64(ptr nocapture %a, <4 x half> %b) #1 {101; CHECK-LABEL: storeu_lane0_64:102; CHECK: stur h0, [x{{[0-9]+}}, #-2]103entry:104 %0 = getelementptr half, ptr %a, i64 -1105 %1 = extractelement <4 x half> %b, i32 0106 store half %1, ptr %0, align 2107 ret void108}109 110define void @storero_lane_64(ptr nocapture %a, <4 x half> %b, i64 %c) #1 {111; CHECK-LABEL: storero_lane_64:112; CHECK: st1 { v0.h }[2], [x{{[0-9]+}}]113entry:114 %0 = getelementptr half, ptr %a, i64 %c115 %1 = extractelement <4 x half> %b, i32 2116 store half %1, ptr %0, align 2117 ret void118}119 120define void @storero_lane0_64(ptr nocapture %a, <4 x half> %b, i64 %c) #1 {121; CHECK-LABEL: storero_lane0_64:122; CHECK: str h0, [x0, x1, lsl #1]123entry:124 %0 = getelementptr half, ptr %a, i64 %c125 %1 = extractelement <4 x half> %b, i32 0126 store half %1, ptr %0, align 2127 ret void128}129 130; Store from one lane of v8f16131define void @store_lane_128(ptr nocapture %a, <8 x half> %b) #1 {132; CHECK-LABEL: store_lane_128:133; CHECK: st1 { v0.h }[5], [x0]134entry:135 %0 = extractelement <8 x half> %b, i32 5136 store half %0, ptr %a, align 2137 ret void138}139 140define void @store_lane0_128(ptr nocapture %a, <8 x half> %b) #1 {141; CHECK-LABEL: store_lane0_128:142; CHECK: str h0, [x0]143entry:144 %0 = extractelement <8 x half> %b, i32 0145 store half %0, ptr %a, align 2146 ret void147}148 149define void @storeu_lane0_128(ptr nocapture %a, <8 x half> %b) #1 {150; CHECK-LABEL: storeu_lane0_128:151; CHECK: stur h0, [x{{[0-9]+}}, #-2]152entry:153 %0 = getelementptr half, ptr %a, i64 -1154 %1 = extractelement <8 x half> %b, i32 0155 store half %1, ptr %0, align 2156 ret void157}158 159define void @storero_lane_128(ptr nocapture %a, <8 x half> %b, i64 %c) #1 {160; CHECK-LABEL: storero_lane_128:161; CHECK: st1 { v0.h }[4], [x{{[0-9]+}}]162entry:163 %0 = getelementptr half, ptr %a, i64 %c164 %1 = extractelement <8 x half> %b, i32 4165 store half %1, ptr %0, align 2166 ret void167}168 169define void @storero_lane0_128(ptr nocapture %a, <8 x half> %b, i64 %c) #1 {170; CHECK-LABEL: storero_lane0_128:171; CHECK: str h0, [x0, x1, lsl #1]172entry:173 %0 = getelementptr half, ptr %a, i64 %c174 %1 = extractelement <8 x half> %b, i32 0175 store half %1, ptr %0, align 2176 ret void177}178 179; NEON intrinsics - (de-)interleaving loads and stores180declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2.v4f16.p0(ptr)181declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3.v4f16.p0(ptr)182declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4.v4f16.p0(ptr)183declare void @llvm.aarch64.neon.st2.v4f16.p0(<4 x half>, <4 x half>, ptr)184declare void @llvm.aarch64.neon.st3.v4f16.p0(<4 x half>, <4 x half>, <4 x half>, ptr)185declare void @llvm.aarch64.neon.st4.v4f16.p0(<4 x half>, <4 x half>, <4 x half>, <4 x half>, ptr)186declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2.v8f16.p0(ptr)187declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3.v8f16.p0(ptr)188declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4.v8f16.p0(ptr)189declare void @llvm.aarch64.neon.st2.v8f16.p0(<8 x half>, <8 x half>, ptr)190declare void @llvm.aarch64.neon.st3.v8f16.p0(<8 x half>, <8 x half>, <8 x half>, ptr)191declare void @llvm.aarch64.neon.st4.v8f16.p0(<8 x half>, <8 x half>, <8 x half>, <8 x half>, ptr)192 193; Load 2 x v4f16 with de-interleaving194define { <4 x half>, <4 x half> } @load_interleave_64_2(ptr %a) #0 {195; CHECK-LABEL: load_interleave_64_2:196; CHECK: ld2 { v0.4h, v1.4h }, [x0]197entry:198 %0 = tail call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2.v4f16.p0(ptr %a)199 ret { <4 x half>, <4 x half> } %0200}201 202; Load 3 x v4f16 with de-interleaving203define { <4 x half>, <4 x half>, <4 x half> } @load_interleave_64_3(ptr %a) #0 {204; CHECK-LABEL: load_interleave_64_3:205; CHECK: ld3 { v0.4h, v1.4h, v2.4h }, [x0]206entry:207 %0 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3.v4f16.p0(ptr %a)208 ret { <4 x half>, <4 x half>, <4 x half> } %0209}210 211; Load 4 x v4f16 with de-interleaving212define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @load_interleave_64_4(ptr %a) #0 {213; CHECK-LABEL: load_interleave_64_4:214; CHECK: ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0]215entry:216 %0 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4.v4f16.p0(ptr %a)217 ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %0218}219 220; Store 2 x v4f16 with interleaving221define void @store_interleave_64_2(ptr %a, <4 x half> %b, <4 x half> %c) #0 {222; CHECK-LABEL: store_interleave_64_2:223; CHECK: st2 { v0.4h, v1.4h }, [x0]224entry:225 tail call void @llvm.aarch64.neon.st2.v4f16.p0(<4 x half> %b, <4 x half> %c, ptr %a)226 ret void227}228 229; Store 3 x v4f16 with interleaving230define void @store_interleave_64_3(ptr %a, <4 x half> %b, <4 x half> %c, <4 x half> %d) #0 {231; CHECK-LABEL: store_interleave_64_3:232; CHECK: st3 { v0.4h, v1.4h, v2.4h }, [x0]233entry:234 tail call void @llvm.aarch64.neon.st3.v4f16.p0(<4 x half> %b, <4 x half> %c, <4 x half> %d, ptr %a)235 ret void236}237 238; Store 4 x v4f16 with interleaving239define void @store_interleave_64_4(ptr %a, <4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x half> %e) #0 {240; CHECK-LABEL: store_interleave_64_4:241; CHECK: st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0]242entry:243 tail call void @llvm.aarch64.neon.st4.v4f16.p0(<4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x half> %e, ptr %a)244 ret void245}246 247; Load 2 x v8f16 with de-interleaving248define { <8 x half>, <8 x half> } @load_interleave_128_2(ptr %a) #0 {249; CHECK-LABEL: load_interleave_128_2:250; CHECK: ld2 { v0.8h, v1.8h }, [x0]251entry:252 %0 = tail call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2.v8f16.p0(ptr %a)253 ret { <8 x half>, <8 x half> } %0254}255 256; Load 3 x v8f16 with de-interleaving257define { <8 x half>, <8 x half>, <8 x half> } @load_interleave_128_3(ptr %a) #0 {258; CHECK-LABEL: load_interleave_128_3:259; CHECK: ld3 { v0.8h, v1.8h, v2.8h }, [x0]260entry:261 %0 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3.v8f16.p0(ptr %a)262 ret { <8 x half>, <8 x half>, <8 x half> } %0263}264 265; Load 8 x v8f16 with de-interleaving266define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @load_interleave_128_4(ptr %a) #0 {267; CHECK-LABEL: load_interleave_128_4:268; CHECK: ld4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x0]269entry:270 %0 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4.v8f16.p0(ptr %a)271 ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %0272}273 274; Store 2 x v8f16 with interleaving275define void @store_interleave_128_2(ptr %a, <8 x half> %b, <8 x half> %c) #0 {276; CHECK-LABEL: store_interleave_128_2:277; CHECK: st2 { v0.8h, v1.8h }, [x0]278entry:279 tail call void @llvm.aarch64.neon.st2.v8f16.p0(<8 x half> %b, <8 x half> %c, ptr %a)280 ret void281}282 283; Store 3 x v8f16 with interleaving284define void @store_interleave_128_3(ptr %a, <8 x half> %b, <8 x half> %c, <8 x half> %d) #0 {285; CHECK-LABEL: store_interleave_128_3:286; CHECK: st3 { v0.8h, v1.8h, v2.8h }, [x0]287entry:288 tail call void @llvm.aarch64.neon.st3.v8f16.p0(<8 x half> %b, <8 x half> %c, <8 x half> %d, ptr %a)289 ret void290}291 292; Store 8 x v8f16 with interleaving293define void @store_interleave_128_4(ptr %a, <8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x half> %e) #0 {294; CHECK-LABEL: store_interleave_128_4:295; CHECK: st4 { v0.8h, v1.8h, v2.8h, v3.8h }, [x0]296entry:297 tail call void @llvm.aarch64.neon.st4.v8f16.p0(<8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x half> %e, ptr %a)298 ret void299}300 301; NEON intrinsics - duplicating loads302declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0(ptr)303declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0(ptr)304declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4r.v4f16.p0(ptr)305declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0(ptr)306declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0(ptr)307declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4r.v8f16.p0(ptr)308 309; Load 2 x v4f16 with duplication310define { <4 x half>, <4 x half> } @load_dup_64_2(ptr %a) #0 {311; CHECK-LABEL: load_dup_64_2:312; CHECK: ld2r { v0.4h, v1.4h }, [x0]313entry:314 %0 = tail call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2r.v4f16.p0(ptr %a)315 ret { <4 x half>, <4 x half> } %0316}317 318; Load 3 x v4f16 with duplication319define { <4 x half>, <4 x half>, <4 x half> } @load_dup_64_3(ptr %a) #0 {320; CHECK-LABEL: load_dup_64_3:321; CHECK: ld3r { v0.4h, v1.4h, v2.4h }, [x0]322entry:323 %0 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3r.v4f16.p0(ptr %a)324 ret { <4 x half>, <4 x half>, <4 x half> } %0325}326 327; Load 4 x v4f16 with duplication328define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @load_dup_64_4(ptr %a) #0 {329; CHECK-LABEL: load_dup_64_4:330; CHECK: ld4r { v0.4h, v1.4h, v2.4h, v3.4h }, [x0]331entry:332 %0 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4r.v4f16.p0(ptr %a)333 ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %0334}335 336; Load 2 x v8f16 with duplication337define { <8 x half>, <8 x half> } @load_dup_128_2(ptr %a) #0 {338; CHECK-LABEL: load_dup_128_2:339; CHECK: ld2r { v0.8h, v1.8h }, [x0]340entry:341 %0 = tail call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2r.v8f16.p0(ptr %a)342 ret { <8 x half>, <8 x half> } %0343}344 345; Load 3 x v8f16 with duplication346define { <8 x half>, <8 x half>, <8 x half> } @load_dup_128_3(ptr %a) #0 {347; CHECK-LABEL: load_dup_128_3:348; CHECK: ld3r { v0.8h, v1.8h, v2.8h }, [x0]349entry:350 %0 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3r.v8f16.p0(ptr %a)351 ret { <8 x half>, <8 x half>, <8 x half> } %0352}353 354; Load 8 x v8f16 with duplication355define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @load_dup_128_4(ptr %a) #0 {356; CHECK-LABEL: load_dup_128_4:357; CHECK: ld4r { v0.8h, v1.8h, v2.8h, v3.8h }, [x0]358entry:359 %0 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4r.v8f16.p0(ptr %a)360 ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %0361}362 363 364; NEON intrinsics - loads and stores to/from one lane365declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2lane.v4f16.p0(<4 x half>, <4 x half>, i64, ptr)366declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3lane.v4f16.p0(<4 x half>, <4 x half>, <4 x half>, i64, ptr)367declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4lane.v4f16.p0(<4 x half>, <4 x half>, <4 x half>, <4 x half>, i64, ptr)368declare void @llvm.aarch64.neon.st2lane.v4f16.p0(<4 x half>, <4 x half>, i64, ptr)369declare void @llvm.aarch64.neon.st3lane.v4f16.p0(<4 x half>, <4 x half>, <4 x half>, i64, ptr)370declare void @llvm.aarch64.neon.st4lane.v4f16.p0(<4 x half>, <4 x half>, <4 x half>, <4 x half>, i64, ptr)371declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2lane.v8f16.p0(<8 x half>, <8 x half>, i64, ptr)372declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3lane.v8f16.p0(<8 x half>, <8 x half>, <8 x half>, i64, ptr)373declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4lane.v8f16.p0(<8 x half>, <8 x half>, <8 x half>, <8 x half>, i64, ptr)374declare void @llvm.aarch64.neon.st2lane.v8f16.p0(<8 x half>, <8 x half>, i64, ptr)375declare void @llvm.aarch64.neon.st3lane.v8f16.p0(<8 x half>, <8 x half>, <8 x half>, i64, ptr)376declare void @llvm.aarch64.neon.st4lane.v8f16.p0(<8 x half>, <8 x half>, <8 x half>, <8 x half>, i64, ptr)377 378; Load one lane of 2 x v4f16379define { <4 x half>, <4 x half> } @load_lane_64_2(ptr %a, <4 x half> %b, <4 x half> %c) #0 {380; CHECK-LABEL: load_lane_64_2:381; CHECK: ld2 { v0.h, v1.h }[2], [x0]382entry:383 %0 = tail call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld2lane.v4f16.p0(<4 x half> %b, <4 x half> %c, i64 2, ptr %a)384 ret { <4 x half>, <4 x half> } %0385}386 387; Load one lane of 3 x v4f16388define { <4 x half>, <4 x half>, <4 x half> } @load_lane_64_3(ptr %a, <4 x half> %b, <4 x half> %c, <4 x half> %d) #0 {389; CHECK-LABEL: load_lane_64_3:390; CHECK: ld3 { v0.h, v1.h, v2.h }[2], [x0]391entry:392 %0 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld3lane.v4f16.p0(<4 x half> %b, <4 x half> %c, <4 x half> %d, i64 2, ptr %a)393 ret { <4 x half>, <4 x half>, <4 x half> } %0394}395 396; Load one lane of 4 x v4f16397define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @load_lane_64_4(ptr %a, <4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x half> %e) #0 {398; CHECK-LABEL: load_lane_64_4:399; CHECK: ld4 { v0.h, v1.h, v2.h, v3.h }[2], [x0]400entry:401 %0 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld4lane.v4f16.p0(<4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x half> %e, i64 2, ptr %a)402 ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %0403}404 405; Store one lane of 2 x v4f16406define void @store_lane_64_2(ptr %a, <4 x half> %b, <4 x half> %c) #0 {407; CHECK-LABEL: store_lane_64_2:408; CHECK: st2 { v0.h, v1.h }[2], [x0]409entry:410 tail call void @llvm.aarch64.neon.st2lane.v4f16.p0(<4 x half> %b, <4 x half> %c, i64 2, ptr %a)411 ret void412}413 414; Store one lane of 3 x v4f16415define void @store_lane_64_3(ptr %a, <4 x half> %b, <4 x half> %c, <4 x half> %d) #0 {416; CHECK-LABEL: store_lane_64_3:417; CHECK: st3 { v0.h, v1.h, v2.h }[2], [x0]418entry:419 tail call void @llvm.aarch64.neon.st3lane.v4f16.p0(<4 x half> %b, <4 x half> %c, <4 x half> %d, i64 2, ptr %a)420 ret void421}422 423; Store one lane of 4 x v4f16424define void @store_lane_64_4(ptr %a, <4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x half> %e) #0 {425; CHECK-LABEL: store_lane_64_4:426; CHECK: st4 { v0.h, v1.h, v2.h, v3.h }[2], [x0]427entry:428 tail call void @llvm.aarch64.neon.st4lane.v4f16.p0(<4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x half> %e, i64 2, ptr %a)429 ret void430}431 432; Load one lane of 2 x v8f16433define { <8 x half>, <8 x half> } @load_lane_128_2(ptr %a, <8 x half> %b, <8 x half> %c) #0 {434; CHECK-LABEL: load_lane_128_2:435; CHECK: ld2 { v0.h, v1.h }[2], [x0]436entry:437 %0 = tail call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2lane.v8f16.p0(<8 x half> %b, <8 x half> %c, i64 2, ptr %a)438 ret { <8 x half>, <8 x half> } %0439}440 441; Load one lane of 3 x v8f16442define { <8 x half>, <8 x half>, <8 x half> } @load_lane_128_3(ptr %a, <8 x half> %b, <8 x half> %c, <8 x half> %d) #0 {443; CHECK-LABEL: load_lane_128_3:444; CHECK: ld3 { v0.h, v1.h, v2.h }[2], [x0]445entry:446 %0 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3lane.v8f16.p0(<8 x half> %b, <8 x half> %c, <8 x half> %d, i64 2, ptr %a)447 ret { <8 x half>, <8 x half>, <8 x half> } %0448}449 450; Load one lane of 8 x v8f16451define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @load_lane_128_4(ptr %a, <8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x half> %e) #0 {452; CHECK-LABEL: load_lane_128_4:453; CHECK: ld4 { v0.h, v1.h, v2.h, v3.h }[2], [x0]454entry:455 %0 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4lane.v8f16.p0(<8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x half> %e, i64 2, ptr %a)456 ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %0457}458 459; Store one lane of 2 x v8f16460define void @store_lane_128_2(ptr %a, <8 x half> %b, <8 x half> %c) #0 {461; CHECK-LABEL: store_lane_128_2:462; CHECK: st2 { v0.h, v1.h }[2], [x0]463entry:464 tail call void @llvm.aarch64.neon.st2lane.v8f16.p0(<8 x half> %b, <8 x half> %c, i64 2, ptr %a)465 ret void466}467 468; Store one lane of 3 x v8f16469define void @store_lane_128_3(ptr %a, <8 x half> %b, <8 x half> %c, <8 x half> %d) #0 {470; CHECK-LABEL: store_lane_128_3:471; CHECK: st3 { v0.h, v1.h, v2.h }[2], [x0]472entry:473 tail call void @llvm.aarch64.neon.st3lane.v8f16.p0(<8 x half> %b, <8 x half> %c, <8 x half> %d, i64 2, ptr %a)474 ret void475}476 477; Store one lane of 8 x v8f16478define void @store_lane_128_4(ptr %a, <8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x half> %e) #0 {479; CHECK-LABEL: store_lane_128_4:480; CHECK: st4 { v0.h, v1.h, v2.h, v3.h }[2], [x0]481entry:482 tail call void @llvm.aarch64.neon.st4lane.v8f16.p0(<8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x half> %e, i64 2, ptr %a)483 ret void484}485 486; NEON intrinsics - load/store without interleaving487declare { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr)488declare { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr)489declare { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr)490declare void @llvm.aarch64.neon.st1x2.v4f16.p0(<4 x half>, <4 x half>, ptr)491declare void @llvm.aarch64.neon.st1x3.v4f16.p0(<4 x half>, <4 x half>, <4 x half>, ptr)492declare void @llvm.aarch64.neon.st1x4.v4f16.p0(<4 x half>, <4 x half>, <4 x half>, <4 x half>, ptr)493declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x2.v8f16.p0(ptr)494declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x3.v8f16.p0(ptr)495declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x4.v8f16.p0(ptr)496declare void @llvm.aarch64.neon.st1x2.v8f16.p0(<8 x half>, <8 x half>, ptr)497declare void @llvm.aarch64.neon.st1x3.v8f16.p0(<8 x half>, <8 x half>, <8 x half>, ptr)498declare void @llvm.aarch64.neon.st1x4.v8f16.p0(<8 x half>, <8 x half>, <8 x half>, <8 x half>, ptr)499 500; Load 2 x v4f16 without de-interleaving501define { <4 x half>, <4 x half> } @load_64_2(ptr %a) #0 {502; CHECK-LABEL: load_64_2:503; CHECK: ld1 { v0.4h, v1.4h }, [x0]504entry:505 %0 = tail call { <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x2.v4f16.p0(ptr %a)506 ret { <4 x half>, <4 x half> } %0507}508 509; Load 3 x v4f16 without de-interleaving510define { <4 x half>, <4 x half>, <4 x half> } @load_64_3(ptr %a) #0 {511; CHECK-LABEL: load_64_3:512; CHECK: ld1 { v0.4h, v1.4h, v2.4h }, [x0]513entry:514 %0 = tail call { <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x3.v4f16.p0(ptr %a)515 ret { <4 x half>, <4 x half>, <4 x half> } %0516}517 518; Load 4 x v4f16 without de-interleaving519define { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @load_64_4(ptr %a) #0 {520; CHECK-LABEL: load_64_4:521; CHECK: ld1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0]522entry:523 %0 = tail call { <4 x half>, <4 x half>, <4 x half>, <4 x half> } @llvm.aarch64.neon.ld1x4.v4f16.p0(ptr %a)524 ret { <4 x half>, <4 x half>, <4 x half>, <4 x half> } %0525}526 527; Store 2 x v4f16 without interleaving528define void @store_64_2(ptr %a, <4 x half> %b, <4 x half> %c) #0 {529; CHECK-LABEL: store_64_2:530; CHECK: st1 { v0.4h, v1.4h }, [x0]531entry:532 tail call void @llvm.aarch64.neon.st1x2.v4f16.p0(<4 x half> %b, <4 x half> %c, ptr %a)533 ret void534}535 536; Store 3 x v4f16 without interleaving537define void @store_64_3(ptr %a, <4 x half> %b, <4 x half> %c, <4 x half> %d) #0 {538; CHECK-LABEL: store_64_3:539; CHECK: st1 { v0.4h, v1.4h, v2.4h }, [x0]540entry:541 tail call void @llvm.aarch64.neon.st1x3.v4f16.p0(<4 x half> %b, <4 x half> %c, <4 x half> %d, ptr %a)542 ret void543}544 545; Store 4 x v4f16 without interleaving546define void @store_64_4(ptr %a, <4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x half> %e) #0 {547; CHECK-LABEL: store_64_4:548; CHECK: st1 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0]549entry:550 tail call void @llvm.aarch64.neon.st1x4.v4f16.p0(<4 x half> %b, <4 x half> %c, <4 x half> %d, <4 x half> %e, ptr %a)551 ret void552}553 554; Load 2 x v8f16 without de-interleaving555define { <8 x half>, <8 x half> } @load_128_2(ptr %a) #0 {556; CHECK-LABEL: load_128_2:557; CHECK: ld1 { v0.8h, v1.8h }, [x0]558entry:559 %0 = tail call { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x2.v8f16.p0(ptr %a)560 ret { <8 x half>, <8 x half> } %0561}562 563; Load 3 x v8f16 without de-interleaving564define { <8 x half>, <8 x half>, <8 x half> } @load_128_3(ptr %a) #0 {565; CHECK-LABEL: load_128_3:566; CHECK: ld1 { v0.8h, v1.8h, v2.8h }, [x0]567entry:568 %0 = tail call { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x3.v8f16.p0(ptr %a)569 ret { <8 x half>, <8 x half>, <8 x half> } %0570}571 572; Load 8 x v8f16 without de-interleaving573define { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @load_128_4(ptr %a) #0 {574; CHECK-LABEL: load_128_4:575; CHECK: ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x0]576entry:577 %0 = tail call { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld1x4.v8f16.p0(ptr %a)578 ret { <8 x half>, <8 x half>, <8 x half>, <8 x half> } %0579}580 581; Store 2 x v8f16 without interleaving582define void @store_128_2(ptr %a, <8 x half> %b, <8 x half> %c) #0 {583; CHECK-LABEL: store_128_2:584; CHECK: st1 { v0.8h, v1.8h }, [x0]585entry:586 tail call void @llvm.aarch64.neon.st1x2.v8f16.p0(<8 x half> %b, <8 x half> %c, ptr %a)587 ret void588}589 590; Store 3 x v8f16 without interleaving591define void @store_128_3(ptr %a, <8 x half> %b, <8 x half> %c, <8 x half> %d) #0 {592; CHECK-LABEL: store_128_3:593; CHECK: st1 { v0.8h, v1.8h, v2.8h }, [x0]594entry:595 tail call void @llvm.aarch64.neon.st1x3.v8f16.p0(<8 x half> %b, <8 x half> %c, <8 x half> %d, ptr %a)596 ret void597}598 599; Store 8 x v8f16 without interleaving600define void @store_128_4(ptr %a, <8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x half> %e) #0 {601; CHECK-LABEL: store_128_4:602; CHECK: st1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x0]603entry:604 tail call void @llvm.aarch64.neon.st1x4.v8f16.p0(<8 x half> %b, <8 x half> %c, <8 x half> %d, <8 x half> %e, ptr %a)605 ret void606}607