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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=aarch64 -global-isel=0 -mattr=+v8.2a,+fullfp16 | FileCheck %s3 4; Test f16 -> i16 NEON intrinics, currently only supported in SDAG.5; Should be merged with fp16_intrinsic_scalar_1op.ll once there is6; support in GlSel.7 8declare i16 @llvm.aarch64.neon.fcvtzs.i16.f16(half)9declare i16 @llvm.aarch64.neon.fcvtzu.i16.f16(half)10declare i16 @llvm.aarch64.neon.fcvtas.i16.f16(half)11declare i16 @llvm.aarch64.neon.fcvtau.i16.f16(half)12declare i16 @llvm.aarch64.neon.fcvtms.i16.f16(half)13declare i16 @llvm.aarch64.neon.fcvtmu.i16.f16(half)14declare i16 @llvm.aarch64.neon.fcvtns.i16.f16(half)15declare i16 @llvm.aarch64.neon.fcvtnu.i16.f16(half)16declare i16 @llvm.aarch64.neon.fcvtps.i16.f16(half)17declare i16 @llvm.aarch64.neon.fcvtpu.i16.f16(half)18 19 20define i16 @fcvtzs_intrinsic_i16(half %a) {21; CHECK-LABEL: fcvtzs_intrinsic_i16:22; CHECK: // %bb.0: // %entry23; CHECK-NEXT: fcvtzs h0, h024; CHECK-NEXT: fmov w0, s025; CHECK-NEXT: ret26entry:27 %fcvt = tail call i16 @llvm.aarch64.neon.fcvtzs.i16.f16(half %a)28 ret i16 %fcvt29}30 31define i16 @fcvtzu_intrinsic_i16(half %a) {32; CHECK-LABEL: fcvtzu_intrinsic_i16:33; CHECK: // %bb.0: // %entry34; CHECK-NEXT: fcvtzu h0, h035; CHECK-NEXT: fmov w0, s036; CHECK-NEXT: ret37entry:38 %fcvt = tail call i16 @llvm.aarch64.neon.fcvtzu.i16.f16(half %a)39 ret i16 %fcvt40}41 42define i16 @fcvtas_intrinsic_i16(half %a) {43; CHECK-LABEL: fcvtas_intrinsic_i16:44; CHECK: // %bb.0: // %entry45; CHECK-NEXT: fcvtas h0, h046; CHECK-NEXT: fmov w0, s047; CHECK-NEXT: ret48entry:49 %fcvt = tail call i16 @llvm.aarch64.neon.fcvtas.i16.f16(half %a)50 ret i16 %fcvt51}52 53define i16 @fcvtau_intrinsic_i16(half %a) {54; CHECK-LABEL: fcvtau_intrinsic_i16:55; CHECK: // %bb.0: // %entry56; CHECK-NEXT: fcvtau h0, h057; CHECK-NEXT: fmov w0, s058; CHECK-NEXT: ret59entry:60 %fcvt = tail call i16 @llvm.aarch64.neon.fcvtau.i16.f16(half %a)61 ret i16 %fcvt62}63 64define i16 @fcvtms_intrinsic_i16(half %a) {65; CHECK-LABEL: fcvtms_intrinsic_i16:66; CHECK: // %bb.0: // %entry67; CHECK-NEXT: fcvtms h0, h068; CHECK-NEXT: fmov w0, s069; CHECK-NEXT: ret70entry:71 %fcvt = tail call i16 @llvm.aarch64.neon.fcvtms.i16.f16(half %a)72 ret i16 %fcvt73}74 75define i16 @fcvtmu_intrinsic_i16(half %a) {76; CHECK-LABEL: fcvtmu_intrinsic_i16:77; CHECK: // %bb.0: // %entry78; CHECK-NEXT: fcvtmu h0, h079; CHECK-NEXT: fmov w0, s080; CHECK-NEXT: ret81entry:82 %fcvt = tail call i16 @llvm.aarch64.neon.fcvtmu.i16.f16(half %a)83 ret i16 %fcvt84}85 86define i16 @fcvtns_intrinsic_i16(half %a) {87; CHECK-LABEL: fcvtns_intrinsic_i16:88; CHECK: // %bb.0: // %entry89; CHECK-NEXT: fcvtns h0, h090; CHECK-NEXT: fmov w0, s091; CHECK-NEXT: ret92entry:93 %fcvt = tail call i16 @llvm.aarch64.neon.fcvtns.i16.f16(half %a)94 ret i16 %fcvt95}96 97define i16 @fcvtnu_intrinsic_i16(half %a) {98; CHECK-LABEL: fcvtnu_intrinsic_i16:99; CHECK: // %bb.0: // %entry100; CHECK-NEXT: fcvtnu h0, h0101; CHECK-NEXT: fmov w0, s0102; CHECK-NEXT: ret103entry:104 %fcvt = tail call i16 @llvm.aarch64.neon.fcvtnu.i16.f16(half %a)105 ret i16 %fcvt106}107 108define i16 @fcvtps_intrinsic_i16(half %a) {109; CHECK-LABEL: fcvtps_intrinsic_i16:110; CHECK: // %bb.0: // %entry111; CHECK-NEXT: fcvtps h0, h0112; CHECK-NEXT: fmov w0, s0113; CHECK-NEXT: ret114entry:115 %fcvt = tail call i16 @llvm.aarch64.neon.fcvtps.i16.f16(half %a)116 ret i16 %fcvt117}118 119define i16 @fcvtpu_intrinsic_i16(half %a) {120; CHECK-LABEL: fcvtpu_intrinsic_i16:121; CHECK: // %bb.0: // %entry122; CHECK-NEXT: fcvtpu h0, h0123; CHECK-NEXT: fmov w0, s0124; CHECK-NEXT: ret125entry:126 %fcvt = tail call i16 @llvm.aarch64.neon.fcvtpu.i16.f16(half %a)127 ret i16 %fcvt128}129