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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 -mattr=+v8.2a,+fullfp16 | FileCheck %s3 4declare half @llvm.aarch64.neon.fmulx.f16(half, half)5declare <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half>, <4 x half>)6declare <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half>, <8 x half>)7declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>)8declare <8 x half> @llvm.fma.v8f16(<8 x half>, <8 x half>, <8 x half>)9declare half @llvm.fma.f16(half, half, half) #110 11define <4 x half> @t_vfma_lane_f16(<4 x half> %a, <4 x half> %b, <4 x half> %c, i32 %lane) {12; CHECK-LABEL: t_vfma_lane_f16:13; CHECK: // %bb.0: // %entry14; CHECK-NEXT: // kill: def $d2 killed $d2 def $q215; CHECK-NEXT: fmla v0.4h, v1.4h, v2.h[0]16; CHECK-NEXT: ret17entry:18 %lane1 = shufflevector <4 x half> %c, <4 x half> undef, <4 x i32> zeroinitializer19 %fmla3 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> %lane1, <4 x half> %a)20 ret <4 x half> %fmla321}22 23define <8 x half> @t_vfmaq_lane_f16(<8 x half> %a, <8 x half> %b, <4 x half> %c, i32 %lane) {24; CHECK-LABEL: t_vfmaq_lane_f16:25; CHECK: // %bb.0: // %entry26; CHECK-NEXT: // kill: def $d2 killed $d2 def $q227; CHECK-NEXT: fmla v0.8h, v1.8h, v2.h[0]28; CHECK-NEXT: ret29entry:30 %lane1 = shufflevector <4 x half> %c, <4 x half> undef, <8 x i32> zeroinitializer31 %fmla3 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %lane1, <8 x half> %a)32 ret <8 x half> %fmla333}34 35define <4 x half> @t_vfma_laneq_f16(<4 x half> %a, <4 x half> %b, <8 x half> %c, i32 %lane) {36; CHECK-LABEL: t_vfma_laneq_f16:37; CHECK: // %bb.0: // %entry38; CHECK-NEXT: fmla v0.4h, v1.4h, v2.h[0]39; CHECK-NEXT: ret40entry:41 %lane1 = shufflevector <8 x half> %c, <8 x half> undef, <4 x i32> zeroinitializer42 %0 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %lane1, <4 x half> %b, <4 x half> %a)43 ret <4 x half> %044}45 46define <8 x half> @t_vfmaq_laneq_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, i32 %lane) {47; CHECK-LABEL: t_vfmaq_laneq_f16:48; CHECK: // %bb.0: // %entry49; CHECK-NEXT: fmla v0.8h, v1.8h, v2.h[0]50; CHECK-NEXT: ret51entry:52 %lane1 = shufflevector <8 x half> %c, <8 x half> undef, <8 x i32> zeroinitializer53 %0 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %lane1, <8 x half> %b, <8 x half> %a)54 ret <8 x half> %055}56 57define <4 x half> @t_vfma_n_f16(<4 x half> %a, <4 x half> %b, half %c) {58; CHECK-LABEL: t_vfma_n_f16:59; CHECK: // %bb.0: // %entry60; CHECK-NEXT: // kill: def $h2 killed $h2 def $q261; CHECK-NEXT: fmla v0.4h, v1.4h, v2.h[0]62; CHECK-NEXT: ret63entry:64 %vecinit = insertelement <4 x half> undef, half %c, i32 065 %vecinit3 = shufflevector <4 x half> %vecinit, <4 x half> undef, <4 x i32> zeroinitializer66 %0 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> %vecinit3, <4 x half> %a) #467 ret <4 x half> %068}69 70define <8 x half> @t_vfmaq_n_f16(<8 x half> %a, <8 x half> %b, half %c) {71; CHECK-LABEL: t_vfmaq_n_f16:72; CHECK: // %bb.0: // %entry73; CHECK-NEXT: // kill: def $h2 killed $h2 def $q274; CHECK-NEXT: fmla v0.8h, v1.8h, v2.h[0]75; CHECK-NEXT: ret76entry:77 %vecinit = insertelement <8 x half> undef, half %c, i32 078 %vecinit7 = shufflevector <8 x half> %vecinit, <8 x half> undef, <8 x i32> zeroinitializer79 %0 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %vecinit7, <8 x half> %a) #480 ret <8 x half> %081}82 83define half @t_vfmah_lane_f16_0(half %a, half %b, <4 x half> %c, i32 %lane) {84; CHECK-LABEL: t_vfmah_lane_f16_0:85; CHECK: // %bb.0: // %entry86; CHECK-NEXT: // kill: def $d2 killed $d2 def $q287; CHECK-NEXT: fmadd h0, h1, h2, h088; CHECK-NEXT: ret89entry:90 %extract = extractelement <4 x half> %c, i32 091 %0 = tail call half @llvm.fma.f16(half %b, half %extract, half %a)92 ret half %093}94 95define half @t_vfmah_lane_f16_0_swap(half %a, half %b, <4 x half> %c, i32 %lane) {96; CHECK-LABEL: t_vfmah_lane_f16_0_swap:97; CHECK: // %bb.0: // %entry98; CHECK-NEXT: // kill: def $d2 killed $d2 def $q299; CHECK-NEXT: fmadd h0, h2, h1, h0100; CHECK-NEXT: ret101entry:102 %extract = extractelement <4 x half> %c, i32 0103 %0 = tail call half @llvm.fma.f16(half %extract, half %b, half %a)104 ret half %0105}106 107define half @t_vfmah_lane_f16_3(half %a, half %b, <4 x half> %c, i32 %lane) {108; CHECK-LABEL: t_vfmah_lane_f16_3:109; CHECK: // %bb.0: // %entry110; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2111; CHECK-NEXT: fmla h0, h1, v2.h[3]112; CHECK-NEXT: ret113entry:114 %extract = extractelement <4 x half> %c, i32 3115 %0 = tail call half @llvm.fma.f16(half %b, half %extract, half %a)116 ret half %0117}118 119define half @t_vfmah_lane_f16_3_0(half %a, <4 x half> %c) {120; CHECK-LABEL: t_vfmah_lane_f16_3_0:121; CHECK: // %bb.0: // %entry122; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1123; CHECK-NEXT: fmla h0, h1, v1.h[3]124; CHECK-NEXT: ret125entry:126 %b = extractelement <4 x half> %c, i32 0127 %extract = extractelement <4 x half> %c, i32 3128 %0 = tail call half @llvm.fma.f16(half %b, half %extract, half %a)129 ret half %0130}131 132define half @t_vfmah_lane_f16_0_0(half %a, <4 x half> %b, <4 x half> %c) {133; CHECK-LABEL: t_vfmah_lane_f16_0_0:134; CHECK: // %bb.0: // %entry135; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2136; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1137; CHECK-NEXT: fmadd h0, h1, h2, h0138; CHECK-NEXT: ret139entry:140 %b0 = extractelement <4 x half> %b, i32 0141 %c0 = extractelement <4 x half> %c, i32 0142 %0 = tail call half @llvm.fma.f16(half %b0, half %c0, half %a)143 ret half %0144}145 146define half @t_vfmah_laneq_f16_0(half %a, half %b, <8 x half> %c, i32 %lane) {147; CHECK-LABEL: t_vfmah_laneq_f16_0:148; CHECK: // %bb.0: // %entry149; CHECK-NEXT: fmadd h0, h1, h2, h0150; CHECK-NEXT: ret151entry:152 %extract = extractelement <8 x half> %c, i32 0153 %0 = tail call half @llvm.fma.f16(half %b, half %extract, half %a)154 ret half %0155}156 157define half @t_vfmah_laneq_f16_0_swap(half %a, half %b, <8 x half> %c, i32 %lane) {158; CHECK-LABEL: t_vfmah_laneq_f16_0_swap:159; CHECK: // %bb.0: // %entry160; CHECK-NEXT: fmadd h0, h2, h1, h0161; CHECK-NEXT: ret162entry:163 %extract = extractelement <8 x half> %c, i32 0164 %0 = tail call half @llvm.fma.f16(half %extract, half %b, half %a)165 ret half %0166}167 168define half @t_vfmah_laneq_f16_7(half %a, half %b, <8 x half> %c, i32 %lane) {169; CHECK-LABEL: t_vfmah_laneq_f16_7:170; CHECK: // %bb.0: // %entry171; CHECK-NEXT: fmla h0, h1, v2.h[7]172; CHECK-NEXT: ret173entry:174 %extract = extractelement <8 x half> %c, i32 7175 %0 = tail call half @llvm.fma.f16(half %b, half %extract, half %a)176 ret half %0177}178 179define <4 x half> @t_vfms_lane_f16(<4 x half> %a, <4 x half> %b, <4 x half> %c, i32 %lane) {180; CHECK-LABEL: t_vfms_lane_f16:181; CHECK: // %bb.0: // %entry182; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2183; CHECK-NEXT: fmls v0.4h, v1.4h, v2.h[0]184; CHECK-NEXT: ret185entry:186 %sub = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b187 %lane1 = shufflevector <4 x half> %c, <4 x half> undef, <4 x i32> zeroinitializer188 %fmla3 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %sub, <4 x half> %lane1, <4 x half> %a)189 ret <4 x half> %fmla3190}191 192define <8 x half> @t_vfmsq_lane_f16(<8 x half> %a, <8 x half> %b, <4 x half> %c, i32 %lane) {193; CHECK-LABEL: t_vfmsq_lane_f16:194; CHECK: // %bb.0: // %entry195; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2196; CHECK-NEXT: fmls v0.8h, v1.8h, v2.h[0]197; CHECK-NEXT: ret198entry:199 %sub = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b200 %lane1 = shufflevector <4 x half> %c, <4 x half> undef, <8 x i32> zeroinitializer201 %fmla3 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %sub, <8 x half> %lane1, <8 x half> %a)202 ret <8 x half> %fmla3203}204 205define <4 x half> @t_vfms_laneq_f16(<4 x half> %a, <4 x half> %b, <8 x half> %c, i32 %lane) {206; CHECK-LABEL: t_vfms_laneq_f16:207; CHECK: // %bb.0: // %entry208; CHECK-NEXT: fmls v0.4h, v1.4h, v2.h[0]209; CHECK-NEXT: ret210entry:211 %sub = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b212 %lane1 = shufflevector <8 x half> %c, <8 x half> undef, <4 x i32> zeroinitializer213 %0 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %lane1, <4 x half> %sub, <4 x half> %a)214 ret <4 x half> %0215}216 217define <8 x half> @t_vfmsq_laneq_f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, i32 %lane) {218; CHECK-LABEL: t_vfmsq_laneq_f16:219; CHECK: // %bb.0: // %entry220; CHECK-NEXT: fmls v0.8h, v1.8h, v2.h[0]221; CHECK-NEXT: ret222entry:223 %sub = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b224 %lane1 = shufflevector <8 x half> %c, <8 x half> undef, <8 x i32> zeroinitializer225 %0 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %lane1, <8 x half> %sub, <8 x half> %a)226 ret <8 x half> %0227}228 229define <4 x half> @t_vfms_n_f16(<4 x half> %a, <4 x half> %b, half %c) {230; CHECK-LABEL: t_vfms_n_f16:231; CHECK: // %bb.0: // %entry232; CHECK-NEXT: // kill: def $h2 killed $h2 def $q2233; CHECK-NEXT: fmls v0.4h, v1.4h, v2.h[0]234; CHECK-NEXT: ret235entry:236 %sub = fsub <4 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b237 %vecinit = insertelement <4 x half> undef, half %c, i32 0238 %vecinit3 = shufflevector <4 x half> %vecinit, <4 x half> undef, <4 x i32> zeroinitializer239 %0 = tail call <4 x half> @llvm.fma.v4f16(<4 x half> %sub, <4 x half> %vecinit3, <4 x half> %a) #4240 ret <4 x half> %0241}242 243define <8 x half> @t_vfmsq_n_f16(<8 x half> %a, <8 x half> %b, half %c) {244; CHECK-LABEL: t_vfmsq_n_f16:245; CHECK: // %bb.0: // %entry246; CHECK-NEXT: // kill: def $h2 killed $h2 def $q2247; CHECK-NEXT: fmls v0.8h, v1.8h, v2.h[0]248; CHECK-NEXT: ret249entry:250 %sub = fsub <8 x half> <half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000, half 0xH8000>, %b251 %vecinit = insertelement <8 x half> undef, half %c, i32 0252 %vecinit7 = shufflevector <8 x half> %vecinit, <8 x half> undef, <8 x i32> zeroinitializer253 %0 = tail call <8 x half> @llvm.fma.v8f16(<8 x half> %sub, <8 x half> %vecinit7, <8 x half> %a) #4254 ret <8 x half> %0255}256 257define half @t_vfmsh_lane_f16_0(half %a, half %b, <4 x half> %c, i32 %lane) {258; CHECK-LABEL: t_vfmsh_lane_f16_0:259; CHECK: // %bb.0: // %entry260; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2261; CHECK-NEXT: fmsub h0, h2, h1, h0262; CHECK-NEXT: ret263entry:264 %0 = fsub half 0xH8000, %b265 %extract = extractelement <4 x half> %c, i32 0266 %1 = tail call half @llvm.fma.f16(half %0, half %extract, half %a)267 ret half %1268}269 270define half @t_vfmsh_lane_f16_0_swap(half %a, half %b, <4 x half> %c, i32 %lane) {271; CHECK-LABEL: t_vfmsh_lane_f16_0_swap:272; CHECK: // %bb.0: // %entry273; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2274; CHECK-NEXT: fmsub h0, h2, h1, h0275; CHECK-NEXT: ret276entry:277 %0 = fsub half 0xH8000, %b278 %extract = extractelement <4 x half> %c, i32 0279 %1 = tail call half @llvm.fma.f16(half %extract, half %0, half %a)280 ret half %1281}282 283define half @t_vfmsh_lane_f16_3(half %a, half %b, <4 x half> %c, i32 %lane) {284; CHECK-LABEL: t_vfmsh_lane_f16_3:285; CHECK: // %bb.0: // %entry286; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2287; CHECK-NEXT: fmls h0, h1, v2.h[3]288; CHECK-NEXT: ret289entry:290 %0 = fsub half 0xH8000, %b291 %extract = extractelement <4 x half> %c, i32 3292 %1 = tail call half @llvm.fma.f16(half %0, half %extract, half %a)293 ret half %1294}295 296define half @t_vfmsh_laneq_f16_0(half %a, half %b, <8 x half> %c, i32 %lane) {297; CHECK-LABEL: t_vfmsh_laneq_f16_0:298; CHECK: // %bb.0: // %entry299; CHECK-NEXT: fmsub h0, h2, h1, h0300; CHECK-NEXT: ret301entry:302 %0 = fsub half 0xH8000, %b303 %extract = extractelement <8 x half> %c, i32 0304 %1 = tail call half @llvm.fma.f16(half %0, half %extract, half %a)305 ret half %1306}307 308define half @t_vfmsh_lane_f16_0_3(half %a, <4 x half> %c, i32 %lane) {309; CHECK-LABEL: t_vfmsh_lane_f16_0_3:310; CHECK: // %bb.0: // %entry311; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1312; CHECK-NEXT: fmls h0, h1, v1.h[3]313; CHECK-NEXT: ret314entry:315 %b = extractelement <4 x half> %c, i32 0316 %0 = fsub half 0xH8000, %b317 %extract = extractelement <4 x half> %c, i32 3318 %1 = tail call half @llvm.fma.f16(half %0, half %extract, half %a)319 ret half %1320}321 322define half @t_vfmsh_laneq_f16_0_swap(half %a, half %b, <8 x half> %c, i32 %lane) {323; CHECK-LABEL: t_vfmsh_laneq_f16_0_swap:324; CHECK: // %bb.0: // %entry325; CHECK-NEXT: fmsub h0, h2, h1, h0326; CHECK-NEXT: ret327entry:328 %0 = fsub half 0xH8000, %b329 %extract = extractelement <8 x half> %c, i32 0330 %1 = tail call half @llvm.fma.f16(half %extract, half %0, half %a)331 ret half %1332}333 334define half @t_vfmsh_laneq_f16_7(half %a, half %b, <8 x half> %c, i32 %lane) {335; CHECK-LABEL: t_vfmsh_laneq_f16_7:336; CHECK: // %bb.0: // %entry337; CHECK-NEXT: fmls h0, h1, v2.h[7]338; CHECK-NEXT: ret339entry:340 %0 = fsub half 0xH8000, %b341 %extract = extractelement <8 x half> %c, i32 7342 %1 = tail call half @llvm.fma.f16(half %0, half %extract, half %a)343 ret half %1344}345 346define <4 x half> @t_vmul_laneq_f16(<4 x half> %a, <8 x half> %b, i32 %lane) {347; CHECK-LABEL: t_vmul_laneq_f16:348; CHECK: // %bb.0: // %entry349; CHECK-NEXT: fmul v0.4h, v0.4h, v1.h[0]350; CHECK-NEXT: ret351entry:352 %shuffle = shufflevector <8 x half> %b, <8 x half> undef, <4 x i32> zeroinitializer353 %mul = fmul <4 x half> %shuffle, %a354 ret <4 x half> %mul355}356 357define <8 x half> @t_vmulq_laneq_f16(<8 x half> %a, <8 x half> %b, i32 %lane) {358; CHECK-LABEL: t_vmulq_laneq_f16:359; CHECK: // %bb.0: // %entry360; CHECK-NEXT: fmul v0.8h, v0.8h, v1.h[0]361; CHECK-NEXT: ret362entry:363 %shuffle = shufflevector <8 x half> %b, <8 x half> undef, <8 x i32> zeroinitializer364 %mul = fmul <8 x half> %shuffle, %a365 ret <8 x half> %mul366}367 368define half @t_vmulh_lane0_f16(half %a, <4 x half> %c, i32 %lane) {369; CHECK-LABEL: t_vmulh_lane0_f16:370; CHECK: // %bb.0: // %entry371; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1372; CHECK-NEXT: fmul h0, h0, h1373; CHECK-NEXT: ret374entry:375 %0 = extractelement <4 x half> %c, i32 0376 %1 = fmul half %0, %a377 ret half %1378}379 380define half @t_vmulh_lane3_f16(half %a, <4 x half> %c, i32 %lane) {381; CHECK-LABEL: t_vmulh_lane3_f16:382; CHECK: // %bb.0: // %entry383; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1384; CHECK-NEXT: fmul h0, h0, v1.h[3]385; CHECK-NEXT: ret386entry:387 %0 = extractelement <4 x half> %c, i32 3388 %1 = fmul half %0, %a389 ret half %1390}391 392define half @t_vmulh_laneq0_f16(half %a, <8 x half> %c, i32 %lane) {393; CHECK-LABEL: t_vmulh_laneq0_f16:394; CHECK: // %bb.0: // %entry395; CHECK-NEXT: fmul h0, h0, h1396; CHECK-NEXT: ret397entry:398 %0 = extractelement <8 x half> %c, i32 0399 %1 = fmul half %0, %a400 ret half %1401}402 403define half @t_vmulh_laneq7_f16(half %a, <8 x half> %c, i32 %lane) {404; CHECK-LABEL: t_vmulh_laneq7_f16:405; CHECK: // %bb.0: // %entry406; CHECK-NEXT: fmul h0, h0, v1.h[7]407; CHECK-NEXT: ret408entry:409 %0 = extractelement <8 x half> %c, i32 7410 %1 = fmul half %0, %a411 ret half %1412}413 414define half @t_vmulx_f16(half %a, half %b) {415; CHECK-LABEL: t_vmulx_f16:416; CHECK: // %bb.0: // %entry417; CHECK-NEXT: fmulx h0, h0, h1418; CHECK-NEXT: ret419entry:420 %fmulx.i = tail call half @llvm.aarch64.neon.fmulx.f16(half %a, half %b)421 ret half %fmulx.i422}423 424define half @t_vmulxh_lane0_f16(half %a, <4 x half> %b) {425; CHECK-LABEL: t_vmulxh_lane0_f16:426; CHECK: // %bb.0: // %entry427; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1428; CHECK-NEXT: fmulx h0, h0, h1429; CHECK-NEXT: ret430entry:431 %extract = extractelement <4 x half> %b, i32 0432 %fmulx.i = tail call half @llvm.aarch64.neon.fmulx.f16(half %a, half %extract)433 ret half %fmulx.i434}435 436define half @t_vmulxh_lane3_f16(half %a, <4 x half> %b, i32 %lane) {437; CHECK-LABEL: t_vmulxh_lane3_f16:438; CHECK: // %bb.0: // %entry439; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1440; CHECK-NEXT: fmulx h0, h0, v1.h[3]441; CHECK-NEXT: ret442entry:443 %extract = extractelement <4 x half> %b, i32 3444 %fmulx.i = tail call half @llvm.aarch64.neon.fmulx.f16(half %a, half %extract)445 ret half %fmulx.i446}447 448define <4 x half> @t_vmulx_lane_f16(<4 x half> %a, <4 x half> %b, i32 %lane) {449; CHECK-LABEL: t_vmulx_lane_f16:450; CHECK: // %bb.0: // %entry451; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1452; CHECK-NEXT: fmulx v0.4h, v0.4h, v1.h[0]453; CHECK-NEXT: ret454entry:455 %shuffle = shufflevector <4 x half> %b, <4 x half> undef, <4 x i32> zeroinitializer456 %vmulx2.i = tail call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> %shuffle) #4457 ret <4 x half> %vmulx2.i458}459 460define <8 x half> @t_vmulxq_lane_f16(<8 x half> %a, <4 x half> %b, i32 %lane) {461; CHECK-LABEL: t_vmulxq_lane_f16:462; CHECK: // %bb.0: // %entry463; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1464; CHECK-NEXT: fmulx v0.8h, v0.8h, v1.h[0]465; CHECK-NEXT: ret466entry:467 %shuffle = shufflevector <4 x half> %b, <4 x half> undef, <8 x i32> zeroinitializer468 %vmulx2.i = tail call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> %a, <8 x half> %shuffle) #4469 ret <8 x half> %vmulx2.i470}471 472define <4 x half> @t_vmulx_laneq_f16(<4 x half> %a, <8 x half> %b, i32 %lane) {473; CHECK-LABEL: t_vmulx_laneq_f16:474; CHECK: // %bb.0: // %entry475; CHECK-NEXT: fmulx v0.4h, v0.4h, v1.h[0]476; CHECK-NEXT: ret477entry:478 %shuffle = shufflevector <8 x half> %b, <8 x half> undef, <4 x i32> zeroinitializer479 %vmulx2.i = tail call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> %shuffle) #4480 ret <4 x half> %vmulx2.i481}482 483define <8 x half> @t_vmulxq_laneq_f16(<8 x half> %a, <8 x half> %b, i32 %lane) {484; CHECK-LABEL: t_vmulxq_laneq_f16:485; CHECK: // %bb.0: // %entry486; CHECK-NEXT: fmulx v0.8h, v0.8h, v1.h[0]487; CHECK-NEXT: ret488entry:489 %shuffle = shufflevector <8 x half> %b, <8 x half> undef, <8 x i32> zeroinitializer490 %vmulx2.i = tail call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> %a, <8 x half> %shuffle) #4491 ret <8 x half> %vmulx2.i492}493 494define half @t_vmulxh_laneq0_f16(half %a, <8 x half> %b) {495; CHECK-LABEL: t_vmulxh_laneq0_f16:496; CHECK: // %bb.0: // %entry497; CHECK-NEXT: fmulx h0, h0, h1498; CHECK-NEXT: ret499entry:500 %extract = extractelement <8 x half> %b, i32 0501 %fmulx.i = tail call half @llvm.aarch64.neon.fmulx.f16(half %a, half %extract)502 ret half %fmulx.i503}504 505define half @t_vmulxh_laneq7_f16(half %a, <8 x half> %b, i32 %lane) {506; CHECK-LABEL: t_vmulxh_laneq7_f16:507; CHECK: // %bb.0: // %entry508; CHECK-NEXT: fmulx h0, h0, v1.h[7]509; CHECK-NEXT: ret510entry:511 %extract = extractelement <8 x half> %b, i32 7512 %fmulx.i = tail call half @llvm.aarch64.neon.fmulx.f16(half %a, half %extract)513 ret half %fmulx.i514}515 516define <4 x half> @t_vmulx_n_f16(<4 x half> %a, half %c) {517; CHECK-LABEL: t_vmulx_n_f16:518; CHECK: // %bb.0: // %entry519; CHECK-NEXT: // kill: def $h1 killed $h1 def $q1520; CHECK-NEXT: dup v1.4h, v1.h[0]521; CHECK-NEXT: fmulx v0.4h, v0.4h, v1.4h522; CHECK-NEXT: ret523entry:524 %vecinit = insertelement <4 x half> undef, half %c, i32 0525 %vecinit3 = shufflevector <4 x half> %vecinit, <4 x half> undef, <4 x i32> zeroinitializer526 %vmulx2.i = tail call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> %a, <4 x half> %vecinit3) #4527 ret <4 x half> %vmulx2.i528}529 530define <8 x half> @t_vmulxq_n_f16(<8 x half> %a, half %c) {531; CHECK-LABEL: t_vmulxq_n_f16:532; CHECK: // %bb.0: // %entry533; CHECK-NEXT: // kill: def $h1 killed $h1 def $q1534; CHECK-NEXT: dup v1.8h, v1.h[0]535; CHECK-NEXT: fmulx v0.8h, v0.8h, v1.8h536; CHECK-NEXT: ret537entry:538 %vecinit = insertelement <8 x half> undef, half %c, i32 0539 %vecinit7 = shufflevector <8 x half> %vecinit, <8 x half> undef, <8 x i32> zeroinitializer540 %vmulx2.i = tail call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> %a, <8 x half> %vecinit7) #4541 ret <8 x half> %vmulx2.i542}543 544define half @t_vfmah_lane3_f16(half %a, half %b, <4 x half> %c) {545; CHECK-LABEL: t_vfmah_lane3_f16:546; CHECK: // %bb.0: // %entry547; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2548; CHECK-NEXT: fmla h0, h1, v2.h[3]549; CHECK-NEXT: ret550entry:551 %extract = extractelement <4 x half> %c, i32 3552 %0 = tail call half @llvm.fma.f16(half %b, half %extract, half %a)553 ret half %0554}555 556define half @t_vfmah_laneq7_f16(half %a, half %b, <8 x half> %c) {557; CHECK-LABEL: t_vfmah_laneq7_f16:558; CHECK: // %bb.0: // %entry559; CHECK-NEXT: fmla h0, h1, v2.h[7]560; CHECK-NEXT: ret561entry:562 %extract = extractelement <8 x half> %c, i32 7563 %0 = tail call half @llvm.fma.f16(half %b, half %extract, half %a)564 ret half %0565}566 567define half @t_vfmsh_lane3_f16(half %a, half %b, <4 x half> %c) {568; CHECK-LABEL: t_vfmsh_lane3_f16:569; CHECK: // %bb.0: // %entry570; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2571; CHECK-NEXT: fmls h0, h1, v2.h[3]572; CHECK-NEXT: ret573entry:574 %0 = fsub half 0xH8000, %b575 %extract = extractelement <4 x half> %c, i32 3576 %1 = tail call half @llvm.fma.f16(half %0, half %extract, half %a)577 ret half %1578}579 580define half @t_vfmsh_laneq7_f16(half %a, half %b, <8 x half> %c) {581; CHECK-LABEL: t_vfmsh_laneq7_f16:582; CHECK: // %bb.0: // %entry583; CHECK-NEXT: fmls h0, h1, v2.h[7]584; CHECK-NEXT: ret585entry:586 %0 = fsub half 0xH8000, %b587 %extract = extractelement <8 x half> %c, i32 7588 %1 = tail call half @llvm.fma.f16(half %0, half %extract, half %a)589 ret half %1590}591 592define half @t_fadd_vfmah_f16(half %a, half %b, <4 x half> %c, <4 x half> %d) {593; CHECK-LABEL: t_fadd_vfmah_f16:594; CHECK: // %bb.0: // %entry595; CHECK-NEXT: fadd v2.4h, v2.4h, v3.4h596; CHECK-NEXT: fmla h0, h1, v2.h[3]597; CHECK-NEXT: ret598entry:599 %0 = fadd <4 x half> %c, %d600 %extract = extractelement <4 x half> %0, i32 3601 %1 = tail call half @llvm.fma.f16(half %b, half %extract, half %a)602 ret half %1603}604 605define half @test_fmulx_horizontal_f16(<2 x half> %v) {606; CHECK-LABEL: test_fmulx_horizontal_f16:607; CHECK: // %bb.0: // %entry608; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0609; CHECK-NEXT: fmulx h0, h0, v0.h[1]610; CHECK-NEXT: ret611entry:612 %0 = extractelement <2 x half> %v, i32 0613 %1 = extractelement <2 x half> %v, i32 1614 %2 = call half @llvm.aarch64.neon.fmulx.f16(half %0, half %1)615 ret half %2616}617