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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 -global-isel=0 -mattr=+v8.2a,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64 -global-isel=1 -mattr=+v8.2a,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5declare i64 @llvm.aarch64.neon.fcvtpu.i64.f16(half)6declare i32 @llvm.aarch64.neon.fcvtpu.i32.f16(half)7declare i64 @llvm.aarch64.neon.fcvtps.i64.f16(half)8declare i32 @llvm.aarch64.neon.fcvtps.i32.f16(half)9declare i64 @llvm.aarch64.neon.fcvtnu.i64.f16(half)10declare i32 @llvm.aarch64.neon.fcvtnu.i32.f16(half)11declare i64 @llvm.aarch64.neon.fcvtns.i64.f16(half)12declare i32 @llvm.aarch64.neon.fcvtns.i32.f16(half)13declare i64 @llvm.aarch64.neon.fcvtmu.i64.f16(half)14declare i32 @llvm.aarch64.neon.fcvtmu.i32.f16(half)15declare i64 @llvm.aarch64.neon.fcvtms.i64.f16(half)16declare i32 @llvm.aarch64.neon.fcvtms.i32.f16(half)17declare i64 @llvm.aarch64.neon.fcvtau.i64.f16(half)18declare i32 @llvm.aarch64.neon.fcvtau.i32.f16(half)19declare i64 @llvm.aarch64.neon.fcvtas.i64.f16(half)20declare i32 @llvm.aarch64.neon.fcvtas.i32.f16(half)21declare i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half)22declare i32 @llvm.aarch64.neon.fcvtzs.i32.f16(half)23declare i64 @llvm.aarch64.neon.fcvtzu.i64.f16(half)24declare i32 @llvm.aarch64.neon.fcvtzu.i32.f16(half)25declare half @llvm.aarch64.neon.frsqrte.f16(half)26declare half @llvm.aarch64.neon.frecpx.f16(half)27declare half @llvm.aarch64.neon.frecpe.f16(half)28 29define dso_local i16 @t2(half %a) {30; CHECK-SD-LABEL: t2:31; CHECK-SD: // %bb.0: // %entry32; CHECK-SD-NEXT: fcmp h0, #0.033; CHECK-SD-NEXT: csetm w0, eq34; CHECK-SD-NEXT: ret35;36; CHECK-GI-LABEL: t2:37; CHECK-GI: // %bb.0: // %entry38; CHECK-GI-NEXT: fcmp h0, #0.039; CHECK-GI-NEXT: cset w8, eq40; CHECK-GI-NEXT: sbfx w0, w8, #0, #141; CHECK-GI-NEXT: ret42entry:43 %0 = fcmp oeq half %a, 0xH000044 %vceqz = sext i1 %0 to i1645 ret i16 %vceqz46}47 48define dso_local i16 @t3(half %a) {49; CHECK-SD-LABEL: t3:50; CHECK-SD: // %bb.0: // %entry51; CHECK-SD-NEXT: fcmp h0, #0.052; CHECK-SD-NEXT: csetm w0, ge53; CHECK-SD-NEXT: ret54;55; CHECK-GI-LABEL: t3:56; CHECK-GI: // %bb.0: // %entry57; CHECK-GI-NEXT: fcmp h0, #0.058; CHECK-GI-NEXT: cset w8, ge59; CHECK-GI-NEXT: sbfx w0, w8, #0, #160; CHECK-GI-NEXT: ret61entry:62 %0 = fcmp oge half %a, 0xH000063 %vcgez = sext i1 %0 to i1664 ret i16 %vcgez65}66 67define dso_local i16 @t4(half %a) {68; CHECK-SD-LABEL: t4:69; CHECK-SD: // %bb.0: // %entry70; CHECK-SD-NEXT: fcmp h0, #0.071; CHECK-SD-NEXT: csetm w0, gt72; CHECK-SD-NEXT: ret73;74; CHECK-GI-LABEL: t4:75; CHECK-GI: // %bb.0: // %entry76; CHECK-GI-NEXT: fcmp h0, #0.077; CHECK-GI-NEXT: cset w8, gt78; CHECK-GI-NEXT: sbfx w0, w8, #0, #179; CHECK-GI-NEXT: ret80entry:81 %0 = fcmp ogt half %a, 0xH000082 %vcgtz = sext i1 %0 to i1683 ret i16 %vcgtz84}85 86define dso_local i16 @t5(half %a) {87; CHECK-SD-LABEL: t5:88; CHECK-SD: // %bb.0: // %entry89; CHECK-SD-NEXT: fcmp h0, #0.090; CHECK-SD-NEXT: csetm w0, ls91; CHECK-SD-NEXT: ret92;93; CHECK-GI-LABEL: t5:94; CHECK-GI: // %bb.0: // %entry95; CHECK-GI-NEXT: fcmp h0, #0.096; CHECK-GI-NEXT: cset w8, ls97; CHECK-GI-NEXT: sbfx w0, w8, #0, #198; CHECK-GI-NEXT: ret99entry:100 %0 = fcmp ole half %a, 0xH0000101 %vclez = sext i1 %0 to i16102 ret i16 %vclez103}104 105define dso_local i16 @t6(half %a) {106; CHECK-SD-LABEL: t6:107; CHECK-SD: // %bb.0: // %entry108; CHECK-SD-NEXT: fcmp h0, #0.0109; CHECK-SD-NEXT: csetm w0, mi110; CHECK-SD-NEXT: ret111;112; CHECK-GI-LABEL: t6:113; CHECK-GI: // %bb.0: // %entry114; CHECK-GI-NEXT: fcmp h0, #0.0115; CHECK-GI-NEXT: cset w8, mi116; CHECK-GI-NEXT: sbfx w0, w8, #0, #1117; CHECK-GI-NEXT: ret118entry:119 %0 = fcmp olt half %a, 0xH0000120 %vcltz = sext i1 %0 to i16121 ret i16 %vcltz122}123 124define dso_local half @t8(i32 %a) {125; CHECK-LABEL: t8:126; CHECK: // %bb.0: // %entry127; CHECK-NEXT: scvtf h0, w0128; CHECK-NEXT: ret129entry:130 %0 = sitofp i32 %a to half131 ret half %0132}133 134define dso_local half @t9(i64 %a) {135; CHECK-LABEL: t9:136; CHECK: // %bb.0: // %entry137; CHECK-NEXT: scvtf h0, x0138; CHECK-NEXT: ret139entry:140 %0 = sitofp i64 %a to half141 ret half %0142}143 144define dso_local half @t12(i64 %a) {145; CHECK-LABEL: t12:146; CHECK: // %bb.0: // %entry147; CHECK-NEXT: ucvtf h0, x0148; CHECK-NEXT: ret149entry:150 %0 = uitofp i64 %a to half151 ret half %0152}153 154define dso_local i16 @t13(half %a) {155; CHECK-LABEL: t13:156; CHECK: // %bb.0: // %entry157; CHECK-NEXT: fcvtzs w0, h0158; CHECK-NEXT: ret159entry:160 %0 = fptosi half %a to i16161 ret i16 %0162}163 164define dso_local i64 @t15(half %a) {165; CHECK-LABEL: t15:166; CHECK: // %bb.0: // %entry167; CHECK-NEXT: fcvtzs x0, h0168; CHECK-NEXT: ret169entry:170 %0 = fptosi half %a to i64171 ret i64 %0172}173 174define dso_local i16 @t16(half %a) {175; CHECK-SD-LABEL: t16:176; CHECK-SD: // %bb.0: // %entry177; CHECK-SD-NEXT: fcvtzs w0, h0178; CHECK-SD-NEXT: ret179;180; CHECK-GI-LABEL: t16:181; CHECK-GI: // %bb.0: // %entry182; CHECK-GI-NEXT: fcvtzu w0, h0183; CHECK-GI-NEXT: ret184entry:185 %0 = fptoui half %a to i16186 ret i16 %0187}188 189define dso_local i64 @t18(half %a) {190; CHECK-LABEL: t18:191; CHECK: // %bb.0: // %entry192; CHECK-NEXT: fcvtzu x0, h0193; CHECK-NEXT: ret194entry:195 %0 = fptoui half %a to i64196 ret i64 %0197}198 199define i32 @fcvtzu_intrinsic_i32(half %a) {200; CHECK-LABEL: fcvtzu_intrinsic_i32:201; CHECK: // %bb.0: // %entry202; CHECK-NEXT: fcvtzu w0, h0203; CHECK-NEXT: ret204entry:205 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtzu.i32.f16(half %a)206 ret i32 %fcvt207}208 209define i64 @fcvtzu_intrinsic_i64(half %a) {210; CHECK-LABEL: fcvtzu_intrinsic_i64:211; CHECK: // %bb.0: // %entry212; CHECK-NEXT: fcvtzs x0, h0213; CHECK-NEXT: ret214entry:215 %fcvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half %a)216 ret i64 %fcvt217}218 219define i32 @fcvtzs_intrinsic_i32(half %a) {220; CHECK-LABEL: fcvtzs_intrinsic_i32:221; CHECK: // %bb.0: // %entry222; CHECK-NEXT: fcvtzs w0, h0223; CHECK-NEXT: ret224entry:225 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f16(half %a)226 ret i32 %fcvt227}228 229define i64 @fcvtzs_intrinsic_i64(half %a) {230; CHECK-LABEL: fcvtzs_intrinsic_i64:231; CHECK: // %bb.0: // %entry232; CHECK-NEXT: fcvtzs x0, h0233; CHECK-NEXT: ret234entry:235 %fcvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half %a)236 ret i64 %fcvt237}238 239define dso_local i16 @t19(half %a) {240; CHECK-LABEL: t19:241; CHECK: // %bb.0: // %entry242; CHECK-NEXT: fcvtas w0, h0243; CHECK-NEXT: ret244entry:245 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtas.i32.f16(half %a)246 %0 = trunc i32 %fcvt to i16247 ret i16 %0248}249 250define dso_local i64 @t21(half %a) {251; CHECK-LABEL: t21:252; CHECK: // %bb.0: // %entry253; CHECK-NEXT: fcvtas x0, h0254; CHECK-NEXT: ret255entry:256 %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtas.i64.f16(half %a)257 ret i64 %vcvtah_s64_f16258}259 260define dso_local i16 @t22(half %a) {261; CHECK-LABEL: t22:262; CHECK: // %bb.0: // %entry263; CHECK-NEXT: fcvtau w0, h0264; CHECK-NEXT: ret265entry:266 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtau.i32.f16(half %a)267 %0 = trunc i32 %fcvt to i16268 ret i16 %0269}270 271define dso_local i64 @t24(half %a) {272; CHECK-LABEL: t24:273; CHECK: // %bb.0: // %entry274; CHECK-NEXT: fcvtau x0, h0275; CHECK-NEXT: ret276entry:277 %vcvtah_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtau.i64.f16(half %a)278 ret i64 %vcvtah_u64_f16279}280 281define dso_local i16 @t25(half %a) {282; CHECK-LABEL: t25:283; CHECK: // %bb.0: // %entry284; CHECK-NEXT: fcvtms w0, h0285; CHECK-NEXT: ret286entry:287 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtms.i32.f16(half %a)288 %0 = trunc i32 %fcvt to i16289 ret i16 %0290}291 292define dso_local i64 @t27(half %a) {293; CHECK-LABEL: t27:294; CHECK: // %bb.0: // %entry295; CHECK-NEXT: fcvtms x0, h0296; CHECK-NEXT: ret297entry:298 %vcvtmh_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtms.i64.f16(half %a)299 ret i64 %vcvtmh_s64_f16300}301 302define dso_local i16 @t28(half %a) {303; CHECK-LABEL: t28:304; CHECK: // %bb.0: // %entry305; CHECK-NEXT: fcvtmu w0, h0306; CHECK-NEXT: ret307entry:308 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtmu.i32.f16(half %a)309 %0 = trunc i32 %fcvt to i16310 ret i16 %0311}312 313define dso_local i64 @t30(half %a) {314; CHECK-LABEL: t30:315; CHECK: // %bb.0: // %entry316; CHECK-NEXT: fcvtmu x0, h0317; CHECK-NEXT: ret318entry:319 %vcvtmh_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtmu.i64.f16(half %a)320 ret i64 %vcvtmh_u64_f16321}322 323define dso_local i16 @t31(half %a) {324; CHECK-LABEL: t31:325; CHECK: // %bb.0: // %entry326; CHECK-NEXT: fcvtns w0, h0327; CHECK-NEXT: ret328entry:329 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtns.i32.f16(half %a)330 %0 = trunc i32 %fcvt to i16331 ret i16 %0332}333 334define dso_local i64 @t33(half %a) {335; CHECK-LABEL: t33:336; CHECK: // %bb.0: // %entry337; CHECK-NEXT: fcvtns x0, h0338; CHECK-NEXT: ret339entry:340 %vcvtnh_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtns.i64.f16(half %a)341 ret i64 %vcvtnh_s64_f16342}343 344define dso_local i16 @t34(half %a) {345; CHECK-LABEL: t34:346; CHECK: // %bb.0: // %entry347; CHECK-NEXT: fcvtnu w0, h0348; CHECK-NEXT: ret349entry:350 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtnu.i32.f16(half %a)351 %0 = trunc i32 %fcvt to i16352 ret i16 %0353}354 355define dso_local i64 @t36(half %a) {356; CHECK-LABEL: t36:357; CHECK: // %bb.0: // %entry358; CHECK-NEXT: fcvtnu x0, h0359; CHECK-NEXT: ret360entry:361 %vcvtnh_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtnu.i64.f16(half %a)362 ret i64 %vcvtnh_u64_f16363}364 365define dso_local i16 @t37(half %a) {366; CHECK-LABEL: t37:367; CHECK: // %bb.0: // %entry368; CHECK-NEXT: fcvtps w0, h0369; CHECK-NEXT: ret370entry:371 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtps.i32.f16(half %a)372 %0 = trunc i32 %fcvt to i16373 ret i16 %0374}375 376define dso_local i64 @t39(half %a) {377; CHECK-LABEL: t39:378; CHECK: // %bb.0: // %entry379; CHECK-NEXT: fcvtps x0, h0380; CHECK-NEXT: ret381entry:382 %vcvtph_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtps.i64.f16(half %a)383 ret i64 %vcvtph_s64_f16384}385 386define dso_local i16 @t40(half %a) {387; CHECK-LABEL: t40:388; CHECK: // %bb.0: // %entry389; CHECK-NEXT: fcvtpu w0, h0390; CHECK-NEXT: ret391entry:392 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtpu.i32.f16(half %a)393 %0 = trunc i32 %fcvt to i16394 ret i16 %0395}396 397define dso_local i64 @t42(half %a) {398; CHECK-LABEL: t42:399; CHECK: // %bb.0: // %entry400; CHECK-NEXT: fcvtpu x0, h0401; CHECK-NEXT: ret402entry:403 %vcvtph_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtpu.i64.f16(half %a)404 ret i64 %vcvtph_u64_f16405}406 407define dso_local half @t44(half %a) {408; CHECK-LABEL: t44:409; CHECK: // %bb.0: // %entry410; CHECK-NEXT: frecpe h0, h0411; CHECK-NEXT: ret412entry:413 %vrecpeh_f16 = tail call half @llvm.aarch64.neon.frecpe.f16(half %a)414 ret half %vrecpeh_f16415}416 417define dso_local half @t45(half %a) {418; CHECK-LABEL: t45:419; CHECK: // %bb.0: // %entry420; CHECK-NEXT: frecpx h0, h0421; CHECK-NEXT: ret422entry:423 %vrecpxh_f16 = tail call half @llvm.aarch64.neon.frecpx.f16(half %a)424 ret half %vrecpxh_f16425}426 427define dso_local half @t53(half %a) {428; CHECK-LABEL: t53:429; CHECK: // %bb.0: // %entry430; CHECK-NEXT: frsqrte h0, h0431; CHECK-NEXT: ret432entry:433 %vrsqrteh_f16 = tail call half @llvm.aarch64.neon.frsqrte.f16(half %a)434 ret half %vrsqrteh_f16435}436