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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 -global-isel=0 -mattr=+v8.2a,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64 -global-isel=1 -mattr=+v8.2a,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5 6declare half @llvm.aarch64.sisd.fabd.f16(half, half)7declare half @llvm.aarch64.neon.fmax.f16(half, half)8declare half @llvm.aarch64.neon.fmin.f16(half, half)9declare half @llvm.aarch64.neon.frsqrts.f16(half, half)10declare half @llvm.aarch64.neon.frecps.f16(half, half)11declare half @llvm.aarch64.neon.fmulx.f16(half, half)12declare half @llvm.fabs.f16(half)13declare i32 @llvm.aarch64.neon.facge.i32.f16(half, half)14declare i32 @llvm.aarch64.neon.facgt.i32.f16(half, half)15 16define dso_local half @t_vabdh_f16(half %a, half %b) {17; CHECK-LABEL: t_vabdh_f16:18; CHECK: // %bb.0: // %entry19; CHECK-NEXT: fabd h0, h0, h120; CHECK-NEXT: ret21entry:22 %vabdh_f16 = tail call half @llvm.aarch64.sisd.fabd.f16(half %a, half %b)23 ret half %vabdh_f1624}25 26define dso_local half @t_vabdh_f16_from_fsub_fabs(half %a, half %b) {27; CHECK-LABEL: t_vabdh_f16_from_fsub_fabs:28; CHECK: // %bb.0: // %entry29; CHECK-NEXT: fabd h0, h0, h130; CHECK-NEXT: ret31entry:32 %sub = fsub half %a, %b33 %abs = tail call half @llvm.fabs.f16(half %sub)34 ret half %abs35}36 37define dso_local i16 @t_vceqh_f16(half %a, half %b) {38; CHECK-SD-LABEL: t_vceqh_f16:39; CHECK-SD: // %bb.0: // %entry40; CHECK-SD-NEXT: fcmp h0, h141; CHECK-SD-NEXT: csetm w0, eq42; CHECK-SD-NEXT: ret43;44; CHECK-GI-LABEL: t_vceqh_f16:45; CHECK-GI: // %bb.0: // %entry46; CHECK-GI-NEXT: fcmp h0, h147; CHECK-GI-NEXT: cset w8, eq48; CHECK-GI-NEXT: sbfx w0, w8, #0, #149; CHECK-GI-NEXT: ret50entry:51 %0 = fcmp oeq half %a, %b52 %vcmpd = sext i1 %0 to i1653 ret i16 %vcmpd54}55 56define dso_local i16 @t_vcgeh_f16(half %a, half %b) {57; CHECK-SD-LABEL: t_vcgeh_f16:58; CHECK-SD: // %bb.0: // %entry59; CHECK-SD-NEXT: fcmp h0, h160; CHECK-SD-NEXT: csetm w0, ge61; CHECK-SD-NEXT: ret62;63; CHECK-GI-LABEL: t_vcgeh_f16:64; CHECK-GI: // %bb.0: // %entry65; CHECK-GI-NEXT: fcmp h0, h166; CHECK-GI-NEXT: cset w8, ge67; CHECK-GI-NEXT: sbfx w0, w8, #0, #168; CHECK-GI-NEXT: ret69entry:70 %0 = fcmp oge half %a, %b71 %vcmpd = sext i1 %0 to i1672 ret i16 %vcmpd73}74 75define dso_local i16 @t_vcgth_f16(half %a, half %b) {76; CHECK-SD-LABEL: t_vcgth_f16:77; CHECK-SD: // %bb.0: // %entry78; CHECK-SD-NEXT: fcmp h0, h179; CHECK-SD-NEXT: csetm w0, gt80; CHECK-SD-NEXT: ret81;82; CHECK-GI-LABEL: t_vcgth_f16:83; CHECK-GI: // %bb.0: // %entry84; CHECK-GI-NEXT: fcmp h0, h185; CHECK-GI-NEXT: cset w8, gt86; CHECK-GI-NEXT: sbfx w0, w8, #0, #187; CHECK-GI-NEXT: ret88entry:89 %0 = fcmp ogt half %a, %b90 %vcmpd = sext i1 %0 to i1691 ret i16 %vcmpd92}93 94define dso_local i16 @t_vcleh_f16(half %a, half %b) {95; CHECK-SD-LABEL: t_vcleh_f16:96; CHECK-SD: // %bb.0: // %entry97; CHECK-SD-NEXT: fcmp h0, h198; CHECK-SD-NEXT: csetm w0, ls99; CHECK-SD-NEXT: ret100;101; CHECK-GI-LABEL: t_vcleh_f16:102; CHECK-GI: // %bb.0: // %entry103; CHECK-GI-NEXT: fcmp h0, h1104; CHECK-GI-NEXT: cset w8, ls105; CHECK-GI-NEXT: sbfx w0, w8, #0, #1106; CHECK-GI-NEXT: ret107entry:108 %0 = fcmp ole half %a, %b109 %vcmpd = sext i1 %0 to i16110 ret i16 %vcmpd111}112 113define dso_local i16 @t_vclth_f16(half %a, half %b) {114; CHECK-SD-LABEL: t_vclth_f16:115; CHECK-SD: // %bb.0: // %entry116; CHECK-SD-NEXT: fcmp h0, h1117; CHECK-SD-NEXT: csetm w0, mi118; CHECK-SD-NEXT: ret119;120; CHECK-GI-LABEL: t_vclth_f16:121; CHECK-GI: // %bb.0: // %entry122; CHECK-GI-NEXT: fcmp h0, h1123; CHECK-GI-NEXT: cset w8, mi124; CHECK-GI-NEXT: sbfx w0, w8, #0, #1125; CHECK-GI-NEXT: ret126entry:127 %0 = fcmp olt half %a, %b128 %vcmpd = sext i1 %0 to i16129 ret i16 %vcmpd130}131 132define dso_local half @t_vmaxh_f16(half %a, half %b) {133; CHECK-LABEL: t_vmaxh_f16:134; CHECK: // %bb.0: // %entry135; CHECK-NEXT: fmax h0, h0, h1136; CHECK-NEXT: ret137entry:138 %vmax = tail call half @llvm.aarch64.neon.fmax.f16(half %a, half %b)139 ret half %vmax140}141 142define dso_local half @t_vminh_f16(half %a, half %b) {143; CHECK-LABEL: t_vminh_f16:144; CHECK: // %bb.0: // %entry145; CHECK-NEXT: fmin h0, h0, h1146; CHECK-NEXT: ret147entry:148 %vmin = tail call half @llvm.aarch64.neon.fmin.f16(half %a, half %b)149 ret half %vmin150}151 152define dso_local half @t_vmulxh_f16(half %a, half %b) {153; CHECK-LABEL: t_vmulxh_f16:154; CHECK: // %bb.0: // %entry155; CHECK-NEXT: fmulx h0, h0, h1156; CHECK-NEXT: ret157entry:158 %vmulxh_f16 = tail call half @llvm.aarch64.neon.fmulx.f16(half %a, half %b)159 ret half %vmulxh_f16160}161 162define dso_local half @t_vrecpsh_f16(half %a, half %b) {163; CHECK-LABEL: t_vrecpsh_f16:164; CHECK: // %bb.0: // %entry165; CHECK-NEXT: frecps h0, h0, h1166; CHECK-NEXT: ret167entry:168 %vrecps = tail call half @llvm.aarch64.neon.frecps.f16(half %a, half %b)169 ret half %vrecps170}171 172define dso_local half @t_vrsqrtsh_f16(half %a, half %b) {173; CHECK-LABEL: t_vrsqrtsh_f16:174; CHECK: // %bb.0: // %entry175; CHECK-NEXT: frsqrts h0, h0, h1176; CHECK-NEXT: ret177entry:178 %vrsqrtsh_f16 = tail call half @llvm.aarch64.neon.frsqrts.f16(half %a, half %b)179 ret half %vrsqrtsh_f16180}181 182declare half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32, i32) #1183declare half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64, i32) #1184declare i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half, i32) #1185declare i64 @llvm.aarch64.neon.vcvtfp2fxs.i64.f16(half, i32) #1186declare half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32, i32) #1187declare i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half, i32) #1188 189define dso_local half @test_vcvth_n_f16_s16_1(i16 %a) {190; CHECK-SD-LABEL: test_vcvth_n_f16_s16_1:191; CHECK-SD: // %bb.0: // %entry192; CHECK-SD-NEXT: fmov s0, w0193; CHECK-SD-NEXT: scvtf h0, h0, #1194; CHECK-SD-NEXT: ret195;196; CHECK-GI-LABEL: test_vcvth_n_f16_s16_1:197; CHECK-GI: // %bb.0: // %entry198; CHECK-GI-NEXT: sxth w8, w0199; CHECK-GI-NEXT: fmov s0, w8200; CHECK-GI-NEXT: scvtf h0, h0, #1201; CHECK-GI-NEXT: ret202entry:203 %sext = sext i16 %a to i32204 %fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %sext, i32 1)205 ret half %fcvth_n206}207 208define dso_local half @test_vcvth_n_f16_s16_16(i16 %a) {209; CHECK-SD-LABEL: test_vcvth_n_f16_s16_16:210; CHECK-SD: // %bb.0: // %entry211; CHECK-SD-NEXT: fmov s0, w0212; CHECK-SD-NEXT: scvtf h0, h0, #16213; CHECK-SD-NEXT: ret214;215; CHECK-GI-LABEL: test_vcvth_n_f16_s16_16:216; CHECK-GI: // %bb.0: // %entry217; CHECK-GI-NEXT: sxth w8, w0218; CHECK-GI-NEXT: fmov s0, w8219; CHECK-GI-NEXT: scvtf h0, h0, #16220; CHECK-GI-NEXT: ret221entry:222 %sext = sext i16 %a to i32223 %fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %sext, i32 16)224 ret half %fcvth_n225}226 227define dso_local half @test_vcvth_n_f16_s32_1(i32 %a) {228; CHECK-LABEL: test_vcvth_n_f16_s32_1:229; CHECK: // %bb.0: // %entry230; CHECK-NEXT: fmov s0, w0231; CHECK-NEXT: scvtf h0, h0, #1232; CHECK-NEXT: ret233entry:234 %vcvth_n_f16_s32 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %a, i32 1)235 ret half %vcvth_n_f16_s32236}237 238define dso_local half @test_vcvth_n_f16_s32_16(i32 %a) {239; CHECK-LABEL: test_vcvth_n_f16_s32_16:240; CHECK: // %bb.0: // %entry241; CHECK-NEXT: fmov s0, w0242; CHECK-NEXT: scvtf h0, h0, #16243; CHECK-NEXT: ret244entry:245 %vcvth_n_f16_s32 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %a, i32 16)246 ret half %vcvth_n_f16_s32247}248 249define dso_local i16 @test_vcvth_n_s16_f16_1(half %a) {250; CHECK-LABEL: test_vcvth_n_s16_f16_1:251; CHECK: // %bb.0: // %entry252; CHECK-NEXT: fcvtzs h0, h0, #1253; CHECK-NEXT: fmov w0, s0254; CHECK-NEXT: ret255entry:256 %fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 1)257 %0 = trunc i32 %fcvth_n to i16258 ret i16 %0259}260 261define dso_local i16 @test_vcvth_n_s16_f16_16(half %a) {262; CHECK-LABEL: test_vcvth_n_s16_f16_16:263; CHECK: // %bb.0: // %entry264; CHECK-NEXT: fcvtzs h0, h0, #16265; CHECK-NEXT: fmov w0, s0266; CHECK-NEXT: ret267entry:268 %fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 16)269 %0 = trunc i32 %fcvth_n to i16270 ret i16 %0271}272 273define dso_local i32 @test_vcvth_n_s32_f16_1(half %a) {274; CHECK-LABEL: test_vcvth_n_s32_f16_1:275; CHECK: // %bb.0: // %entry276; CHECK-NEXT: fcvtzs h0, h0, #1277; CHECK-NEXT: fmov w0, s0278; CHECK-NEXT: ret279entry:280 %vcvth_n_s32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 1)281 ret i32 %vcvth_n_s32_f16282}283 284define dso_local i32 @test_vcvth_n_s32_f16_16(half %a) {285; CHECK-LABEL: test_vcvth_n_s32_f16_16:286; CHECK: // %bb.0: // %entry287; CHECK-NEXT: fcvtzs h0, h0, #16288; CHECK-NEXT: fmov w0, s0289; CHECK-NEXT: ret290entry:291 %vcvth_n_s32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 16)292 ret i32 %vcvth_n_s32_f16293}294 295define dso_local i64 @test_vcvth_n_s64_f16_1(half %a) {296; CHECK-LABEL: test_vcvth_n_s64_f16_1:297; CHECK: // %bb.0: // %entry298; CHECK-NEXT: fcvtzs h0, h0, #1299; CHECK-NEXT: fmov x0, d0300; CHECK-NEXT: ret301entry:302 %vcvth_n_s64_f16 = tail call i64 @llvm.aarch64.neon.vcvtfp2fxs.i64.f16(half %a, i32 1)303 ret i64 %vcvth_n_s64_f16304}305 306define dso_local i64 @test_vcvth_n_s64_f16_32(half %a) {307; CHECK-LABEL: test_vcvth_n_s64_f16_32:308; CHECK: // %bb.0: // %entry309; CHECK-NEXT: fcvtzs h0, h0, #32310; CHECK-NEXT: fmov x0, d0311; CHECK-NEXT: ret312entry:313 %vcvth_n_s64_f16 = tail call i64 @llvm.aarch64.neon.vcvtfp2fxs.i64.f16(half %a, i32 32)314 ret i64 %vcvth_n_s64_f16315}316 317define dso_local half @test_vcvth_n_f16_u16_1(i16 %a) {318; CHECK-SD-LABEL: test_vcvth_n_f16_u16_1:319; CHECK-SD: // %bb.0: // %entry320; CHECK-SD-NEXT: fmov s0, w0321; CHECK-SD-NEXT: ucvtf h0, h0, #1322; CHECK-SD-NEXT: ret323;324; CHECK-GI-LABEL: test_vcvth_n_f16_u16_1:325; CHECK-GI: // %bb.0: // %entry326; CHECK-GI-NEXT: and w8, w0, #0xffff327; CHECK-GI-NEXT: fmov s0, w8328; CHECK-GI-NEXT: ucvtf h0, h0, #1329; CHECK-GI-NEXT: ret330entry:331 %0 = zext i16 %a to i32332 %fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %0, i32 1)333 ret half %fcvth_n334}335 336define dso_local half @test_vcvth_n_f16_u16_16(i16 %a) {337; CHECK-SD-LABEL: test_vcvth_n_f16_u16_16:338; CHECK-SD: // %bb.0: // %entry339; CHECK-SD-NEXT: fmov s0, w0340; CHECK-SD-NEXT: ucvtf h0, h0, #16341; CHECK-SD-NEXT: ret342;343; CHECK-GI-LABEL: test_vcvth_n_f16_u16_16:344; CHECK-GI: // %bb.0: // %entry345; CHECK-GI-NEXT: and w8, w0, #0xffff346; CHECK-GI-NEXT: fmov s0, w8347; CHECK-GI-NEXT: ucvtf h0, h0, #16348; CHECK-GI-NEXT: ret349entry:350 %0 = zext i16 %a to i32351 %fcvth_n = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %0, i32 16)352 ret half %fcvth_n353}354 355define dso_local half @test_vcvth_n_f16_u32_1(i32 %a) {356; CHECK-LABEL: test_vcvth_n_f16_u32_1:357; CHECK: // %bb.0: // %entry358; CHECK-NEXT: fmov s0, w0359; CHECK-NEXT: ucvtf h0, h0, #1360; CHECK-NEXT: ret361entry:362 %vcvth_n_f16_u32 = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %a, i32 1)363 ret half %vcvth_n_f16_u32364}365 366define dso_local half @test_vcvth_n_f16_u32_16(i32 %a) {367; CHECK-LABEL: test_vcvth_n_f16_u32_16:368; CHECK: // %bb.0: // %entry369; CHECK-NEXT: fmov s0, w0370; CHECK-NEXT: ucvtf h0, h0, #16371; CHECK-NEXT: ret372entry:373 %vcvth_n_f16_u32 = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %a, i32 16)374 ret half %vcvth_n_f16_u32375}376 377define dso_local i16 @test_vcvth_n_u16_f16_1(half %a) {378; CHECK-LABEL: test_vcvth_n_u16_f16_1:379; CHECK: // %bb.0: // %entry380; CHECK-NEXT: fcvtzu h0, h0, #1381; CHECK-NEXT: fmov w0, s0382; CHECK-NEXT: ret383entry:384 %fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 1)385 %0 = trunc i32 %fcvth_n to i16386 ret i16 %0387}388 389define dso_local i16 @test_vcvth_n_u16_f16_16(half %a) {390; CHECK-LABEL: test_vcvth_n_u16_f16_16:391; CHECK: // %bb.0: // %entry392; CHECK-NEXT: fcvtzu h0, h0, #16393; CHECK-NEXT: fmov w0, s0394; CHECK-NEXT: ret395entry:396 %fcvth_n = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 16)397 %0 = trunc i32 %fcvth_n to i16398 ret i16 %0399}400 401define dso_local i32 @test_vcvth_n_u32_f16_1(half %a) {402; CHECK-LABEL: test_vcvth_n_u32_f16_1:403; CHECK: // %bb.0: // %entry404; CHECK-NEXT: fcvtzu h0, h0, #1405; CHECK-NEXT: fmov w0, s0406; CHECK-NEXT: ret407entry:408 %vcvth_n_u32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 1)409 ret i32 %vcvth_n_u32_f16410}411 412define dso_local i32 @test_vcvth_n_u32_f16_16(half %a) {413; CHECK-LABEL: test_vcvth_n_u32_f16_16:414; CHECK: // %bb.0: // %entry415; CHECK-NEXT: fcvtzu h0, h0, #16416; CHECK-NEXT: fmov w0, s0417; CHECK-NEXT: ret418entry:419 %vcvth_n_u32_f16 = tail call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 16)420 ret i32 %vcvth_n_u32_f16421}422 423define dso_local i16 @vcageh_f16_test(half %a, half %b) {424; CHECK-LABEL: vcageh_f16_test:425; CHECK: // %bb.0: // %entry426; CHECK-NEXT: facge h0, h0, h1427; CHECK-NEXT: fmov w0, s0428; CHECK-NEXT: ret429entry:430 %facg = tail call i32 @llvm.aarch64.neon.facge.i32.f16(half %a, half %b)431 %0 = trunc i32 %facg to i16432 ret i16 %0433}434 435define dso_local i16 @vcagth_f16_test(half %a, half %b) {436; CHECK-LABEL: vcagth_f16_test:437; CHECK: // %bb.0: // %entry438; CHECK-NEXT: facgt h0, h0, h1439; CHECK-NEXT: fmov w0, s0440; CHECK-NEXT: ret441entry:442 %facg = tail call i32 @llvm.aarch64.neon.facgt.i32.f16(half %a, half %b)443 %0 = trunc i32 %facg to i16444 ret i16 %0445}446 447define dso_local half @vcvth_n_f16_s64_test(i64 %a) {448; CHECK-LABEL: vcvth_n_f16_s64_test:449; CHECK: // %bb.0: // %entry450; CHECK-NEXT: fmov d0, x0451; CHECK-NEXT: scvtf h0, h0, #16452; CHECK-NEXT: ret453entry:454 %vcvth_n_f16_s64 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 16)455 ret half %vcvth_n_f16_s64456}457