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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-linux -mattr=+neon,+fp8fma < %s | FileCheck %s3 4define <8 x half> @test_fmlalb(<8 x half> %d, <16 x i8> %a, <16 x i8> %b) {5; CHECK-LABEL: test_fmlalb:6; CHECK: // %bb.0:7; CHECK-NEXT: fmlalb v0.8h, v1.16b, v2.16b8; CHECK-NEXT: ret9 %r = call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.v8f16(<8 x half> %d, <16 x i8> %a, <16 x i8> %b)10 ret <8 x half> %r11}12 13define <8 x half> @test_fmlalt(<8 x half> %d, <16 x i8> %a, <16 x i8> %b) {14; CHECK-LABEL: test_fmlalt:15; CHECK: // %bb.0:16; CHECK-NEXT: fmlalt v0.8h, v1.16b, v2.16b17; CHECK-NEXT: ret18 %r = call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.v8f16(<8 x half> %d, <16 x i8> %a, <16 x i8> %b)19 ret <8 x half> %r20}21 22define <4 x float> @test_fmlallbb(<4 x float> %d, <16 x i8> %a, <16 x i8> %b) {23; CHECK-LABEL: test_fmlallbb:24; CHECK: // %bb.0:25; CHECK-NEXT: fmlallbb v0.4s, v1.16b, v2.16b26; CHECK-NEXT: ret27 %r = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.v4f32(<4 x float> %d, <16 x i8> %a, <16 x i8> %b)28 ret <4 x float> %r29}30 31define <4 x float> @test_fmlallbt(<4 x float> %d, <16 x i8> %a, <16 x i8> %b) {32; CHECK-LABEL: test_fmlallbt:33; CHECK: // %bb.0:34; CHECK-NEXT: fmlallbt v0.4s, v1.16b, v2.16b35; CHECK-NEXT: ret36 %r = call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.v4f32(<4 x float> %d, <16 x i8> %a, <16 x i8> %b)37 ret <4 x float> %r38}39 40define <4 x float> @test_fmlalltb(<4 x float> %d, <16 x i8> %a, <16 x i8> %b) {41; CHECK-LABEL: test_fmlalltb:42; CHECK: // %bb.0:43; CHECK-NEXT: fmlalltb v0.4s, v1.16b, v2.16b44; CHECK-NEXT: ret45 %r = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.v4f32(<4 x float> %d, <16 x i8> %a, <16 x i8> %b)46 ret <4 x float> %r47}48 49define <4 x float> @test_fmlalltt(<4 x float> %d, <16 x i8> %a, <16 x i8> %b) {50; CHECK-LABEL: test_fmlalltt:51; CHECK: // %bb.0:52; CHECK-NEXT: fmlalltt v0.4s, v1.16b, v2.16b53; CHECK-NEXT: ret54 %r = call <4 x float> @llvm.aarch64.neon.fp8.fmlalltt.v4f32(<4 x float> %d, <16 x i8> %a, <16 x i8> %b)55 ret <4 x float> %r56}57 58define <8 x half> @test_fmlalb_lane(<8 x half> %vd, <16 x i8> %vn, <16 x i8> %vm) {59; CHECK-LABEL: test_fmlalb_lane:60; CHECK: // %bb.0:61; CHECK-NEXT: fmlalb v0.8h, v1.16b, v2.b[0]62; CHECK-NEXT: ret63 %res = tail call <8 x half> @llvm.aarch64.neon.fp8.fmlalb.lane(<8 x half> %vd, <16 x i8> %vn, <16 x i8> %vm, i32 0)64 ret <8 x half> %res65}66 67define <8 x half> @test_fmlalt_lane(<8 x half> %vd, <16 x i8> %vn, <16 x i8> %vm) {68; CHECK-LABEL: test_fmlalt_lane:69; CHECK: // %bb.0:70; CHECK-NEXT: fmlalt v0.8h, v1.16b, v2.b[4]71; CHECK-NEXT: ret72 %res = tail call <8 x half> @llvm.aarch64.neon.fp8.fmlalt.lane(<8 x half> %vd, <16 x i8> %vn, <16 x i8> %vm, i32 4)73 ret <8 x half> %res74}75 76define <4 x float> @test_fmlallbb_lane(<4 x float> %vd, <16 x i8> %vn, <16 x i8> %vm) {77; CHECK-LABEL: test_fmlallbb_lane:78; CHECK: // %bb.0:79; CHECK-NEXT: fmlallbb v0.4s, v1.16b, v2.b[7]80; CHECK-NEXT: ret81 %res = tail call <4 x float> @llvm.aarch64.neon.fp8.fmlallbb.lane(<4 x float> %vd, <16 x i8> %vn, <16 x i8> %vm, i32 7)82 ret <4 x float> %res83}84 85define <4 x float> @test_fmlallbt_lane(<4 x float> %vd, <16 x i8> %vn, <16 x i8> %vm) {86; CHECK-LABEL: test_fmlallbt_lane:87; CHECK: // %bb.0:88; CHECK-NEXT: fmlallbt v0.4s, v1.16b, v2.b[10]89; CHECK-NEXT: ret90 %res = tail call <4 x float> @llvm.aarch64.neon.fp8.fmlallbt.lane(<4 x float> %vd, <16 x i8> %vn, <16 x i8> %vm, i32 10)91 ret <4 x float> %res92}93 94define <4 x float> @test_fmlalltb_lane(<4 x float> %vd, <16 x i8> %vn, <16 x i8> %vm) {95; CHECK-LABEL: test_fmlalltb_lane:96; CHECK: // %bb.0:97; CHECK-NEXT: fmlalltb v0.4s, v1.16b, v2.b[13]98; CHECK-NEXT: ret99 %res = tail call <4 x float> @llvm.aarch64.neon.fp8.fmlalltb.lane(<4 x float> %vd, <16 x i8> %vn, <16 x i8> %vm, i32 13)100 ret <4 x float> %res101}102 103define <4 x float> @test_fmlalltt_lane(<4 x float> %vd, <16 x i8> %vn, <16 x i8> %vm) {104; CHECK-LABEL: test_fmlalltt_lane:105; CHECK: // %bb.0:106; CHECK-NEXT: fmlalltt v0.4s, v1.16b, v2.b[15]107; CHECK-NEXT: ret108 %res = tail call <4 x float> @llvm.aarch64.neon.fp8.fmlalltt.lane(<4 x float> %vd, <16 x i8> %vn, <16 x i8> %vm, i32 15)109 ret <4 x float> %res110}111