80 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mattr=+sve2,+fp8 < %s | FileCheck %s3; RUN: llc -mattr=+sve,+sme2,+fp8 < %s | FileCheck %s4; RUN: llc -mattr=+sme2,+fp8 --force-streaming < %s | FileCheck %s5 6target triple = "aarch64-linux"7 8define <vscale x 8 x bfloat> @cvt1_bf16(<vscale x 16 x i8> %s) {9; CHECK-LABEL: cvt1_bf16:10; CHECK: // %bb.0:11; CHECK-NEXT: bf1cvt z0.h, z0.b12; CHECK-NEXT: ret13 %r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt1.nxv8bf16(<vscale x 16 x i8> %s)14 ret <vscale x 8 x bfloat> %r15}16 17define <vscale x 8 x bfloat> @cvt2_bf16(<vscale x 16 x i8> %s) {18; CHECK-LABEL: cvt2_bf16:19; CHECK: // %bb.0:20; CHECK-NEXT: bf2cvt z0.h, z0.b21; CHECK-NEXT: ret22 %r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvt2.nxv8bf16(<vscale x 16 x i8> %s)23 ret <vscale x 8 x bfloat> %r24}25 26define <vscale x 8 x bfloat> @cvtlt1_bf16(<vscale x 16 x i8> %s) {27; CHECK-LABEL: cvtlt1_bf16:28; CHECK: // %bb.0:29; CHECK-NEXT: bf1cvtlt z0.h, z0.b30; CHECK-NEXT: ret31 %r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt1.nxv8bf16(<vscale x 16 x i8> %s)32 ret <vscale x 8 x bfloat> %r33}34 35define <vscale x 8 x bfloat> @cvtlt2_bf16(<vscale x 16 x i8> %s) {36; CHECK-LABEL: cvtlt2_bf16:37; CHECK: // %bb.0:38; CHECK-NEXT: bf2cvtlt z0.h, z0.b39; CHECK-NEXT: ret40 %r = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fp8.cvtlt2.nxv8bf16(<vscale x 16 x i8> %s)41 ret <vscale x 8 x bfloat> %r42}43 44define <vscale x 8 x half> @cvt1_f16(<vscale x 16 x i8> %s) {45; CHECK-LABEL: cvt1_f16:46; CHECK: // %bb.0:47; CHECK-NEXT: f1cvt z0.h, z0.b48; CHECK-NEXT: ret49 %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt1.nxv8f16(<vscale x 16 x i8> %s)50 ret <vscale x 8 x half> %r51}52 53define <vscale x 8 x half> @cvt2_f16(<vscale x 16 x i8> %s) {54; CHECK-LABEL: cvt2_f16:55; CHECK: // %bb.0:56; CHECK-NEXT: f2cvt z0.h, z0.b57; CHECK-NEXT: ret58 %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvt2.nxv8f16(<vscale x 16 x i8> %s)59 ret <vscale x 8 x half> %r60}61 62 63define <vscale x 8 x half> @cvtlt1_f16(<vscale x 16 x i8> %s) {64; CHECK-LABEL: cvtlt1_f16:65; CHECK: // %bb.0:66; CHECK-NEXT: f1cvtlt z0.h, z0.b67; CHECK-NEXT: ret68 %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt1.nxv8f16(<vscale x 16 x i8> %s)69 ret <vscale x 8 x half> %r70}71 72define <vscale x 8 x half> @cvtlt2_f16(<vscale x 16 x i8> %s) {73; CHECK-LABEL: cvtlt2_f16:74; CHECK: // %bb.0:75; CHECK-NEXT: f2cvtlt z0.h, z0.b76; CHECK-NEXT: ret77 %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8> %s)78 ret <vscale x 8 x half> %r79}80