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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mattr=+sve2,+fp8 < %s | FileCheck %s3; RUN: llc -mattr=+sve,+sme2,+fp8 < %s | FileCheck %s4; RUN: llc -mattr=+sme2,+fp8 --force-streaming < %s | FileCheck %s5 6target triple = "aarch64-linux"7 8define <vscale x 16 x i8> @cvtn_bf16(<vscale x 8 x bfloat> %s1, <vscale x 8 x bfloat> %s2) {9; CHECK-LABEL: cvtn_bf16:10; CHECK: // %bb.0:11; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z112; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z113; CHECK-NEXT: bfcvtn z0.b, { z0.h, z1.h }14; CHECK-NEXT: ret15 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(<vscale x 8 x bfloat> %s1, <vscale x 8 x bfloat> %s2)16 ret <vscale x 16 x i8> %r17}18 19define <vscale x 16 x i8> @cvtn_f16(<vscale x 8 x half> %s1, <vscale x 8 x half> %s2) {20; CHECK-LABEL: cvtn_f16:21; CHECK: // %bb.0:22; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z123; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z124; CHECK-NEXT: fcvtn z0.b, { z0.h, z1.h }25; CHECK-NEXT: ret26 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8f16(<vscale x 8 x half> %s1, <vscale x 8 x half> %s2)27 ret <vscale x 16 x i8> %r28}29 30define <vscale x 16 x i8> @cvtnb_f32(<vscale x 4 x float> %s1, <vscale x 4 x float> %s2) {31; CHECK-LABEL: cvtnb_f32:32; CHECK: // %bb.0:33; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z134; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z135; CHECK-NEXT: fcvtnb z0.b, { z0.s, z1.s }36; CHECK-NEXT: ret37 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(<vscale x 4 x float> %s1, <vscale x 4 x float> %s2)38 ret <vscale x 16 x i8> %r39}40 41define <vscale x 16 x i8> @cvtnt_f32(<vscale x 16 x i8> %d, <vscale x 4 x float> %s1, <vscale x 4 x float> %s2) {42; CHECK-LABEL: cvtnt_f32:43; CHECK: // %bb.0:44; CHECK-NEXT: mov z3.d, z2.d45; CHECK-NEXT: mov z2.d, z1.d46; CHECK-NEXT: fcvtnt z0.b, { z2.s, z3.s }47; CHECK-NEXT: ret48 %r = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(<vscale x 16 x i8> %d, <vscale x 4 x float> %s1, <vscale x 4 x float> %s2)49 ret <vscale x 16 x i8> %r50}51