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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mattr=+sve2,+fp8dot2,+fp8dot4 < %s | FileCheck %s3; RUN: llc -mattr=+sme,+ssve-fp8dot2,+ssve-fp8dot4 --force-streaming < %s | FileCheck %s4 5target triple = "aarch64-linux"6 7define <vscale x 4 x float> @fdot_4way(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {8; CHECK-LABEL: fdot_4way:9; CHECK: // %bb.0:10; CHECK-NEXT: fdot z0.s, z1.b, z2.b11; CHECK-NEXT: ret12 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2)13 ret <vscale x 4 x float> %r14}15 16define <vscale x 8 x half> @fdot_2way(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {17; CHECK-LABEL: fdot_2way:18; CHECK: // %bb.0:19; CHECK-NEXT: fdot z0.h, z1.b, z2.b20; CHECK-NEXT: ret21 %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.nxv8f16(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2)22 ret <vscale x 8 x half> %r23}24 25define <vscale x 4 x float> @fdot_4way_lane(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {26; CHECK-LABEL: fdot_4way_lane:27; CHECK: // %bb.0:28; CHECK-NEXT: fdot z0.s, z1.b, z2.b[3]29; CHECK-NEXT: ret30 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fdot.lane.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2, i32 3)31 ret <vscale x 4 x float> %r32}33 34define <vscale x 8 x half> @fdot_2way_lane(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {35; CHECK-LABEL: fdot_2way_lane:36; CHECK: // %bb.0:37; CHECK-NEXT: fdot z0.h, z1.b, z2.b[5]38; CHECK-NEXT: ret39 %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fdot.lane.nxv8f16(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2, i32 5)40 ret <vscale x 8 x half> %r41}42