115 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mattr=+sve2,+fp8,+fp8fma < %s | FileCheck %s3; RUN: llc -mattr=+sme,+fp8,+ssve-fp8fma --force-streaming < %s | FileCheck %s4 5target triple = "aarch64-linux"6 7define <vscale x 8 x half> @fmla_2way_bot(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {8; CHECK-LABEL: fmla_2way_bot:9; CHECK: // %bb.0:10; CHECK-NEXT: fmlalb z0.h, z1.b, z2.b11; CHECK-NEXT: ret12 %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2)13 ret <vscale x 8 x half> %r14}15 16define <vscale x 8 x half> @fmla_2way_top(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {17; CHECK-LABEL: fmla_2way_top:18; CHECK: // %bb.0:19; CHECK-NEXT: fmlalt z0.h, z1.b, z2.b20; CHECK-NEXT: ret21 %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2)22 ret <vscale x 8 x half> %r23}24 25define <vscale x 8 x half> @fmla_2way_bot_lane(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {26; CHECK-LABEL: fmla_2way_bot_lane:27; CHECK: // %bb.0:28; CHECK-NEXT: fmlalb z0.h, z1.b, z2.b[3]29; CHECK-NEXT: ret30 %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2, i32 3)31 ret <vscale x 8 x half> %r32}33 34define <vscale x 8 x half> @fmla_2way_top_lane(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {35; CHECK-LABEL: fmla_2way_top_lane:36; CHECK: // %bb.0:37; CHECK-NEXT: fmlalt z0.h, z1.b, z2.b[3]38; CHECK-NEXT: ret39 %r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2, i32 3)40 ret <vscale x 8 x half> %r41}42 43define <vscale x 4 x float> @fmla_4way_bb(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {44; CHECK-LABEL: fmla_4way_bb:45; CHECK: // %bb.0:46; CHECK-NEXT: fmlallbb z0.s, z1.b, z2.b47; CHECK-NEXT: ret48 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2)49 ret <vscale x 4 x float> %r50}51 52define <vscale x 4 x float> @fmla_4way_bt(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {53; CHECK-LABEL: fmla_4way_bt:54; CHECK: // %bb.0:55; CHECK-NEXT: fmlallbt z0.s, z1.b, z2.b56; CHECK-NEXT: ret57 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbt.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2)58 ret <vscale x 4 x float> %r59}60 61define <vscale x 4 x float> @fmla_4way_tb(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {62; CHECK-LABEL: fmla_4way_tb:63; CHECK: // %bb.0:64; CHECK-NEXT: fmlalltb z0.s, z1.b, z2.b65; CHECK-NEXT: ret66 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlalltb.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2)67 ret <vscale x 4 x float> %r68}69 70define <vscale x 4 x float> @fmla_4way_tt(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {71; CHECK-LABEL: fmla_4way_tt:72; CHECK: // %bb.0:73; CHECK-NEXT: fmlalltt z0.s, z1.b, z2.b74; CHECK-NEXT: ret75 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlalltt.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2)76 ret <vscale x 4 x float> %r77}78 79define <vscale x 4 x float> @fmla_4way_bb_lane(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {80; CHECK-LABEL: fmla_4way_bb_lane:81; CHECK: // %bb.0:82; CHECK-NEXT: fmlallbb z0.s, z1.b, z2.b[3]83; CHECK-NEXT: ret84 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbb.lane.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2, i32 3)85 ret <vscale x 4 x float> %r86}87 88define <vscale x 4 x float> @fmla_4way_bt_lane(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {89; CHECK-LABEL: fmla_4way_bt_lane:90; CHECK: // %bb.0:91; CHECK-NEXT: fmlallbt z0.s, z1.b, z2.b[3]92; CHECK-NEXT: ret93 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbt.lane.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2, i32 3)94 ret <vscale x 4 x float> %r95}96 97define <vscale x 4 x float> @fmla_4way_tb_lane(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {98; CHECK-LABEL: fmla_4way_tb_lane:99; CHECK: // %bb.0:100; CHECK-NEXT: fmlalltb z0.s, z1.b, z2.b[3]101; CHECK-NEXT: ret102 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlalltb.lane.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2, i32 3)103 ret <vscale x 4 x float> %r104}105 106define <vscale x 4 x float> @fmla_4way_tt_lane(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {107; CHECK-LABEL: fmla_4way_tt_lane:108; CHECK: // %bb.0:109; CHECK-NEXT: fmlalltt z0.s, z1.b, z2.b[3]110; CHECK-NEXT: ret111 %r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlalltt.lane.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2, i32 3)112 ret <vscale x 4 x float> %r113}114 115