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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT3; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP164 5; i32 saturate6 7define i32 @stest_f64i32(double %x) {8; CHECK-LABEL: stest_f64i32:9; CHECK: // %bb.0: // %entry10; CHECK-NEXT: fcvtzs w0, d011; CHECK-NEXT: ret12entry:13 %conv = fptosi double %x to i6414 %0 = icmp slt i64 %conv, 214748364715 %spec.store.select = select i1 %0, i64 %conv, i64 214748364716 %1 = icmp sgt i64 %spec.store.select, -214748364817 %spec.store.select7 = select i1 %1, i64 %spec.store.select, i64 -214748364818 %conv6 = trunc i64 %spec.store.select7 to i3219 ret i32 %conv620}21 22define i32 @utest_f64i32(double %x) {23; CHECK-LABEL: utest_f64i32:24; CHECK: // %bb.0: // %entry25; CHECK-NEXT: fcvtzu w0, d026; CHECK-NEXT: ret27entry:28 %conv = fptoui double %x to i6429 %0 = icmp ult i64 %conv, 429496729530 %spec.store.select = select i1 %0, i64 %conv, i64 429496729531 %conv6 = trunc i64 %spec.store.select to i3232 ret i32 %conv633}34 35define i32 @ustest_f64i32(double %x) {36; CHECK-LABEL: ustest_f64i32:37; CHECK: // %bb.0: // %entry38; CHECK-NEXT: fcvtzu w0, d039; CHECK-NEXT: ret40entry:41 %conv = fptosi double %x to i6442 %0 = icmp slt i64 %conv, 429496729543 %spec.store.select = select i1 %0, i64 %conv, i64 429496729544 %1 = icmp sgt i64 %spec.store.select, 045 %spec.store.select7 = select i1 %1, i64 %spec.store.select, i64 046 %conv6 = trunc i64 %spec.store.select7 to i3247 ret i32 %conv648}49 50define i32 @stest_f32i32(float %x) {51; CHECK-LABEL: stest_f32i32:52; CHECK: // %bb.0: // %entry53; CHECK-NEXT: fcvtzs w0, s054; CHECK-NEXT: ret55entry:56 %conv = fptosi float %x to i6457 %0 = icmp slt i64 %conv, 214748364758 %spec.store.select = select i1 %0, i64 %conv, i64 214748364759 %1 = icmp sgt i64 %spec.store.select, -214748364860 %spec.store.select7 = select i1 %1, i64 %spec.store.select, i64 -214748364861 %conv6 = trunc i64 %spec.store.select7 to i3262 ret i32 %conv663}64 65define i32 @utest_f32i32(float %x) {66; CHECK-LABEL: utest_f32i32:67; CHECK: // %bb.0: // %entry68; CHECK-NEXT: fcvtzu w0, s069; CHECK-NEXT: ret70entry:71 %conv = fptoui float %x to i6472 %0 = icmp ult i64 %conv, 429496729573 %spec.store.select = select i1 %0, i64 %conv, i64 429496729574 %conv6 = trunc i64 %spec.store.select to i3275 ret i32 %conv676}77 78define i32 @ustest_f32i32(float %x) {79; CHECK-LABEL: ustest_f32i32:80; CHECK: // %bb.0: // %entry81; CHECK-NEXT: fcvtzu w0, s082; CHECK-NEXT: ret83entry:84 %conv = fptosi float %x to i6485 %0 = icmp slt i64 %conv, 429496729586 %spec.store.select = select i1 %0, i64 %conv, i64 429496729587 %1 = icmp sgt i64 %spec.store.select, 088 %spec.store.select7 = select i1 %1, i64 %spec.store.select, i64 089 %conv6 = trunc i64 %spec.store.select7 to i3290 ret i32 %conv691}92 93define i32 @stest_f16i32(half %x) {94; CHECK-CVT-LABEL: stest_f16i32:95; CHECK-CVT: // %bb.0: // %entry96; CHECK-CVT-NEXT: fcvt s0, h097; CHECK-CVT-NEXT: fcvtzs w0, s098; CHECK-CVT-NEXT: ret99;100; CHECK-FP16-LABEL: stest_f16i32:101; CHECK-FP16: // %bb.0: // %entry102; CHECK-FP16-NEXT: fcvtzs w0, h0103; CHECK-FP16-NEXT: ret104entry:105 %conv = fptosi half %x to i64106 %0 = icmp slt i64 %conv, 2147483647107 %spec.store.select = select i1 %0, i64 %conv, i64 2147483647108 %1 = icmp sgt i64 %spec.store.select, -2147483648109 %spec.store.select7 = select i1 %1, i64 %spec.store.select, i64 -2147483648110 %conv6 = trunc i64 %spec.store.select7 to i32111 ret i32 %conv6112}113 114define i32 @utest_f16i32(half %x) {115; CHECK-CVT-LABEL: utest_f16i32:116; CHECK-CVT: // %bb.0: // %entry117; CHECK-CVT-NEXT: fcvt s0, h0118; CHECK-CVT-NEXT: fcvtzu w0, s0119; CHECK-CVT-NEXT: ret120;121; CHECK-FP16-LABEL: utest_f16i32:122; CHECK-FP16: // %bb.0: // %entry123; CHECK-FP16-NEXT: fcvtzu w0, h0124; CHECK-FP16-NEXT: ret125entry:126 %conv = fptoui half %x to i64127 %0 = icmp ult i64 %conv, 4294967295128 %spec.store.select = select i1 %0, i64 %conv, i64 4294967295129 %conv6 = trunc i64 %spec.store.select to i32130 ret i32 %conv6131}132 133define i32 @ustest_f16i32(half %x) {134; CHECK-CVT-LABEL: ustest_f16i32:135; CHECK-CVT: // %bb.0: // %entry136; CHECK-CVT-NEXT: fcvt s0, h0137; CHECK-CVT-NEXT: fcvtzu w0, s0138; CHECK-CVT-NEXT: ret139;140; CHECK-FP16-LABEL: ustest_f16i32:141; CHECK-FP16: // %bb.0: // %entry142; CHECK-FP16-NEXT: fcvtzu w0, h0143; CHECK-FP16-NEXT: ret144entry:145 %conv = fptosi half %x to i64146 %0 = icmp slt i64 %conv, 4294967295147 %spec.store.select = select i1 %0, i64 %conv, i64 4294967295148 %1 = icmp sgt i64 %spec.store.select, 0149 %spec.store.select7 = select i1 %1, i64 %spec.store.select, i64 0150 %conv6 = trunc i64 %spec.store.select7 to i32151 ret i32 %conv6152}153 154; i16 saturate155 156define i16 @stest_f64i16(double %x) {157; CHECK-LABEL: stest_f64i16:158; CHECK: // %bb.0: // %entry159; CHECK-NEXT: fcvtzs w8, d0160; CHECK-NEXT: mov w9, #32767 // =0x7fff161; CHECK-NEXT: cmp w8, w9162; CHECK-NEXT: csel w8, w8, w9, lt163; CHECK-NEXT: mov w9, #-32768 // =0xffff8000164; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768165; CHECK-NEXT: csel w0, w8, w9, gt166; CHECK-NEXT: ret167entry:168 %conv = fptosi double %x to i32169 %0 = icmp slt i32 %conv, 32767170 %spec.store.select = select i1 %0, i32 %conv, i32 32767171 %1 = icmp sgt i32 %spec.store.select, -32768172 %spec.store.select7 = select i1 %1, i32 %spec.store.select, i32 -32768173 %conv6 = trunc i32 %spec.store.select7 to i16174 ret i16 %conv6175}176 177define i16 @utest_f64i16(double %x) {178; CHECK-LABEL: utest_f64i16:179; CHECK: // %bb.0: // %entry180; CHECK-NEXT: fcvtzu w8, d0181; CHECK-NEXT: mov w9, #65535 // =0xffff182; CHECK-NEXT: cmp w8, w9183; CHECK-NEXT: csel w0, w8, w9, lo184; CHECK-NEXT: ret185entry:186 %conv = fptoui double %x to i32187 %0 = icmp ult i32 %conv, 65535188 %spec.store.select = select i1 %0, i32 %conv, i32 65535189 %conv6 = trunc i32 %spec.store.select to i16190 ret i16 %conv6191}192 193define i16 @ustest_f64i16(double %x) {194; CHECK-LABEL: ustest_f64i16:195; CHECK: // %bb.0: // %entry196; CHECK-NEXT: fcvtzs w8, d0197; CHECK-NEXT: mov w9, #65535 // =0xffff198; CHECK-NEXT: cmp w8, w9199; CHECK-NEXT: csel w8, w8, w9, lt200; CHECK-NEXT: bic w0, w8, w8, asr #31201; CHECK-NEXT: ret202entry:203 %conv = fptosi double %x to i32204 %0 = icmp slt i32 %conv, 65535205 %spec.store.select = select i1 %0, i32 %conv, i32 65535206 %1 = icmp sgt i32 %spec.store.select, 0207 %spec.store.select7 = select i1 %1, i32 %spec.store.select, i32 0208 %conv6 = trunc i32 %spec.store.select7 to i16209 ret i16 %conv6210}211 212define i16 @stest_f32i16(float %x) {213; CHECK-LABEL: stest_f32i16:214; CHECK: // %bb.0: // %entry215; CHECK-NEXT: fcvtzs w8, s0216; CHECK-NEXT: mov w9, #32767 // =0x7fff217; CHECK-NEXT: cmp w8, w9218; CHECK-NEXT: csel w8, w8, w9, lt219; CHECK-NEXT: mov w9, #-32768 // =0xffff8000220; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768221; CHECK-NEXT: csel w0, w8, w9, gt222; CHECK-NEXT: ret223entry:224 %conv = fptosi float %x to i32225 %0 = icmp slt i32 %conv, 32767226 %spec.store.select = select i1 %0, i32 %conv, i32 32767227 %1 = icmp sgt i32 %spec.store.select, -32768228 %spec.store.select7 = select i1 %1, i32 %spec.store.select, i32 -32768229 %conv6 = trunc i32 %spec.store.select7 to i16230 ret i16 %conv6231}232 233define i16 @utest_f32i16(float %x) {234; CHECK-LABEL: utest_f32i16:235; CHECK: // %bb.0: // %entry236; CHECK-NEXT: fcvtzu w8, s0237; CHECK-NEXT: mov w9, #65535 // =0xffff238; CHECK-NEXT: cmp w8, w9239; CHECK-NEXT: csel w0, w8, w9, lo240; CHECK-NEXT: ret241entry:242 %conv = fptoui float %x to i32243 %0 = icmp ult i32 %conv, 65535244 %spec.store.select = select i1 %0, i32 %conv, i32 65535245 %conv6 = trunc i32 %spec.store.select to i16246 ret i16 %conv6247}248 249define i16 @ustest_f32i16(float %x) {250; CHECK-LABEL: ustest_f32i16:251; CHECK: // %bb.0: // %entry252; CHECK-NEXT: fcvtzs w8, s0253; CHECK-NEXT: mov w9, #65535 // =0xffff254; CHECK-NEXT: cmp w8, w9255; CHECK-NEXT: csel w8, w8, w9, lt256; CHECK-NEXT: bic w0, w8, w8, asr #31257; CHECK-NEXT: ret258entry:259 %conv = fptosi float %x to i32260 %0 = icmp slt i32 %conv, 65535261 %spec.store.select = select i1 %0, i32 %conv, i32 65535262 %1 = icmp sgt i32 %spec.store.select, 0263 %spec.store.select7 = select i1 %1, i32 %spec.store.select, i32 0264 %conv6 = trunc i32 %spec.store.select7 to i16265 ret i16 %conv6266}267 268define i16 @stest_f16i16(half %x) {269; CHECK-CVT-LABEL: stest_f16i16:270; CHECK-CVT: // %bb.0: // %entry271; CHECK-CVT-NEXT: fcvt s0, h0272; CHECK-CVT-NEXT: mov w9, #32767 // =0x7fff273; CHECK-CVT-NEXT: fcvtzs w8, s0274; CHECK-CVT-NEXT: cmp w8, w9275; CHECK-CVT-NEXT: csel w8, w8, w9, lt276; CHECK-CVT-NEXT: mov w9, #-32768 // =0xffff8000277; CHECK-CVT-NEXT: cmn w8, #8, lsl #12 // =32768278; CHECK-CVT-NEXT: csel w0, w8, w9, gt279; CHECK-CVT-NEXT: ret280;281; CHECK-FP16-LABEL: stest_f16i16:282; CHECK-FP16: // %bb.0: // %entry283; CHECK-FP16-NEXT: fcvtzs w8, h0284; CHECK-FP16-NEXT: mov w9, #32767 // =0x7fff285; CHECK-FP16-NEXT: cmp w8, w9286; CHECK-FP16-NEXT: csel w8, w8, w9, lt287; CHECK-FP16-NEXT: mov w9, #-32768 // =0xffff8000288; CHECK-FP16-NEXT: cmn w8, #8, lsl #12 // =32768289; CHECK-FP16-NEXT: csel w0, w8, w9, gt290; CHECK-FP16-NEXT: ret291entry:292 %conv = fptosi half %x to i32293 %0 = icmp slt i32 %conv, 32767294 %spec.store.select = select i1 %0, i32 %conv, i32 32767295 %1 = icmp sgt i32 %spec.store.select, -32768296 %spec.store.select7 = select i1 %1, i32 %spec.store.select, i32 -32768297 %conv6 = trunc i32 %spec.store.select7 to i16298 ret i16 %conv6299}300 301define i16 @utest_f16i16(half %x) {302; CHECK-CVT-LABEL: utest_f16i16:303; CHECK-CVT: // %bb.0: // %entry304; CHECK-CVT-NEXT: fcvt s0, h0305; CHECK-CVT-NEXT: mov w9, #65535 // =0xffff306; CHECK-CVT-NEXT: fcvtzu w8, s0307; CHECK-CVT-NEXT: cmp w8, w9308; CHECK-CVT-NEXT: csel w0, w8, w9, lo309; CHECK-CVT-NEXT: ret310;311; CHECK-FP16-LABEL: utest_f16i16:312; CHECK-FP16: // %bb.0: // %entry313; CHECK-FP16-NEXT: fcvtzu w8, h0314; CHECK-FP16-NEXT: mov w9, #65535 // =0xffff315; CHECK-FP16-NEXT: cmp w8, w9316; CHECK-FP16-NEXT: csel w0, w8, w9, lo317; CHECK-FP16-NEXT: ret318entry:319 %conv = fptoui half %x to i32320 %0 = icmp ult i32 %conv, 65535321 %spec.store.select = select i1 %0, i32 %conv, i32 65535322 %conv6 = trunc i32 %spec.store.select to i16323 ret i16 %conv6324}325 326define i16 @ustest_f16i16(half %x) {327; CHECK-CVT-LABEL: ustest_f16i16:328; CHECK-CVT: // %bb.0: // %entry329; CHECK-CVT-NEXT: fcvt s0, h0330; CHECK-CVT-NEXT: mov w9, #65535 // =0xffff331; CHECK-CVT-NEXT: fcvtzs w8, s0332; CHECK-CVT-NEXT: cmp w8, w9333; CHECK-CVT-NEXT: csel w8, w8, w9, lt334; CHECK-CVT-NEXT: bic w0, w8, w8, asr #31335; CHECK-CVT-NEXT: ret336;337; CHECK-FP16-LABEL: ustest_f16i16:338; CHECK-FP16: // %bb.0: // %entry339; CHECK-FP16-NEXT: fcvtzs w8, h0340; CHECK-FP16-NEXT: mov w9, #65535 // =0xffff341; CHECK-FP16-NEXT: cmp w8, w9342; CHECK-FP16-NEXT: csel w8, w8, w9, lt343; CHECK-FP16-NEXT: bic w0, w8, w8, asr #31344; CHECK-FP16-NEXT: ret345entry:346 %conv = fptosi half %x to i32347 %0 = icmp slt i32 %conv, 65535348 %spec.store.select = select i1 %0, i32 %conv, i32 65535349 %1 = icmp sgt i32 %spec.store.select, 0350 %spec.store.select7 = select i1 %1, i32 %spec.store.select, i32 0351 %conv6 = trunc i32 %spec.store.select7 to i16352 ret i16 %conv6353}354 355; i64 saturate356 357define i64 @stest_f64i64(double %x) {358; CHECK-LABEL: stest_f64i64:359; CHECK: // %bb.0: // %entry360; CHECK-NEXT: fcvtzs x0, d0361; CHECK-NEXT: ret362entry:363 %conv = fptosi double %x to i128364 %0 = icmp slt i128 %conv, 9223372036854775807365 %spec.store.select = select i1 %0, i128 %conv, i128 9223372036854775807366 %1 = icmp sgt i128 %spec.store.select, -9223372036854775808367 %spec.store.select7 = select i1 %1, i128 %spec.store.select, i128 -9223372036854775808368 %conv6 = trunc i128 %spec.store.select7 to i64369 ret i64 %conv6370}371 372define i64 @utest_f64i64(double %x) {373; CHECK-LABEL: utest_f64i64:374; CHECK: // %bb.0: // %entry375; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill376; CHECK-NEXT: .cfi_def_cfa_offset 16377; CHECK-NEXT: .cfi_offset w30, -16378; CHECK-NEXT: bl __fixunsdfti379; CHECK-NEXT: cmp x1, #0380; CHECK-NEXT: csel x0, x0, xzr, eq381; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload382; CHECK-NEXT: ret383entry:384 %conv = fptoui double %x to i128385 %0 = icmp ult i128 %conv, 18446744073709551616386 %spec.store.select = select i1 %0, i128 %conv, i128 18446744073709551616387 %conv6 = trunc i128 %spec.store.select to i64388 ret i64 %conv6389}390 391define i64 @ustest_f64i64(double %x) {392; CHECK-LABEL: ustest_f64i64:393; CHECK: // %bb.0: // %entry394; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill395; CHECK-NEXT: .cfi_def_cfa_offset 16396; CHECK-NEXT: .cfi_offset w30, -16397; CHECK-NEXT: bl __fixdfti398; CHECK-NEXT: cmp x1, #1399; CHECK-NEXT: csel x8, x0, xzr, lt400; CHECK-NEXT: csinc x9, x1, xzr, lt401; CHECK-NEXT: cmp xzr, x8402; CHECK-NEXT: ngcs xzr, x9403; CHECK-NEXT: csel x0, x8, xzr, lt404; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload405; CHECK-NEXT: ret406entry:407 %conv = fptosi double %x to i128408 %0 = icmp slt i128 %conv, 18446744073709551616409 %spec.store.select = select i1 %0, i128 %conv, i128 18446744073709551616410 %1 = icmp sgt i128 %spec.store.select, 0411 %spec.store.select7 = select i1 %1, i128 %spec.store.select, i128 0412 %conv6 = trunc i128 %spec.store.select7 to i64413 ret i64 %conv6414}415 416define i64 @stest_f32i64(float %x) {417; CHECK-LABEL: stest_f32i64:418; CHECK: // %bb.0: // %entry419; CHECK-NEXT: fcvtzs x0, s0420; CHECK-NEXT: ret421entry:422 %conv = fptosi float %x to i128423 %0 = icmp slt i128 %conv, 9223372036854775807424 %spec.store.select = select i1 %0, i128 %conv, i128 9223372036854775807425 %1 = icmp sgt i128 %spec.store.select, -9223372036854775808426 %spec.store.select7 = select i1 %1, i128 %spec.store.select, i128 -9223372036854775808427 %conv6 = trunc i128 %spec.store.select7 to i64428 ret i64 %conv6429}430 431define i64 @utest_f32i64(float %x) {432; CHECK-LABEL: utest_f32i64:433; CHECK: // %bb.0: // %entry434; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill435; CHECK-NEXT: .cfi_def_cfa_offset 16436; CHECK-NEXT: .cfi_offset w30, -16437; CHECK-NEXT: bl __fixunssfti438; CHECK-NEXT: cmp x1, #0439; CHECK-NEXT: csel x0, x0, xzr, eq440; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload441; CHECK-NEXT: ret442entry:443 %conv = fptoui float %x to i128444 %0 = icmp ult i128 %conv, 18446744073709551616445 %spec.store.select = select i1 %0, i128 %conv, i128 18446744073709551616446 %conv6 = trunc i128 %spec.store.select to i64447 ret i64 %conv6448}449 450define i64 @ustest_f32i64(float %x) {451; CHECK-LABEL: ustest_f32i64:452; CHECK: // %bb.0: // %entry453; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill454; CHECK-NEXT: .cfi_def_cfa_offset 16455; CHECK-NEXT: .cfi_offset w30, -16456; CHECK-NEXT: bl __fixsfti457; CHECK-NEXT: cmp x1, #1458; CHECK-NEXT: csel x8, x0, xzr, lt459; CHECK-NEXT: csinc x9, x1, xzr, lt460; CHECK-NEXT: cmp xzr, x8461; CHECK-NEXT: ngcs xzr, x9462; CHECK-NEXT: csel x0, x8, xzr, lt463; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload464; CHECK-NEXT: ret465entry:466 %conv = fptosi float %x to i128467 %0 = icmp slt i128 %conv, 18446744073709551616468 %spec.store.select = select i1 %0, i128 %conv, i128 18446744073709551616469 %1 = icmp sgt i128 %spec.store.select, 0470 %spec.store.select7 = select i1 %1, i128 %spec.store.select, i128 0471 %conv6 = trunc i128 %spec.store.select7 to i64472 ret i64 %conv6473}474 475define i64 @stest_f16i64(half %x) {476; CHECK-CVT-LABEL: stest_f16i64:477; CHECK-CVT: // %bb.0: // %entry478; CHECK-CVT-NEXT: fcvt s0, h0479; CHECK-CVT-NEXT: fcvtzs x0, s0480; CHECK-CVT-NEXT: ret481;482; CHECK-FP16-LABEL: stest_f16i64:483; CHECK-FP16: // %bb.0: // %entry484; CHECK-FP16-NEXT: fcvtzs x0, h0485; CHECK-FP16-NEXT: ret486entry:487 %conv = fptosi half %x to i128488 %0 = icmp slt i128 %conv, 9223372036854775807489 %spec.store.select = select i1 %0, i128 %conv, i128 9223372036854775807490 %1 = icmp sgt i128 %spec.store.select, -9223372036854775808491 %spec.store.select7 = select i1 %1, i128 %spec.store.select, i128 -9223372036854775808492 %conv6 = trunc i128 %spec.store.select7 to i64493 ret i64 %conv6494}495 496define i64 @utest_f16i64(half %x) {497; CHECK-LABEL: utest_f16i64:498; CHECK: // %bb.0: // %entry499; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill500; CHECK-NEXT: .cfi_def_cfa_offset 16501; CHECK-NEXT: .cfi_offset w30, -16502; CHECK-NEXT: bl __fixunshfti503; CHECK-NEXT: cmp x1, #0504; CHECK-NEXT: csel x0, x0, xzr, eq505; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload506; CHECK-NEXT: ret507entry:508 %conv = fptoui half %x to i128509 %0 = icmp ult i128 %conv, 18446744073709551616510 %spec.store.select = select i1 %0, i128 %conv, i128 18446744073709551616511 %conv6 = trunc i128 %spec.store.select to i64512 ret i64 %conv6513}514 515define i64 @ustest_f16i64(half %x) {516; CHECK-LABEL: ustest_f16i64:517; CHECK: // %bb.0: // %entry518; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill519; CHECK-NEXT: .cfi_def_cfa_offset 16520; CHECK-NEXT: .cfi_offset w30, -16521; CHECK-NEXT: bl __fixhfti522; CHECK-NEXT: cmp x1, #1523; CHECK-NEXT: csel x8, x0, xzr, lt524; CHECK-NEXT: csinc x9, x1, xzr, lt525; CHECK-NEXT: cmp xzr, x8526; CHECK-NEXT: ngcs xzr, x9527; CHECK-NEXT: csel x0, x8, xzr, lt528; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload529; CHECK-NEXT: ret530entry:531 %conv = fptosi half %x to i128532 %0 = icmp slt i128 %conv, 18446744073709551616533 %spec.store.select = select i1 %0, i128 %conv, i128 18446744073709551616534 %1 = icmp sgt i128 %spec.store.select, 0535 %spec.store.select7 = select i1 %1, i128 %spec.store.select, i128 0536 %conv6 = trunc i128 %spec.store.select7 to i64537 ret i64 %conv6538}539 540 541 542; i32 saturate543 544define i32 @stest_f64i32_mm(double %x) {545; CHECK-LABEL: stest_f64i32_mm:546; CHECK: // %bb.0: // %entry547; CHECK-NEXT: fcvtzs w0, d0548; CHECK-NEXT: ret549entry:550 %conv = fptosi double %x to i64551 %spec.store.select = call i64 @llvm.smin.i64(i64 %conv, i64 2147483647)552 %spec.store.select7 = call i64 @llvm.smax.i64(i64 %spec.store.select, i64 -2147483648)553 %conv6 = trunc i64 %spec.store.select7 to i32554 ret i32 %conv6555}556 557define i32 @utest_f64i32_mm(double %x) {558; CHECK-LABEL: utest_f64i32_mm:559; CHECK: // %bb.0: // %entry560; CHECK-NEXT: fcvtzu w0, d0561; CHECK-NEXT: ret562entry:563 %conv = fptoui double %x to i64564 %spec.store.select = call i64 @llvm.umin.i64(i64 %conv, i64 4294967295)565 %conv6 = trunc i64 %spec.store.select to i32566 ret i32 %conv6567}568 569define i32 @ustest_f64i32_mm(double %x) {570; CHECK-LABEL: ustest_f64i32_mm:571; CHECK: // %bb.0: // %entry572; CHECK-NEXT: fcvtzu w0, d0573; CHECK-NEXT: ret574entry:575 %conv = fptosi double %x to i64576 %spec.store.select = call i64 @llvm.smin.i64(i64 %conv, i64 4294967295)577 %spec.store.select7 = call i64 @llvm.smax.i64(i64 %spec.store.select, i64 0)578 %conv6 = trunc i64 %spec.store.select7 to i32579 ret i32 %conv6580}581 582define i32 @stest_f32i32_mm(float %x) {583; CHECK-LABEL: stest_f32i32_mm:584; CHECK: // %bb.0: // %entry585; CHECK-NEXT: fcvtzs w0, s0586; CHECK-NEXT: ret587entry:588 %conv = fptosi float %x to i64589 %spec.store.select = call i64 @llvm.smin.i64(i64 %conv, i64 2147483647)590 %spec.store.select7 = call i64 @llvm.smax.i64(i64 %spec.store.select, i64 -2147483648)591 %conv6 = trunc i64 %spec.store.select7 to i32592 ret i32 %conv6593}594 595define i32 @utest_f32i32_mm(float %x) {596; CHECK-LABEL: utest_f32i32_mm:597; CHECK: // %bb.0: // %entry598; CHECK-NEXT: fcvtzu w0, s0599; CHECK-NEXT: ret600entry:601 %conv = fptoui float %x to i64602 %spec.store.select = call i64 @llvm.umin.i64(i64 %conv, i64 4294967295)603 %conv6 = trunc i64 %spec.store.select to i32604 ret i32 %conv6605}606 607define i32 @ustest_f32i32_mm(float %x) {608; CHECK-LABEL: ustest_f32i32_mm:609; CHECK: // %bb.0: // %entry610; CHECK-NEXT: fcvtzu w0, s0611; CHECK-NEXT: ret612entry:613 %conv = fptosi float %x to i64614 %spec.store.select = call i64 @llvm.smin.i64(i64 %conv, i64 4294967295)615 %spec.store.select7 = call i64 @llvm.smax.i64(i64 %spec.store.select, i64 0)616 %conv6 = trunc i64 %spec.store.select7 to i32617 ret i32 %conv6618}619 620define i32 @stest_f16i32_mm(half %x) {621; CHECK-CVT-LABEL: stest_f16i32_mm:622; CHECK-CVT: // %bb.0: // %entry623; CHECK-CVT-NEXT: fcvt s0, h0624; CHECK-CVT-NEXT: fcvtzs w0, s0625; CHECK-CVT-NEXT: ret626;627; CHECK-FP16-LABEL: stest_f16i32_mm:628; CHECK-FP16: // %bb.0: // %entry629; CHECK-FP16-NEXT: fcvtzs w0, h0630; CHECK-FP16-NEXT: ret631entry:632 %conv = fptosi half %x to i64633 %spec.store.select = call i64 @llvm.smin.i64(i64 %conv, i64 2147483647)634 %spec.store.select7 = call i64 @llvm.smax.i64(i64 %spec.store.select, i64 -2147483648)635 %conv6 = trunc i64 %spec.store.select7 to i32636 ret i32 %conv6637}638 639define i32 @utest_f16i32_mm(half %x) {640; CHECK-CVT-LABEL: utest_f16i32_mm:641; CHECK-CVT: // %bb.0: // %entry642; CHECK-CVT-NEXT: fcvt s0, h0643; CHECK-CVT-NEXT: fcvtzu w0, s0644; CHECK-CVT-NEXT: ret645;646; CHECK-FP16-LABEL: utest_f16i32_mm:647; CHECK-FP16: // %bb.0: // %entry648; CHECK-FP16-NEXT: fcvtzu w0, h0649; CHECK-FP16-NEXT: ret650entry:651 %conv = fptoui half %x to i64652 %spec.store.select = call i64 @llvm.umin.i64(i64 %conv, i64 4294967295)653 %conv6 = trunc i64 %spec.store.select to i32654 ret i32 %conv6655}656 657define i32 @ustest_f16i32_mm(half %x) {658; CHECK-CVT-LABEL: ustest_f16i32_mm:659; CHECK-CVT: // %bb.0: // %entry660; CHECK-CVT-NEXT: fcvt s0, h0661; CHECK-CVT-NEXT: fcvtzu w0, s0662; CHECK-CVT-NEXT: ret663;664; CHECK-FP16-LABEL: ustest_f16i32_mm:665; CHECK-FP16: // %bb.0: // %entry666; CHECK-FP16-NEXT: fcvtzu w0, h0667; CHECK-FP16-NEXT: ret668entry:669 %conv = fptosi half %x to i64670 %spec.store.select = call i64 @llvm.smin.i64(i64 %conv, i64 4294967295)671 %spec.store.select7 = call i64 @llvm.smax.i64(i64 %spec.store.select, i64 0)672 %conv6 = trunc i64 %spec.store.select7 to i32673 ret i32 %conv6674}675 676; i16 saturate677 678define i16 @stest_f64i16_mm(double %x) {679; CHECK-LABEL: stest_f64i16_mm:680; CHECK: // %bb.0: // %entry681; CHECK-NEXT: fcvtzs w8, d0682; CHECK-NEXT: mov w9, #32767 // =0x7fff683; CHECK-NEXT: cmp w8, w9684; CHECK-NEXT: csel w8, w8, w9, lt685; CHECK-NEXT: mov w9, #-32768 // =0xffff8000686; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768687; CHECK-NEXT: csel w0, w8, w9, gt688; CHECK-NEXT: ret689entry:690 %conv = fptosi double %x to i32691 %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 32767)692 %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 -32768)693 %conv6 = trunc i32 %spec.store.select7 to i16694 ret i16 %conv6695}696 697define i16 @utest_f64i16_mm(double %x) {698; CHECK-LABEL: utest_f64i16_mm:699; CHECK: // %bb.0: // %entry700; CHECK-NEXT: fcvtzu w8, d0701; CHECK-NEXT: mov w9, #65535 // =0xffff702; CHECK-NEXT: cmp w8, w9703; CHECK-NEXT: csel w0, w8, w9, lo704; CHECK-NEXT: ret705entry:706 %conv = fptoui double %x to i32707 %spec.store.select = call i32 @llvm.umin.i32(i32 %conv, i32 65535)708 %conv6 = trunc i32 %spec.store.select to i16709 ret i16 %conv6710}711 712define i16 @ustest_f64i16_mm(double %x) {713; CHECK-LABEL: ustest_f64i16_mm:714; CHECK: // %bb.0: // %entry715; CHECK-NEXT: fcvtzs w8, d0716; CHECK-NEXT: mov w9, #65535 // =0xffff717; CHECK-NEXT: cmp w8, w9718; CHECK-NEXT: csel w8, w8, w9, lt719; CHECK-NEXT: bic w0, w8, w8, asr #31720; CHECK-NEXT: ret721entry:722 %conv = fptosi double %x to i32723 %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 65535)724 %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 0)725 %conv6 = trunc i32 %spec.store.select7 to i16726 ret i16 %conv6727}728 729define i16 @stest_f32i16_mm(float %x) {730; CHECK-LABEL: stest_f32i16_mm:731; CHECK: // %bb.0: // %entry732; CHECK-NEXT: fcvtzs w8, s0733; CHECK-NEXT: mov w9, #32767 // =0x7fff734; CHECK-NEXT: cmp w8, w9735; CHECK-NEXT: csel w8, w8, w9, lt736; CHECK-NEXT: mov w9, #-32768 // =0xffff8000737; CHECK-NEXT: cmn w8, #8, lsl #12 // =32768738; CHECK-NEXT: csel w0, w8, w9, gt739; CHECK-NEXT: ret740entry:741 %conv = fptosi float %x to i32742 %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 32767)743 %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 -32768)744 %conv6 = trunc i32 %spec.store.select7 to i16745 ret i16 %conv6746}747 748define i16 @utest_f32i16_mm(float %x) {749; CHECK-LABEL: utest_f32i16_mm:750; CHECK: // %bb.0: // %entry751; CHECK-NEXT: fcvtzu w8, s0752; CHECK-NEXT: mov w9, #65535 // =0xffff753; CHECK-NEXT: cmp w8, w9754; CHECK-NEXT: csel w0, w8, w9, lo755; CHECK-NEXT: ret756entry:757 %conv = fptoui float %x to i32758 %spec.store.select = call i32 @llvm.umin.i32(i32 %conv, i32 65535)759 %conv6 = trunc i32 %spec.store.select to i16760 ret i16 %conv6761}762 763define i16 @ustest_f32i16_mm(float %x) {764; CHECK-LABEL: ustest_f32i16_mm:765; CHECK: // %bb.0: // %entry766; CHECK-NEXT: fcvtzs w8, s0767; CHECK-NEXT: mov w9, #65535 // =0xffff768; CHECK-NEXT: cmp w8, w9769; CHECK-NEXT: csel w8, w8, w9, lt770; CHECK-NEXT: bic w0, w8, w8, asr #31771; CHECK-NEXT: ret772entry:773 %conv = fptosi float %x to i32774 %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 65535)775 %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 0)776 %conv6 = trunc i32 %spec.store.select7 to i16777 ret i16 %conv6778}779 780define i16 @stest_f16i16_mm(half %x) {781; CHECK-CVT-LABEL: stest_f16i16_mm:782; CHECK-CVT: // %bb.0: // %entry783; CHECK-CVT-NEXT: fcvt s0, h0784; CHECK-CVT-NEXT: mov w9, #32767 // =0x7fff785; CHECK-CVT-NEXT: fcvtzs w8, s0786; CHECK-CVT-NEXT: cmp w8, w9787; CHECK-CVT-NEXT: csel w8, w8, w9, lt788; CHECK-CVT-NEXT: mov w9, #-32768 // =0xffff8000789; CHECK-CVT-NEXT: cmn w8, #8, lsl #12 // =32768790; CHECK-CVT-NEXT: csel w0, w8, w9, gt791; CHECK-CVT-NEXT: ret792;793; CHECK-FP16-LABEL: stest_f16i16_mm:794; CHECK-FP16: // %bb.0: // %entry795; CHECK-FP16-NEXT: fcvtzs w8, h0796; CHECK-FP16-NEXT: mov w9, #32767 // =0x7fff797; CHECK-FP16-NEXT: cmp w8, w9798; CHECK-FP16-NEXT: csel w8, w8, w9, lt799; CHECK-FP16-NEXT: mov w9, #-32768 // =0xffff8000800; CHECK-FP16-NEXT: cmn w8, #8, lsl #12 // =32768801; CHECK-FP16-NEXT: csel w0, w8, w9, gt802; CHECK-FP16-NEXT: ret803entry:804 %conv = fptosi half %x to i32805 %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 32767)806 %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 -32768)807 %conv6 = trunc i32 %spec.store.select7 to i16808 ret i16 %conv6809}810 811define i16 @utest_f16i16_mm(half %x) {812; CHECK-CVT-LABEL: utest_f16i16_mm:813; CHECK-CVT: // %bb.0: // %entry814; CHECK-CVT-NEXT: fcvt s0, h0815; CHECK-CVT-NEXT: mov w9, #65535 // =0xffff816; CHECK-CVT-NEXT: fcvtzu w8, s0817; CHECK-CVT-NEXT: cmp w8, w9818; CHECK-CVT-NEXT: csel w0, w8, w9, lo819; CHECK-CVT-NEXT: ret820;821; CHECK-FP16-LABEL: utest_f16i16_mm:822; CHECK-FP16: // %bb.0: // %entry823; CHECK-FP16-NEXT: fcvtzu w8, h0824; CHECK-FP16-NEXT: mov w9, #65535 // =0xffff825; CHECK-FP16-NEXT: cmp w8, w9826; CHECK-FP16-NEXT: csel w0, w8, w9, lo827; CHECK-FP16-NEXT: ret828entry:829 %conv = fptoui half %x to i32830 %spec.store.select = call i32 @llvm.umin.i32(i32 %conv, i32 65535)831 %conv6 = trunc i32 %spec.store.select to i16832 ret i16 %conv6833}834 835define i16 @ustest_f16i16_mm(half %x) {836; CHECK-CVT-LABEL: ustest_f16i16_mm:837; CHECK-CVT: // %bb.0: // %entry838; CHECK-CVT-NEXT: fcvt s0, h0839; CHECK-CVT-NEXT: mov w9, #65535 // =0xffff840; CHECK-CVT-NEXT: fcvtzs w8, s0841; CHECK-CVT-NEXT: cmp w8, w9842; CHECK-CVT-NEXT: csel w8, w8, w9, lt843; CHECK-CVT-NEXT: bic w0, w8, w8, asr #31844; CHECK-CVT-NEXT: ret845;846; CHECK-FP16-LABEL: ustest_f16i16_mm:847; CHECK-FP16: // %bb.0: // %entry848; CHECK-FP16-NEXT: fcvtzs w8, h0849; CHECK-FP16-NEXT: mov w9, #65535 // =0xffff850; CHECK-FP16-NEXT: cmp w8, w9851; CHECK-FP16-NEXT: csel w8, w8, w9, lt852; CHECK-FP16-NEXT: bic w0, w8, w8, asr #31853; CHECK-FP16-NEXT: ret854entry:855 %conv = fptosi half %x to i32856 %spec.store.select = call i32 @llvm.smin.i32(i32 %conv, i32 65535)857 %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 0)858 %conv6 = trunc i32 %spec.store.select7 to i16859 ret i16 %conv6860}861 862; i64 saturate863 864define i64 @stest_f64i64_mm(double %x) {865; CHECK-LABEL: stest_f64i64_mm:866; CHECK: // %bb.0: // %entry867; CHECK-NEXT: fcvtzs x0, d0868; CHECK-NEXT: ret869entry:870 %conv = fptosi double %x to i128871 %spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 9223372036854775807)872 %spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 -9223372036854775808)873 %conv6 = trunc i128 %spec.store.select7 to i64874 ret i64 %conv6875}876 877define i64 @utest_f64i64_mm(double %x) {878; CHECK-LABEL: utest_f64i64_mm:879; CHECK: // %bb.0: // %entry880; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill881; CHECK-NEXT: .cfi_def_cfa_offset 16882; CHECK-NEXT: .cfi_offset w30, -16883; CHECK-NEXT: bl __fixunsdfti884; CHECK-NEXT: cmp x1, #0885; CHECK-NEXT: csel x0, x0, xzr, eq886; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload887; CHECK-NEXT: ret888entry:889 %conv = fptoui double %x to i128890 %spec.store.select = call i128 @llvm.umin.i128(i128 %conv, i128 18446744073709551616)891 %conv6 = trunc i128 %spec.store.select to i64892 ret i64 %conv6893}894 895define i64 @ustest_f64i64_mm(double %x) {896; CHECK-LABEL: ustest_f64i64_mm:897; CHECK: // %bb.0: // %entry898; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill899; CHECK-NEXT: .cfi_def_cfa_offset 16900; CHECK-NEXT: .cfi_offset w30, -16901; CHECK-NEXT: bl __fixdfti902; CHECK-NEXT: cmp x1, #1903; CHECK-NEXT: csinc x8, x1, xzr, lt904; CHECK-NEXT: csel x9, x0, xzr, lt905; CHECK-NEXT: cmp x8, #0906; CHECK-NEXT: csel x0, xzr, x9, mi907; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload908; CHECK-NEXT: ret909entry:910 %conv = fptosi double %x to i128911 %spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 18446744073709551616)912 %spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 0)913 %conv6 = trunc i128 %spec.store.select7 to i64914 ret i64 %conv6915}916 917define i64 @stest_f32i64_mm(float %x) {918; CHECK-LABEL: stest_f32i64_mm:919; CHECK: // %bb.0: // %entry920; CHECK-NEXT: fcvtzs x0, s0921; CHECK-NEXT: ret922entry:923 %conv = fptosi float %x to i128924 %spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 9223372036854775807)925 %spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 -9223372036854775808)926 %conv6 = trunc i128 %spec.store.select7 to i64927 ret i64 %conv6928}929 930define i64 @utest_f32i64_mm(float %x) {931; CHECK-LABEL: utest_f32i64_mm:932; CHECK: // %bb.0: // %entry933; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill934; CHECK-NEXT: .cfi_def_cfa_offset 16935; CHECK-NEXT: .cfi_offset w30, -16936; CHECK-NEXT: bl __fixunssfti937; CHECK-NEXT: cmp x1, #0938; CHECK-NEXT: csel x0, x0, xzr, eq939; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload940; CHECK-NEXT: ret941entry:942 %conv = fptoui float %x to i128943 %spec.store.select = call i128 @llvm.umin.i128(i128 %conv, i128 18446744073709551616)944 %conv6 = trunc i128 %spec.store.select to i64945 ret i64 %conv6946}947 948define i64 @ustest_f32i64_mm(float %x) {949; CHECK-LABEL: ustest_f32i64_mm:950; CHECK: // %bb.0: // %entry951; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill952; CHECK-NEXT: .cfi_def_cfa_offset 16953; CHECK-NEXT: .cfi_offset w30, -16954; CHECK-NEXT: bl __fixsfti955; CHECK-NEXT: cmp x1, #1956; CHECK-NEXT: csinc x8, x1, xzr, lt957; CHECK-NEXT: csel x9, x0, xzr, lt958; CHECK-NEXT: cmp x8, #0959; CHECK-NEXT: csel x0, xzr, x9, mi960; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload961; CHECK-NEXT: ret962entry:963 %conv = fptosi float %x to i128964 %spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 18446744073709551616)965 %spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 0)966 %conv6 = trunc i128 %spec.store.select7 to i64967 ret i64 %conv6968}969 970define i64 @stest_f16i64_mm(half %x) {971; CHECK-CVT-LABEL: stest_f16i64_mm:972; CHECK-CVT: // %bb.0: // %entry973; CHECK-CVT-NEXT: fcvt s0, h0974; CHECK-CVT-NEXT: fcvtzs x0, s0975; CHECK-CVT-NEXT: ret976;977; CHECK-FP16-LABEL: stest_f16i64_mm:978; CHECK-FP16: // %bb.0: // %entry979; CHECK-FP16-NEXT: fcvtzs x0, h0980; CHECK-FP16-NEXT: ret981entry:982 %conv = fptosi half %x to i128983 %spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 9223372036854775807)984 %spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 -9223372036854775808)985 %conv6 = trunc i128 %spec.store.select7 to i64986 ret i64 %conv6987}988 989define i64 @utest_f16i64_mm(half %x) {990; CHECK-LABEL: utest_f16i64_mm:991; CHECK: // %bb.0: // %entry992; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill993; CHECK-NEXT: .cfi_def_cfa_offset 16994; CHECK-NEXT: .cfi_offset w30, -16995; CHECK-NEXT: bl __fixunshfti996; CHECK-NEXT: cmp x1, #0997; CHECK-NEXT: csel x0, x0, xzr, eq998; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload999; CHECK-NEXT: ret1000entry:1001 %conv = fptoui half %x to i1281002 %spec.store.select = call i128 @llvm.umin.i128(i128 %conv, i128 18446744073709551616)1003 %conv6 = trunc i128 %spec.store.select to i641004 ret i64 %conv61005}1006 1007define i64 @ustest_f16i64_mm(half %x) {1008; CHECK-LABEL: ustest_f16i64_mm:1009; CHECK: // %bb.0: // %entry1010; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill1011; CHECK-NEXT: .cfi_def_cfa_offset 161012; CHECK-NEXT: .cfi_offset w30, -161013; CHECK-NEXT: bl __fixhfti1014; CHECK-NEXT: cmp x1, #11015; CHECK-NEXT: csinc x8, x1, xzr, lt1016; CHECK-NEXT: csel x9, x0, xzr, lt1017; CHECK-NEXT: cmp x8, #01018; CHECK-NEXT: csel x0, xzr, x9, mi1019; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload1020; CHECK-NEXT: ret1021entry:1022 %conv = fptosi half %x to i1281023 %spec.store.select = call i128 @llvm.smin.i128(i128 %conv, i128 18446744073709551616)1024 %spec.store.select7 = call i128 @llvm.smax.i128(i128 %spec.store.select, i128 0)1025 %conv6 = trunc i128 %spec.store.select7 to i641026 ret i64 %conv61027}1028 1029; i32 non saturate1030 1031define i32 @ustest_f16i32_nsat(half %x) {1032; CHECK-CVT-LABEL: ustest_f16i32_nsat:1033; CHECK-CVT: // %bb.0:1034; CHECK-CVT-NEXT: fcvt s0, h01035; CHECK-CVT-NEXT: fcvtzs w8, s01036; CHECK-CVT-NEXT: and w8, w8, w8, asr #311037; CHECK-CVT-NEXT: bic w0, w8, w8, asr #311038; CHECK-CVT-NEXT: ret1039;1040; CHECK-FP16-LABEL: ustest_f16i32_nsat:1041; CHECK-FP16: // %bb.0:1042; CHECK-FP16-NEXT: fcvtzs w8, h01043; CHECK-FP16-NEXT: and w8, w8, w8, asr #311044; CHECK-FP16-NEXT: bic w0, w8, w8, asr #311045; CHECK-FP16-NEXT: ret1046 %conv = fptosi half %x to i321047 %spec.store.select = call i32 @llvm.smin.i32(i32 0, i32 %conv)1048 %spec.store.select7 = call i32 @llvm.smax.i32(i32 %spec.store.select, i32 0)1049 ret i32 %spec.store.select71050}1051 1052declare i32 @llvm.smin.i32(i32, i32)1053declare i32 @llvm.smax.i32(i32, i32)1054declare i32 @llvm.umin.i32(i32, i32)1055declare i64 @llvm.smin.i64(i64, i64)1056declare i64 @llvm.smax.i64(i64, i64)1057declare i64 @llvm.umin.i64(i64, i64)1058declare i128 @llvm.smin.i128(i128, i128)1059declare i128 @llvm.smax.i128(i128, i128)1060declare i128 @llvm.umin.i128(i128, i128)1061