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1; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s2 3define i64 @test_free_zext(ptr %a, ptr %b) {4; CHECK-LABEL: test_free_zext:5; CHECK-DAG: ldrb w[[A:[0-9]+]], [x0]6; CHECK: ldrh w[[B:[0-9]+]], [x1]7; CHECK: add x0, x[[B]], x[[A]]8 %1 = load i8, ptr %a, align 19 %conv = zext i8 %1 to i6410 %2 = load i16, ptr %b, align 211 %conv1 = zext i16 %2 to i6412 %add = add nsw i64 %conv1, %conv13 ret i64 %add14}15 16define void @test_free_zext2(ptr %ptr, ptr %dst1, ptr %dst2) {17; CHECK-LABEL: test_free_zext2:18; CHECK: ldrh w[[A:[0-9]+]], [x0]19; CHECK-NOT: and x20; CHECK: str w[[A]], [x1]21; CHECK: str x[[A]], [x2]22 %load = load i32, ptr %ptr, align 823 %load16 = and i32 %load, 6553524 %load64 = zext i32 %load16 to i6425 store i32 %load16, ptr %dst1, align 426 store i64 %load64, ptr %dst2, align 827 ret void28}29 30; Test for CodeGenPrepare::optimizeLoadExt(): simple case: two loads31; feeding a phi that zext's each loaded value.32define i32 @test_free_zext3(ptr %ptr, ptr %ptr2, ptr %dst, i32 %c) {33; CHECK-LABEL: test_free_zext3:34bb1:35; CHECK: ldrh [[REG:w[0-9]+]]36; CHECK-NOT: and {{w[0-9]+}}, [[REG]], #0xffff37 %tmp1 = load i32, ptr %ptr, align 438 %cmp = icmp ne i32 %c, 039 br i1 %cmp, label %bb2, label %bb340bb2:41; CHECK: ldrh [[REG2:w[0-9]+]]42; CHECK-NOT: and {{w[0-9]+}}, [[REG2]], #0xffff43 %tmp2 = load i32, ptr %ptr2, align 444 br label %bb345bb3:46 %tmp3 = phi i32 [ %tmp1, %bb1 ], [ %tmp2, %bb2 ]47; CHECK-NOT: and {{w[0-9]+}}, {{w[0-9]+}}, #0xffff48 %tmpand = and i32 %tmp3, 6553549 ret i32 %tmpand50}51 52; Test for CodeGenPrepare::optimizeLoadExt(): check case of zext-able53; load feeding a phi in the same block.54define void @test_free_zext4(ptr %ptr, ptr %ptr2, ptr %dst) {55; CHECK-LABEL: test_free_zext4:56; CHECK: ldrh [[REG:w[0-9]+]]57; TODO: fix isel to remove final and XCHECK-NOT: and {{w[0-9]+}}, {{w[0-9]+}}, #0xffff58; CHECK: ldrh [[REG:w[0-9]+]]59bb1:60 %load1 = load i32, ptr %ptr, align 461 br label %loop62loop:63 %phi = phi i32 [ %load1, %bb1 ], [ %load2, %loop ]64 %and = and i32 %phi, 6553565 store i32 %and, ptr %dst, align 466 %load2 = load i32, ptr %ptr2, align 467 %cmp = icmp ne i32 %and, 068 br i1 %cmp, label %loop, label %end69end:70 ret void71}72