568 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=2 2>&1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; CHECK-GI: warning: Instruction selection used fallback path for freeze_v2i86 7%struct.T = type { i32, i32 }8 9define i32 @freeze_int() {10; CHECK-LABEL: freeze_int:11; CHECK: // %bb.0:12; CHECK-NEXT: mul w0, w8, w813; CHECK-NEXT: ret14 %y1 = freeze i32 undef15 %t1 = mul i32 %y1, %y116 ret i32 %t117}18 19define i5 @freeze_int2() {20; CHECK-LABEL: freeze_int2:21; CHECK: // %bb.0:22; CHECK-NEXT: mul w0, w8, w823; CHECK-NEXT: ret24 %y1 = freeze i5 undef25 %t1 = mul i5 %y1, %y126 ret i5 %t127}28 29define float @freeze_float() {30; CHECK-LABEL: freeze_float:31; CHECK: // %bb.0:32; CHECK-NEXT: fadd s0, s0, s033; CHECK-NEXT: ret34 %y1 = freeze float undef35 %t1 = fadd float %y1, %y136 ret float %t137}38 39define <2 x i8> @freeze_v2i8() {40; CHECK-LABEL: freeze_v2i8:41; CHECK: // %bb.0:42; CHECK-NEXT: add v0.2s, v0.2s, v0.2s43; CHECK-NEXT: ret44 %y1 = freeze <2 x i8> undef45 %t1 = add <2 x i8> %y1, %y146 ret <2 x i8> %t147}48 49define <3 x i8> @freeze_v3i8() {50; CHECK-SD-LABEL: freeze_v3i8:51; CHECK-SD: // %bb.0:52; CHECK-SD-NEXT: add v0.4h, v0.4h, v0.4h53; CHECK-SD-NEXT: umov w0, v0.h[0]54; CHECK-SD-NEXT: umov w1, v0.h[1]55; CHECK-SD-NEXT: umov w2, v0.h[2]56; CHECK-SD-NEXT: ret57;58; CHECK-GI-LABEL: freeze_v3i8:59; CHECK-GI: // %bb.0:60; CHECK-GI-NEXT: mov b0, v0.b[1]61; CHECK-GI-NEXT: mov b1, v0.b[2]62; CHECK-GI-NEXT: fmov w8, s063; CHECK-GI-NEXT: mov v0.h[1], w864; CHECK-GI-NEXT: fmov w8, s165; CHECK-GI-NEXT: mov v0.h[2], w866; CHECK-GI-NEXT: add v0.4h, v0.4h, v0.4h67; CHECK-GI-NEXT: umov w0, v0.h[0]68; CHECK-GI-NEXT: umov w1, v0.h[1]69; CHECK-GI-NEXT: umov w2, v0.h[2]70; CHECK-GI-NEXT: ret71 %y1 = freeze <3 x i8> undef72 %t1 = add <3 x i8> %y1, %y173 ret <3 x i8> %t174}75 76define <4 x i8> @freeze_v4i8() {77; CHECK-SD-LABEL: freeze_v4i8:78; CHECK-SD: // %bb.0:79; CHECK-SD-NEXT: add v0.4h, v0.4h, v0.4h80; CHECK-SD-NEXT: ret81;82; CHECK-GI-LABEL: freeze_v4i8:83; CHECK-GI: // %bb.0:84; CHECK-GI-NEXT: mov b0, v0.b[1]85; CHECK-GI-NEXT: fmov w8, s086; CHECK-GI-NEXT: mov b1, v0.b[2]87; CHECK-GI-NEXT: mov v0.h[1], w888; CHECK-GI-NEXT: fmov w8, s189; CHECK-GI-NEXT: mov b2, v0.b[3]90; CHECK-GI-NEXT: mov v0.h[2], w891; CHECK-GI-NEXT: fmov w8, s292; CHECK-GI-NEXT: mov v0.h[3], w893; CHECK-GI-NEXT: add v0.4h, v0.4h, v0.4h94; CHECK-GI-NEXT: ret95 %y1 = freeze <4 x i8> undef96 %t1 = add <4 x i8> %y1, %y197 ret <4 x i8> %t198}99 100define <8 x i8> @freeze_v8i8() {101; CHECK-LABEL: freeze_v8i8:102; CHECK: // %bb.0:103; CHECK-NEXT: add v0.8b, v0.8b, v0.8b104; CHECK-NEXT: ret105 %y1 = freeze <8 x i8> undef106 %t1 = add <8 x i8> %y1, %y1107 ret <8 x i8> %t1108}109 110define <16 x i8> @freeze_v16i8() {111; CHECK-LABEL: freeze_v16i8:112; CHECK: // %bb.0:113; CHECK-NEXT: add v0.16b, v0.16b, v0.16b114; CHECK-NEXT: ret115 %y1 = freeze <16 x i8> undef116 %t1 = add <16 x i8> %y1, %y1117 ret <16 x i8> %t1118}119 120define <32 x i8> @freeze_v32i8() {121; CHECK-LABEL: freeze_v32i8:122; CHECK: // %bb.0:123; CHECK-NEXT: add v0.16b, v0.16b, v0.16b124; CHECK-NEXT: mov v1.16b, v0.16b125; CHECK-NEXT: ret126 %y1 = freeze <32 x i8> undef127 %t1 = add <32 x i8> %y1, %y1128 ret <32 x i8> %t1129}130 131define <2 x i16> @freeze_v2i16() {132; CHECK-SD-LABEL: freeze_v2i16:133; CHECK-SD: // %bb.0:134; CHECK-SD-NEXT: add v0.2s, v0.2s, v0.2s135; CHECK-SD-NEXT: ret136;137; CHECK-GI-LABEL: freeze_v2i16:138; CHECK-GI: // %bb.0:139; CHECK-GI-NEXT: mov h0, v0.h[1]140; CHECK-GI-NEXT: fmov w8, s0141; CHECK-GI-NEXT: mov v0.s[1], w8142; CHECK-GI-NEXT: add v0.2s, v0.2s, v0.2s143; CHECK-GI-NEXT: ret144 %y1 = freeze <2 x i16> undef145 %t1 = add <2 x i16> %y1, %y1146 ret <2 x i16> %t1147}148 149define <3 x i16> @freeze_v3i16() {150; CHECK-LABEL: freeze_v3i16:151; CHECK: // %bb.0:152; CHECK-NEXT: add v0.4h, v0.4h, v0.4h153; CHECK-NEXT: ret154 %y1 = freeze <3 x i16> undef155 %t1 = add <3 x i16> %y1, %y1156 ret <3 x i16> %t1157}158 159define <4 x i16> @freeze_v4i16() {160; CHECK-LABEL: freeze_v4i16:161; CHECK: // %bb.0:162; CHECK-NEXT: add v0.4h, v0.4h, v0.4h163; CHECK-NEXT: ret164 %y1 = freeze <4 x i16> undef165 %t1 = add <4 x i16> %y1, %y1166 ret <4 x i16> %t1167}168 169define <8 x i16> @freeze_v8i16() {170; CHECK-LABEL: freeze_v8i16:171; CHECK: // %bb.0:172; CHECK-NEXT: add v0.8h, v0.8h, v0.8h173; CHECK-NEXT: ret174 %y1 = freeze <8 x i16> undef175 %t1 = add <8 x i16> %y1, %y1176 ret <8 x i16> %t1177}178 179define <16 x i16> @freeze_v16i16() {180; CHECK-LABEL: freeze_v16i16:181; CHECK: // %bb.0:182; CHECK-NEXT: add v0.8h, v0.8h, v0.8h183; CHECK-NEXT: mov v1.16b, v0.16b184; CHECK-NEXT: ret185 %y1 = freeze <16 x i16> undef186 %t1 = add <16 x i16> %y1, %y1187 ret <16 x i16> %t1188}189 190define <2 x i32> @freeze_v2i32() {191; CHECK-LABEL: freeze_v2i32:192; CHECK: // %bb.0:193; CHECK-NEXT: add v0.2s, v0.2s, v0.2s194; CHECK-NEXT: ret195 %y1 = freeze <2 x i32> undef196 %t1 = add <2 x i32> %y1, %y1197 ret <2 x i32> %t1198}199 200define <3 x i32> @freeze_v3i32() {201; CHECK-LABEL: freeze_v3i32:202; CHECK: // %bb.0:203; CHECK-NEXT: add v0.4s, v0.4s, v0.4s204; CHECK-NEXT: ret205 %y1 = freeze <3 x i32> undef206 %t1 = add <3 x i32> %y1, %y1207 ret <3 x i32> %t1208}209 210define <4 x i32> @freeze_v4i32() {211; CHECK-LABEL: freeze_v4i32:212; CHECK: // %bb.0:213; CHECK-NEXT: add v0.4s, v0.4s, v0.4s214; CHECK-NEXT: ret215 %y1 = freeze <4 x i32> undef216 %t1 = add <4 x i32> %y1, %y1217 ret <4 x i32> %t1218}219 220define <8 x i32> @freeze_v8i32() {221; CHECK-LABEL: freeze_v8i32:222; CHECK: // %bb.0:223; CHECK-NEXT: add v0.4s, v0.4s, v0.4s224; CHECK-NEXT: mov v1.16b, v0.16b225; CHECK-NEXT: ret226 %y1 = freeze <8 x i32> undef227 %t1 = add <8 x i32> %y1, %y1228 ret <8 x i32> %t1229}230 231define <2 x i64> @freeze_v2i64() {232; CHECK-LABEL: freeze_v2i64:233; CHECK: // %bb.0:234; CHECK-NEXT: add v0.2d, v0.2d, v0.2d235; CHECK-NEXT: ret236 %y1 = freeze <2 x i64> undef237 %t1 = add <2 x i64> %y1, %y1238 ret <2 x i64> %t1239}240 241define <3 x i64> @freeze_v3i64() {242; CHECK-SD-LABEL: freeze_v3i64:243; CHECK-SD: // %bb.0:244; CHECK-SD-NEXT: add v0.2d, v0.2d, v0.2d245; CHECK-SD-NEXT: fmov d2, d0246; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8247; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1248; CHECK-SD-NEXT: ret249;250; CHECK-GI-LABEL: freeze_v3i64:251; CHECK-GI: // %bb.0:252; CHECK-GI-NEXT: add v0.2d, v0.2d, v0.2d253; CHECK-GI-NEXT: add x8, x8, x8254; CHECK-GI-NEXT: fmov d2, x8255; CHECK-GI-NEXT: mov d1, v0.d[1]256; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0257; CHECK-GI-NEXT: ret258 %y1 = freeze <3 x i64> undef259 %t1 = add <3 x i64> %y1, %y1260 ret <3 x i64> %t1261}262 263define <4 x i64> @freeze_v4i64() {264; CHECK-LABEL: freeze_v4i64:265; CHECK: // %bb.0:266; CHECK-NEXT: add v0.2d, v0.2d, v0.2d267; CHECK-NEXT: mov v1.16b, v0.16b268; CHECK-NEXT: ret269 %y1 = freeze <4 x i64> undef270 %t1 = add <4 x i64> %y1, %y1271 ret <4 x i64> %t1272}273 274define <2 x ptr> @freeze_v2p0() {275; CHECK-SD-LABEL: freeze_v2p0:276; CHECK-SD: // %bb.0:277; CHECK-SD-NEXT: mov w8, #4 // =0x4278; CHECK-SD-NEXT: dup v0.2d, x8279; CHECK-SD-NEXT: add v0.2d, v0.2d, v0.2d280; CHECK-SD-NEXT: ret281;282; CHECK-GI-LABEL: freeze_v2p0:283; CHECK-GI: // %bb.0:284; CHECK-GI-NEXT: adrp x8, .LCPI21_0285; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI21_0]286; CHECK-GI-NEXT: add v0.2d, v0.2d, v0.2d287; CHECK-GI-NEXT: ret288 %y1 = freeze <2 x ptr> undef289 %t1 = getelementptr i32, <2 x ptr> %y1, i32 1290 ret <2 x ptr> %t1291}292 293define <3 x ptr> @freeze_v3p0() {294; CHECK-SD-LABEL: freeze_v3p0:295; CHECK-SD: // %bb.0:296; CHECK-SD-NEXT: mov w8, #4 // =0x4297; CHECK-SD-NEXT: dup v2.2d, x8298; CHECK-SD-NEXT: add v0.2d, v0.2d, v2.2d299; CHECK-SD-NEXT: add d2, d0, d2300; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8301; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0302; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1303; CHECK-SD-NEXT: ret304;305; CHECK-GI-LABEL: freeze_v3p0:306; CHECK-GI: // %bb.0:307; CHECK-GI-NEXT: adrp x8, .LCPI22_0308; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI22_0]309; CHECK-GI-NEXT: add x8, x8, #4310; CHECK-GI-NEXT: fmov d2, x8311; CHECK-GI-NEXT: add v0.2d, v0.2d, v0.2d312; CHECK-GI-NEXT: mov d1, v0.d[1]313; CHECK-GI-NEXT: ret314 %y1 = freeze <3 x ptr> undef315 %t1 = getelementptr i32, <3 x ptr> %y1, i32 1316 ret <3 x ptr> %t1317}318 319define <4 x ptr> @freeze_v4p0() {320; CHECK-SD-LABEL: freeze_v4p0:321; CHECK-SD: // %bb.0:322; CHECK-SD-NEXT: mov w8, #4 // =0x4323; CHECK-SD-NEXT: dup v0.2d, x8324; CHECK-SD-NEXT: add v0.2d, v0.2d, v0.2d325; CHECK-SD-NEXT: mov v1.16b, v0.16b326; CHECK-SD-NEXT: ret327;328; CHECK-GI-LABEL: freeze_v4p0:329; CHECK-GI: // %bb.0:330; CHECK-GI-NEXT: adrp x8, .LCPI23_0331; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI23_0]332; CHECK-GI-NEXT: add v0.2d, v0.2d, v0.2d333; CHECK-GI-NEXT: mov v1.16b, v0.16b334; CHECK-GI-NEXT: ret335 %y1 = freeze <4 x ptr> undef336 %t1 = getelementptr i32, <4 x ptr> %y1, i32 1337 ret <4 x ptr> %t1338}339 340define ptr @freeze_ptr() {341; CHECK-LABEL: freeze_ptr:342; CHECK: // %bb.0:343; CHECK-NEXT: add x0, x8, #4344; CHECK-NEXT: ret345 %y1 = freeze ptr undef346 %t1 = getelementptr i8, ptr %y1, i64 4347 ret ptr %t1348}349 350define i32 @freeze_struct() {351; CHECK-LABEL: freeze_struct:352; CHECK: // %bb.0:353; CHECK-NEXT: add w0, w8, w8354; CHECK-NEXT: ret355 %y1 = freeze %struct.T undef356 %v1 = extractvalue %struct.T %y1, 0357 %v2 = extractvalue %struct.T %y1, 1358 %t1 = add i32 %v1, %v2359 ret i32 %t1360}361 362define i32 @freeze_anonstruct() {363; CHECK-LABEL: freeze_anonstruct:364; CHECK: // %bb.0:365; CHECK-NEXT: add w0, w8, w8366; CHECK-NEXT: ret367 %y1 = freeze {i32, i32} undef368 %v1 = extractvalue {i32, i32} %y1, 0369 %v2 = extractvalue {i32, i32} %y1, 1370 %t1 = add i32 %v1, %v2371 ret i32 %t1372}373 374define i32 @freeze_anonstruct2() {375; CHECK-LABEL: freeze_anonstruct2:376; CHECK: // %bb.0:377; CHECK-NEXT: add w0, w8, w8, uxth378; CHECK-NEXT: ret379 %y1 = freeze {i32, i16} undef380 %v1 = extractvalue {i32, i16} %y1, 0381 %v2 = extractvalue {i32, i16} %y1, 1382 %z2 = zext i16 %v2 to i32383 %t1 = add i32 %v1, %z2384 ret i32 %t1385}386 387define i64 @freeze_array() {388; CHECK-LABEL: freeze_array:389; CHECK: // %bb.0:390; CHECK-NEXT: add x0, x8, x8391; CHECK-NEXT: ret392 %y1 = freeze [2 x i64] undef393 %v1 = extractvalue [2 x i64] %y1, 0394 %v2 = extractvalue [2 x i64] %y1, 1395 %t1 = add i64 %v1, %v2396 ret i64 %t1397}398 399define <8 x i16> @freeze_abdu(<8 x i16> %a, <8 x i16> %b) {400; CHECK-SD-LABEL: freeze_abdu:401; CHECK-SD: // %bb.0:402; CHECK-SD-NEXT: uaba v0.8h, v0.8h, v1.8h403; CHECK-SD-NEXT: ret404;405; CHECK-GI-LABEL: freeze_abdu:406; CHECK-GI: // %bb.0:407; CHECK-GI-NEXT: uabd v1.8h, v0.8h, v1.8h408; CHECK-GI-NEXT: add v0.8h, v0.8h, v1.8h409; CHECK-GI-NEXT: ret410 %d = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %a, <8 x i16> %b)411 %f = freeze <8 x i16> %d412 %r = add <8 x i16> %a, %f413 ret <8 x i16> %r414}415 416define <8 x i16> @freeze_abds(<8 x i16> %a, <8 x i16> %b) {417; CHECK-SD-LABEL: freeze_abds:418; CHECK-SD: // %bb.0:419; CHECK-SD-NEXT: saba v0.8h, v0.8h, v1.8h420; CHECK-SD-NEXT: ret421;422; CHECK-GI-LABEL: freeze_abds:423; CHECK-GI: // %bb.0:424; CHECK-GI-NEXT: sabd v1.8h, v0.8h, v1.8h425; CHECK-GI-NEXT: add v0.8h, v0.8h, v1.8h426; CHECK-GI-NEXT: ret427 %d = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %a, <8 x i16> %b)428 %f = freeze <8 x i16> %d429 %r = add <8 x i16> %a, %f430 ret <8 x i16> %r431}432 433define <8 x i16> @freeze_uhadd(<8 x i16> %a0, <8 x i16> %a1) {434; CHECK-SD-LABEL: freeze_uhadd:435; CHECK-SD: // %bb.0:436; CHECK-SD-NEXT: movi v2.8h, #15437; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b438; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b439; CHECK-SD-NEXT: uhadd v0.8h, v0.8h, v1.8h440; CHECK-SD-NEXT: ret441;442; CHECK-GI-LABEL: freeze_uhadd:443; CHECK-GI: // %bb.0:444; CHECK-GI-NEXT: movi v2.8h, #15445; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b446; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b447; CHECK-GI-NEXT: movi v2.8h, #31448; CHECK-GI-NEXT: uhadd v0.8h, v0.8h, v1.8h449; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b450; CHECK-GI-NEXT: ret451 %m0 = and <8 x i16> %a0, splat (i16 15)452 %m1 = and <8 x i16> %a1, splat (i16 15)453 %avg = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %m0, <8 x i16> %m1)454 %frozen = freeze <8 x i16> %avg455 %masked = and <8 x i16> %frozen, splat (i16 31)456 ret <8 x i16> %masked457}458 459define <8 x i16> @freeze_urhadd(<8 x i16> %a0, <8 x i16> %a1) {460; CHECK-SD-LABEL: freeze_urhadd:461; CHECK-SD: // %bb.0:462; CHECK-SD-NEXT: movi v2.8h, #15463; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b464; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b465; CHECK-SD-NEXT: urhadd v0.8h, v0.8h, v1.8h466; CHECK-SD-NEXT: ret467;468; CHECK-GI-LABEL: freeze_urhadd:469; CHECK-GI: // %bb.0:470; CHECK-GI-NEXT: movi v2.8h, #15471; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b472; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b473; CHECK-GI-NEXT: movi v2.8h, #31474; CHECK-GI-NEXT: urhadd v0.8h, v0.8h, v1.8h475; CHECK-GI-NEXT: and v0.16b, v0.16b, v2.16b476; CHECK-GI-NEXT: ret477 %m0 = and <8 x i16> %a0, splat (i16 15)478 %m1 = and <8 x i16> %a1, splat (i16 15)479 %avg = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %m0, <8 x i16> %m1)480 %frozen = freeze <8 x i16> %avg481 %masked = and <8 x i16> %frozen, splat (i16 31)482 ret <8 x i16> %masked483}484 485define <8 x i16> @freeze_shadd(<8 x i8> %a0, <8 x i16> %a1) {486; CHECK-SD-LABEL: freeze_shadd:487; CHECK-SD: // %bb.0:488; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0489; CHECK-SD-NEXT: sshr v1.8h, v1.8h, #8490; CHECK-SD-NEXT: shadd v0.8h, v0.8h, v1.8h491; CHECK-SD-NEXT: ret492;493; CHECK-GI-LABEL: freeze_shadd:494; CHECK-GI: // %bb.0:495; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0496; CHECK-GI-NEXT: sshr v1.8h, v1.8h, #8497; CHECK-GI-NEXT: shadd v0.8h, v0.8h, v1.8h498; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8499; CHECK-GI-NEXT: sshr v0.8h, v0.8h, #8500; CHECK-GI-NEXT: ret501 %x0 = sext <8 x i8> %a0 to <8 x i16>502 %x1 = ashr <8 x i16> %a1, splat (i16 8)503 %avg = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)504 %frozen = freeze <8 x i16> %avg505 %trunc = trunc <8 x i16> %frozen to <8 x i8>506 %sext = sext <8 x i8> %trunc to <8 x i16>507 ret <8 x i16> %sext508}509 510define <8 x i16> @freeze_srhadd(<8 x i8> %a0, <8 x i16> %a1) {511; CHECK-SD-LABEL: freeze_srhadd:512; CHECK-SD: // %bb.0:513; CHECK-SD-NEXT: sshll v0.8h, v0.8b, #0514; CHECK-SD-NEXT: sshr v1.8h, v1.8h, #8515; CHECK-SD-NEXT: srhadd v0.8h, v0.8h, v1.8h516; CHECK-SD-NEXT: ret517;518; CHECK-GI-LABEL: freeze_srhadd:519; CHECK-GI: // %bb.0:520; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0521; CHECK-GI-NEXT: sshr v1.8h, v1.8h, #8522; CHECK-GI-NEXT: srhadd v0.8h, v0.8h, v1.8h523; CHECK-GI-NEXT: shl v0.8h, v0.8h, #8524; CHECK-GI-NEXT: sshr v0.8h, v0.8h, #8525; CHECK-GI-NEXT: ret526 %x0 = sext <8 x i8> %a0 to <8 x i16>527 %x1 = ashr <8 x i16> %a1, splat (i16 8)528 %avg = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)529 %frozen = freeze <8 x i16> %avg530 %trunc = trunc <8 x i16> %frozen to <8 x i8>531 %sext = sext <8 x i8> %trunc to <8 x i16>532 ret <8 x i16> %sext533}534 535define i32 @freeze_scmp(i32 %a0) nounwind {536; CHECK-LABEL: freeze_scmp:537; CHECK: // %bb.0:538; CHECK-NEXT: mov w8, #2 // =0x2539; CHECK-NEXT: cmp w8, w0540; CHECK-NEXT: cset w8, gt541; CHECK-NEXT: csinv w8, w8, wzr, ge542; CHECK-NEXT: cmp wzr, w8543; CHECK-NEXT: cset w8, gt544; CHECK-NEXT: csinv w0, w8, wzr, ge545; CHECK-NEXT: ret546 %x = call i32 @llvm.scmp.i32(i32 2, i32 %a0)547 %y = freeze i32 %x548 %z = call i32 @llvm.scmp.i32(i32 0, i32 %y)549 ret i32 %z550}551 552define i32 @freeze_ucmp(i32 %a0) nounwind {553; CHECK-LABEL: freeze_ucmp:554; CHECK: // %bb.0:555; CHECK-NEXT: mov w8, #2 // =0x2556; CHECK-NEXT: cmp w8, w0557; CHECK-NEXT: cset w8, hi558; CHECK-NEXT: csinv w8, w8, wzr, hs559; CHECK-NEXT: cmp w8, #1560; CHECK-NEXT: cset w8, hi561; CHECK-NEXT: csinv w0, w8, wzr, hs562; CHECK-NEXT: ret563 %x = call i32 @llvm.ucmp.i32(i32 2, i32 %a0)564 %y = freeze i32 %x565 %z = call i32 @llvm.ucmp.i32(i32 %y, i32 1)566 ret i32 %z567}568