135 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc %s -o - | FileCheck %s3; RUN: llc -combiner-disabled %s -o - | FileCheck %s4 5target triple = "aarch64-unknown-linux-gnu"6 7; Verify lowering code in isolation to ensure we can lower shifts that would8; normally be optimised away.9 10define i32 @fshl_i32_by_zero(i32 %unused, i32 %a, i32 %b) {11; CHECK-LABEL: fshl_i32_by_zero:12; CHECK: // %bb.0:13; CHECK-NEXT: mov w0, w114; CHECK-NEXT: ret15 %r = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 0)16 ret i32 %r17}18 19define i32 @fshl_i32_by_half_srclen(i32 %unused, i32 %a, i32 %b) {20; CHECK-LABEL: fshl_i32_by_half_srclen:21; CHECK: // %bb.0:22; CHECK-NEXT: extr w0, w1, w2, #1623; CHECK-NEXT: ret24 %r = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 16)25 ret i32 %r26}27 28define i32 @fshl_i32_by_srclen(i32 %unused, i32 %a, i32 %b) {29; CHECK-LABEL: fshl_i32_by_srclen:30; CHECK: // %bb.0:31; CHECK-NEXT: mov w0, w132; CHECK-NEXT: ret33 %r = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 32)34 ret i32 %r35}36 37define i32 @fshl_i32_by_srclen_plus1(i32 %unused, i32 %a, i32 %b) {38; CHECK-LABEL: fshl_i32_by_srclen_plus1:39; CHECK: // %bb.0:40; CHECK-NEXT: extr w0, w1, w2, #3141; CHECK-NEXT: ret42 %r = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 33)43 ret i32 %r44}45 46define i64 @fshl_i64_by_zero(i64 %unused, i64 %a, i64 %b) {47; CHECK-LABEL: fshl_i64_by_zero:48; CHECK: // %bb.0:49; CHECK-NEXT: mov x0, x150; CHECK-NEXT: ret51 %r = call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 0)52 ret i64 %r53}54 55define i64 @fshl_i64_by_srclen(i64 %unused, i64 %a, i64 %b) {56; CHECK-LABEL: fshl_i64_by_srclen:57; CHECK: // %bb.0:58; CHECK-NEXT: mov x0, x159; CHECK-NEXT: ret60 %r = call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 64)61 ret i64 %r62}63 64define i64 @fshl_i64_by_srclen_plus1(i64 %unused, i64 %a, i64 %b) {65; CHECK-LABEL: fshl_i64_by_srclen_plus1:66; CHECK: // %bb.0:67; CHECK-NEXT: extr x0, x1, x2, #6368; CHECK-NEXT: ret69 %r = call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 65)70 ret i64 %r71}72 73define i32 @fshr_i32_by_zero(i32 %unused, i32 %a, i32 %b) {74; CHECK-LABEL: fshr_i32_by_zero:75; CHECK: // %bb.0:76; CHECK-NEXT: mov w0, w277; CHECK-NEXT: ret78 %r = call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 0)79 ret i32 %r80}81 82define i32 @fshr_i32_by_srclen(i32 %unused, i32 %a, i32 %b) {83; CHECK-LABEL: fshr_i32_by_srclen:84; CHECK: // %bb.0:85; CHECK-NEXT: mov w0, w286; CHECK-NEXT: ret87 %r = call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 32)88 ret i32 %r89}90 91define i32 @fshr_i32_by_half_srclen(i32 %unused, i32 %a, i32 %b) {92; CHECK-LABEL: fshr_i32_by_half_srclen:93; CHECK: // %bb.0:94; CHECK-NEXT: extr w0, w1, w2, #1695; CHECK-NEXT: ret96 %r = call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 16)97 ret i32 %r98}99 100define i32 @fshr_i32_by_srclen_plus1(i32 %unused, i32 %a, i32 %b) {101; CHECK-LABEL: fshr_i32_by_srclen_plus1:102; CHECK: // %bb.0:103; CHECK-NEXT: extr w0, w1, w2, #1104; CHECK-NEXT: ret105 %r = call i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 33)106 ret i32 %r107}108 109define i64 @fshr_i64_by_zero(i64 %unused, i64 %a, i64 %b) {110; CHECK-LABEL: fshr_i64_by_zero:111; CHECK: // %bb.0:112; CHECK-NEXT: mov x0, x2113; CHECK-NEXT: ret114 %r = call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 0)115 ret i64 %r116}117 118define i64 @fshr_i64_by_srclen(i64 %unused, i64 %a, i64 %b) {119; CHECK-LABEL: fshr_i64_by_srclen:120; CHECK: // %bb.0:121; CHECK-NEXT: mov x0, x2122; CHECK-NEXT: ret123 %r = call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 64)124 ret i64 %r125}126 127define i64 @fshr_i64_by_srclen_plus1(i64 %unused, i64 %a, i64 %b) {128; CHECK-LABEL: fshr_i64_by_srclen_plus1:129; CHECK: // %bb.0:130; CHECK-NEXT: extr x0, x1, x2, #1131; CHECK-NEXT: ret132 %r = call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 65)133 ret i64 %r134}135