4491 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-none-eabi -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define i8 @rotl_i8(i8 %a, i8 %c) {6; CHECK-SD-LABEL: rotl_i8:7; CHECK-SD: // %bb.0: // %entry8; CHECK-SD-NEXT: neg w8, w19; CHECK-SD-NEXT: and w9, w0, #0xff10; CHECK-SD-NEXT: and w10, w1, #0x711; CHECK-SD-NEXT: and w8, w8, #0x712; CHECK-SD-NEXT: lsl w10, w0, w1013; CHECK-SD-NEXT: lsr w8, w9, w814; CHECK-SD-NEXT: orr w0, w10, w815; CHECK-SD-NEXT: ret16;17; CHECK-GI-LABEL: rotl_i8:18; CHECK-GI: // %bb.0: // %entry19; CHECK-GI-NEXT: mov x8, xzr20; CHECK-GI-NEXT: neg w9, w121; CHECK-GI-NEXT: and w10, w0, #0xff22; CHECK-GI-NEXT: sub x8, x8, w9, uxtb23; CHECK-GI-NEXT: and x9, x9, #0x724; CHECK-GI-NEXT: lsr w9, w10, w925; CHECK-GI-NEXT: and x8, x8, #0x726; CHECK-GI-NEXT: lsl w8, w0, w827; CHECK-GI-NEXT: orr w0, w9, w828; CHECK-GI-NEXT: ret29entry:30 %d = call i8 @llvm.fshl(i8 %a, i8 %a, i8 %c)31 ret i8 %d32}33 34define i8 @rotr_i8(i8 %a, i8 %c) {35; CHECK-SD-LABEL: rotr_i8:36; CHECK-SD: // %bb.0: // %entry37; CHECK-SD-NEXT: neg w8, w138; CHECK-SD-NEXT: and w9, w0, #0xff39; CHECK-SD-NEXT: and w10, w1, #0x740; CHECK-SD-NEXT: and w8, w8, #0x741; CHECK-SD-NEXT: lsr w9, w9, w1042; CHECK-SD-NEXT: lsl w8, w0, w843; CHECK-SD-NEXT: orr w0, w9, w844; CHECK-SD-NEXT: ret45;46; CHECK-GI-LABEL: rotr_i8:47; CHECK-GI: // %bb.0: // %entry48; CHECK-GI-NEXT: mov x8, xzr49; CHECK-GI-NEXT: // kill: def $w1 killed $w1 def $x150; CHECK-GI-NEXT: and x9, x1, #0x751; CHECK-GI-NEXT: and w10, w0, #0xff52; CHECK-GI-NEXT: sub x8, x8, w1, uxtb53; CHECK-GI-NEXT: lsr w9, w10, w954; CHECK-GI-NEXT: and x8, x8, #0x755; CHECK-GI-NEXT: lsl w8, w0, w856; CHECK-GI-NEXT: orr w0, w9, w857; CHECK-GI-NEXT: ret58entry:59 %d = call i8 @llvm.fshr(i8 %a, i8 %a, i8 %c)60 ret i8 %d61}62 63define i16 @rotl_i16(i16 %a, i16 %c) {64; CHECK-SD-LABEL: rotl_i16:65; CHECK-SD: // %bb.0: // %entry66; CHECK-SD-NEXT: neg w8, w167; CHECK-SD-NEXT: and w9, w0, #0xffff68; CHECK-SD-NEXT: and w10, w1, #0xf69; CHECK-SD-NEXT: and w8, w8, #0xf70; CHECK-SD-NEXT: lsl w10, w0, w1071; CHECK-SD-NEXT: lsr w8, w9, w872; CHECK-SD-NEXT: orr w0, w10, w873; CHECK-SD-NEXT: ret74;75; CHECK-GI-LABEL: rotl_i16:76; CHECK-GI: // %bb.0: // %entry77; CHECK-GI-NEXT: mov x8, xzr78; CHECK-GI-NEXT: neg w9, w179; CHECK-GI-NEXT: and w10, w0, #0xffff80; CHECK-GI-NEXT: sub x8, x8, w9, uxth81; CHECK-GI-NEXT: and x9, x9, #0xf82; CHECK-GI-NEXT: lsr w9, w10, w983; CHECK-GI-NEXT: and x8, x8, #0xf84; CHECK-GI-NEXT: lsl w8, w0, w885; CHECK-GI-NEXT: orr w0, w9, w886; CHECK-GI-NEXT: ret87entry:88 %d = call i16 @llvm.fshl(i16 %a, i16 %a, i16 %c)89 ret i16 %d90}91 92define i16 @rotr_i16(i16 %a, i16 %c) {93; CHECK-SD-LABEL: rotr_i16:94; CHECK-SD: // %bb.0: // %entry95; CHECK-SD-NEXT: neg w8, w196; CHECK-SD-NEXT: and w9, w0, #0xffff97; CHECK-SD-NEXT: and w10, w1, #0xf98; CHECK-SD-NEXT: and w8, w8, #0xf99; CHECK-SD-NEXT: lsr w9, w9, w10100; CHECK-SD-NEXT: lsl w8, w0, w8101; CHECK-SD-NEXT: orr w0, w9, w8102; CHECK-SD-NEXT: ret103;104; CHECK-GI-LABEL: rotr_i16:105; CHECK-GI: // %bb.0: // %entry106; CHECK-GI-NEXT: mov x8, xzr107; CHECK-GI-NEXT: // kill: def $w1 killed $w1 def $x1108; CHECK-GI-NEXT: and x9, x1, #0xf109; CHECK-GI-NEXT: and w10, w0, #0xffff110; CHECK-GI-NEXT: sub x8, x8, w1, uxth111; CHECK-GI-NEXT: lsr w9, w10, w9112; CHECK-GI-NEXT: and x8, x8, #0xf113; CHECK-GI-NEXT: lsl w8, w0, w8114; CHECK-GI-NEXT: orr w0, w9, w8115; CHECK-GI-NEXT: ret116entry:117 %d = call i16 @llvm.fshr(i16 %a, i16 %a, i16 %c)118 ret i16 %d119}120 121define i32 @rotl_i32(i32 %a, i32 %c) {122; CHECK-LABEL: rotl_i32:123; CHECK: // %bb.0: // %entry124; CHECK-NEXT: neg w8, w1125; CHECK-NEXT: ror w0, w0, w8126; CHECK-NEXT: ret127entry:128 %d = call i32 @llvm.fshl(i32 %a, i32 %a, i32 %c)129 ret i32 %d130}131 132define i32 @rotr_i32(i32 %a, i32 %c) {133; CHECK-LABEL: rotr_i32:134; CHECK: // %bb.0: // %entry135; CHECK-NEXT: ror w0, w0, w1136; CHECK-NEXT: ret137entry:138 %d = call i32 @llvm.fshr(i32 %a, i32 %a, i32 %c)139 ret i32 %d140}141 142define i64 @rotl_i64(i64 %a, i64 %c) {143; CHECK-SD-LABEL: rotl_i64:144; CHECK-SD: // %bb.0: // %entry145; CHECK-SD-NEXT: neg w8, w1146; CHECK-SD-NEXT: ror x0, x0, x8147; CHECK-SD-NEXT: ret148;149; CHECK-GI-LABEL: rotl_i64:150; CHECK-GI: // %bb.0: // %entry151; CHECK-GI-NEXT: neg x8, x1152; CHECK-GI-NEXT: ror x0, x0, x8153; CHECK-GI-NEXT: ret154entry:155 %d = call i64 @llvm.fshl(i64 %a, i64 %a, i64 %c)156 ret i64 %d157}158 159define i64 @rotr_i64(i64 %a, i64 %c) {160; CHECK-LABEL: rotr_i64:161; CHECK: // %bb.0: // %entry162; CHECK-NEXT: ror x0, x0, x1163; CHECK-NEXT: ret164entry:165 %d = call i64 @llvm.fshr(i64 %a, i64 %a, i64 %c)166 ret i64 %d167}168 169define i128 @rotl_i128(i128 %a, i128 %c) {170; CHECK-SD-LABEL: rotl_i128:171; CHECK-SD: // %bb.0: // %entry172; CHECK-SD-NEXT: tst x2, #0x40173; CHECK-SD-NEXT: mvn w12, w2174; CHECK-SD-NEXT: csel x8, x1, x0, ne175; CHECK-SD-NEXT: csel x9, x0, x1, ne176; CHECK-SD-NEXT: lsr x10, x9, #1177; CHECK-SD-NEXT: lsr x11, x8, #1178; CHECK-SD-NEXT: lsl x8, x8, x2179; CHECK-SD-NEXT: lsl x9, x9, x2180; CHECK-SD-NEXT: lsr x10, x10, x12181; CHECK-SD-NEXT: lsr x11, x11, x12182; CHECK-SD-NEXT: orr x0, x8, x10183; CHECK-SD-NEXT: orr x1, x9, x11184; CHECK-SD-NEXT: ret185;186; CHECK-GI-LABEL: rotl_i128:187; CHECK-GI: // %bb.0: // %entry188; CHECK-GI-NEXT: mov w8, #64 // =0x40189; CHECK-GI-NEXT: and x9, x2, #0x7f190; CHECK-GI-NEXT: neg x10, x2191; CHECK-GI-NEXT: sub x12, x8, x9192; CHECK-GI-NEXT: sub x11, x9, #64193; CHECK-GI-NEXT: lsl x14, x1, x9194; CHECK-GI-NEXT: lsr x12, x0, x12195; CHECK-GI-NEXT: lsl x13, x0, x9196; CHECK-GI-NEXT: cmp x9, #64197; CHECK-GI-NEXT: and x9, x10, #0x7f198; CHECK-GI-NEXT: lsl x11, x0, x11199; CHECK-GI-NEXT: orr x12, x12, x14200; CHECK-GI-NEXT: sub x8, x8, x9201; CHECK-GI-NEXT: sub x14, x9, #64202; CHECK-GI-NEXT: csel x11, x12, x11, lo203; CHECK-GI-NEXT: lsr x12, x0, x9204; CHECK-GI-NEXT: lsl x8, x1, x8205; CHECK-GI-NEXT: csel x13, x13, xzr, lo206; CHECK-GI-NEXT: tst x2, #0x7f207; CHECK-GI-NEXT: lsr x14, x1, x14208; CHECK-GI-NEXT: csel x11, x1, x11, eq209; CHECK-GI-NEXT: orr x8, x12, x8210; CHECK-GI-NEXT: cmp x9, #64211; CHECK-GI-NEXT: lsr x12, x1, x9212; CHECK-GI-NEXT: csel x8, x8, x14, lo213; CHECK-GI-NEXT: tst x10, #0x7f214; CHECK-GI-NEXT: csel x8, x0, x8, eq215; CHECK-GI-NEXT: cmp x9, #64216; CHECK-GI-NEXT: csel x9, x12, xzr, lo217; CHECK-GI-NEXT: orr x0, x13, x8218; CHECK-GI-NEXT: orr x1, x11, x9219; CHECK-GI-NEXT: ret220entry:221 %d = call i128 @llvm.fshl(i128 %a, i128 %a, i128 %c)222 ret i128 %d223}224 225define i128 @rotr_i128(i128 %a, i128 %c) {226; CHECK-SD-LABEL: rotr_i128:227; CHECK-SD: // %bb.0: // %entry228; CHECK-SD-NEXT: tst x2, #0x40229; CHECK-SD-NEXT: mvn w12, w2230; CHECK-SD-NEXT: csel x8, x0, x1, eq231; CHECK-SD-NEXT: csel x9, x1, x0, eq232; CHECK-SD-NEXT: lsl x10, x9, #1233; CHECK-SD-NEXT: lsl x11, x8, #1234; CHECK-SD-NEXT: lsr x8, x8, x2235; CHECK-SD-NEXT: lsr x9, x9, x2236; CHECK-SD-NEXT: lsl x10, x10, x12237; CHECK-SD-NEXT: lsl x11, x11, x12238; CHECK-SD-NEXT: orr x0, x10, x8239; CHECK-SD-NEXT: orr x1, x11, x9240; CHECK-SD-NEXT: ret241;242; CHECK-GI-LABEL: rotr_i128:243; CHECK-GI: // %bb.0: // %entry244; CHECK-GI-NEXT: mov w8, #64 // =0x40245; CHECK-GI-NEXT: and x9, x2, #0x7f246; CHECK-GI-NEXT: neg x13, x2247; CHECK-GI-NEXT: sub x10, x8, x9248; CHECK-GI-NEXT: sub x11, x9, #64249; CHECK-GI-NEXT: lsr x12, x0, x9250; CHECK-GI-NEXT: lsl x10, x1, x10251; CHECK-GI-NEXT: lsr x11, x1, x11252; CHECK-GI-NEXT: and x14, x13, #0x7f253; CHECK-GI-NEXT: cmp x9, #64254; CHECK-GI-NEXT: sub x8, x8, x14255; CHECK-GI-NEXT: lsl x15, x1, x14256; CHECK-GI-NEXT: orr x10, x12, x10257; CHECK-GI-NEXT: lsr x12, x1, x9258; CHECK-GI-NEXT: lsr x8, x0, x8259; CHECK-GI-NEXT: csel x10, x10, x11, lo260; CHECK-GI-NEXT: sub x11, x14, #64261; CHECK-GI-NEXT: tst x2, #0x7f262; CHECK-GI-NEXT: csel x10, x0, x10, eq263; CHECK-GI-NEXT: cmp x9, #64264; CHECK-GI-NEXT: lsl x9, x0, x14265; CHECK-GI-NEXT: lsl x11, x0, x11266; CHECK-GI-NEXT: csel x12, x12, xzr, lo267; CHECK-GI-NEXT: orr x8, x8, x15268; CHECK-GI-NEXT: cmp x14, #64269; CHECK-GI-NEXT: csel x9, x9, xzr, lo270; CHECK-GI-NEXT: csel x8, x8, x11, lo271; CHECK-GI-NEXT: tst x13, #0x7f272; CHECK-GI-NEXT: csel x8, x1, x8, eq273; CHECK-GI-NEXT: orr x0, x10, x9274; CHECK-GI-NEXT: orr x1, x12, x8275; CHECK-GI-NEXT: ret276entry:277 %d = call i128 @llvm.fshr(i128 %a, i128 %a, i128 %c)278 ret i128 %d279}280 281define i8 @fshl_i8(i8 %a, i8 %b, i8 %c) {282; CHECK-SD-LABEL: fshl_i8:283; CHECK-SD: // %bb.0: // %entry284; CHECK-SD-NEXT: and w8, w2, #0x7285; CHECK-SD-NEXT: ubfiz w9, w1, #23, #8286; CHECK-SD-NEXT: mvn w10, w8287; CHECK-SD-NEXT: lsl w8, w0, w8288; CHECK-SD-NEXT: lsr w9, w9, w10289; CHECK-SD-NEXT: orr w0, w8, w9290; CHECK-SD-NEXT: ret291;292; CHECK-GI-LABEL: fshl_i8:293; CHECK-GI: // %bb.0: // %entry294; CHECK-GI-NEXT: mov w8, #7 // =0x7295; CHECK-GI-NEXT: ubfx w9, w1, #1, #7296; CHECK-GI-NEXT: and w10, w2, #0x7297; CHECK-GI-NEXT: bic w8, w8, w2298; CHECK-GI-NEXT: lsl w10, w0, w10299; CHECK-GI-NEXT: lsr w8, w9, w8300; CHECK-GI-NEXT: orr w0, w10, w8301; CHECK-GI-NEXT: ret302entry:303 %d = call i8 @llvm.fshl(i8 %a, i8 %b, i8 %c)304 ret i8 %d305}306 307define i8 @fshr_i8(i8 %a, i8 %b, i8 %c) {308; CHECK-SD-LABEL: fshr_i8:309; CHECK-SD: // %bb.0: // %entry310; CHECK-SD-NEXT: mov w8, #24 // =0x18311; CHECK-SD-NEXT: lsl w9, w1, #24312; CHECK-SD-NEXT: mvn w10, w2313; CHECK-SD-NEXT: bfxil w8, w2, #0, #3314; CHECK-SD-NEXT: lsl w11, w0, #1315; CHECK-SD-NEXT: and x10, x10, #0x7316; CHECK-SD-NEXT: lsr w8, w9, w8317; CHECK-SD-NEXT: lsl w9, w11, w10318; CHECK-SD-NEXT: orr w0, w9, w8319; CHECK-SD-NEXT: ret320;321; CHECK-GI-LABEL: fshr_i8:322; CHECK-GI: // %bb.0: // %entry323; CHECK-GI-NEXT: mov w8, #7 // =0x7324; CHECK-GI-NEXT: lsl w9, w0, #1325; CHECK-GI-NEXT: and w10, w2, #0x7326; CHECK-GI-NEXT: bic w8, w8, w2327; CHECK-GI-NEXT: and w11, w1, #0xff328; CHECK-GI-NEXT: lsl w8, w9, w8329; CHECK-GI-NEXT: lsr w9, w11, w10330; CHECK-GI-NEXT: orr w0, w8, w9331; CHECK-GI-NEXT: ret332entry:333 %d = call i8 @llvm.fshr(i8 %a, i8 %b, i8 %c)334 ret i8 %d335}336 337define i16 @fshl_i16(i16 %a, i16 %b, i16 %c) {338; CHECK-SD-LABEL: fshl_i16:339; CHECK-SD: // %bb.0: // %entry340; CHECK-SD-NEXT: and w8, w2, #0xf341; CHECK-SD-NEXT: ubfiz w9, w1, #15, #16342; CHECK-SD-NEXT: mvn w10, w8343; CHECK-SD-NEXT: lsl w8, w0, w8344; CHECK-SD-NEXT: lsr w9, w9, w10345; CHECK-SD-NEXT: orr w0, w8, w9346; CHECK-SD-NEXT: ret347;348; CHECK-GI-LABEL: fshl_i16:349; CHECK-GI: // %bb.0: // %entry350; CHECK-GI-NEXT: mov w8, #15 // =0xf351; CHECK-GI-NEXT: ubfx w9, w1, #1, #15352; CHECK-GI-NEXT: and w10, w2, #0xf353; CHECK-GI-NEXT: bic w8, w8, w2354; CHECK-GI-NEXT: lsl w10, w0, w10355; CHECK-GI-NEXT: lsr w8, w9, w8356; CHECK-GI-NEXT: orr w0, w10, w8357; CHECK-GI-NEXT: ret358entry:359 %d = call i16 @llvm.fshl(i16 %a, i16 %b, i16 %c)360 ret i16 %d361}362 363define i16 @fshr_i16(i16 %a, i16 %b, i16 %c) {364; CHECK-SD-LABEL: fshr_i16:365; CHECK-SD: // %bb.0: // %entry366; CHECK-SD-NEXT: mov w8, #16 // =0x10367; CHECK-SD-NEXT: lsl w9, w1, #16368; CHECK-SD-NEXT: mvn w10, w2369; CHECK-SD-NEXT: bfxil w8, w2, #0, #4370; CHECK-SD-NEXT: lsl w11, w0, #1371; CHECK-SD-NEXT: and x10, x10, #0xf372; CHECK-SD-NEXT: lsr w8, w9, w8373; CHECK-SD-NEXT: lsl w9, w11, w10374; CHECK-SD-NEXT: orr w0, w9, w8375; CHECK-SD-NEXT: ret376;377; CHECK-GI-LABEL: fshr_i16:378; CHECK-GI: // %bb.0: // %entry379; CHECK-GI-NEXT: mov w8, #15 // =0xf380; CHECK-GI-NEXT: lsl w9, w0, #1381; CHECK-GI-NEXT: and w10, w2, #0xf382; CHECK-GI-NEXT: bic w8, w8, w2383; CHECK-GI-NEXT: and w11, w1, #0xffff384; CHECK-GI-NEXT: lsl w8, w9, w8385; CHECK-GI-NEXT: lsr w9, w11, w10386; CHECK-GI-NEXT: orr w0, w8, w9387; CHECK-GI-NEXT: ret388entry:389 %d = call i16 @llvm.fshr(i16 %a, i16 %b, i16 %c)390 ret i16 %d391}392 393define i32 @fshl_i32(i32 %a, i32 %b, i32 %c) {394; CHECK-SD-LABEL: fshl_i32:395; CHECK-SD: // %bb.0: // %entry396; CHECK-SD-NEXT: lsr w8, w1, #1397; CHECK-SD-NEXT: mvn w9, w2398; CHECK-SD-NEXT: lsl w10, w0, w2399; CHECK-SD-NEXT: lsr w8, w8, w9400; CHECK-SD-NEXT: orr w0, w10, w8401; CHECK-SD-NEXT: ret402;403; CHECK-GI-LABEL: fshl_i32:404; CHECK-GI: // %bb.0: // %entry405; CHECK-GI-NEXT: mov w8, #31 // =0x1f406; CHECK-GI-NEXT: lsr w9, w1, #1407; CHECK-GI-NEXT: and w10, w2, #0x1f408; CHECK-GI-NEXT: bic w8, w8, w2409; CHECK-GI-NEXT: lsl w10, w0, w10410; CHECK-GI-NEXT: lsr w8, w9, w8411; CHECK-GI-NEXT: orr w0, w10, w8412; CHECK-GI-NEXT: ret413entry:414 %d = call i32 @llvm.fshl(i32 %a, i32 %b, i32 %c)415 ret i32 %d416}417 418define i32 @fshr_i32(i32 %a, i32 %b, i32 %c) {419; CHECK-SD-LABEL: fshr_i32:420; CHECK-SD: // %bb.0: // %entry421; CHECK-SD-NEXT: lsl w8, w0, #1422; CHECK-SD-NEXT: mvn w9, w2423; CHECK-SD-NEXT: lsr w10, w1, w2424; CHECK-SD-NEXT: lsl w8, w8, w9425; CHECK-SD-NEXT: orr w0, w8, w10426; CHECK-SD-NEXT: ret427;428; CHECK-GI-LABEL: fshr_i32:429; CHECK-GI: // %bb.0: // %entry430; CHECK-GI-NEXT: mov w8, #31 // =0x1f431; CHECK-GI-NEXT: lsl w9, w0, #1432; CHECK-GI-NEXT: and w10, w2, #0x1f433; CHECK-GI-NEXT: bic w8, w8, w2434; CHECK-GI-NEXT: lsl w8, w9, w8435; CHECK-GI-NEXT: lsr w9, w1, w10436; CHECK-GI-NEXT: orr w0, w8, w9437; CHECK-GI-NEXT: ret438entry:439 %d = call i32 @llvm.fshr(i32 %a, i32 %b, i32 %c)440 ret i32 %d441}442 443define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) {444; CHECK-SD-LABEL: fshl_i64:445; CHECK-SD: // %bb.0: // %entry446; CHECK-SD-NEXT: lsr x8, x1, #1447; CHECK-SD-NEXT: mvn w9, w2448; CHECK-SD-NEXT: lsl x10, x0, x2449; CHECK-SD-NEXT: lsr x8, x8, x9450; CHECK-SD-NEXT: orr x0, x10, x8451; CHECK-SD-NEXT: ret452;453; CHECK-GI-LABEL: fshl_i64:454; CHECK-GI: // %bb.0: // %entry455; CHECK-GI-NEXT: mov w8, #63 // =0x3f456; CHECK-GI-NEXT: lsr x9, x1, #1457; CHECK-GI-NEXT: and x10, x2, #0x3f458; CHECK-GI-NEXT: bic x8, x8, x2459; CHECK-GI-NEXT: lsl x10, x0, x10460; CHECK-GI-NEXT: lsr x8, x9, x8461; CHECK-GI-NEXT: orr x0, x10, x8462; CHECK-GI-NEXT: ret463entry:464 %d = call i64 @llvm.fshl(i64 %a, i64 %b, i64 %c)465 ret i64 %d466}467 468define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) {469; CHECK-SD-LABEL: fshr_i64:470; CHECK-SD: // %bb.0: // %entry471; CHECK-SD-NEXT: lsl x8, x0, #1472; CHECK-SD-NEXT: mvn w9, w2473; CHECK-SD-NEXT: lsr x10, x1, x2474; CHECK-SD-NEXT: lsl x8, x8, x9475; CHECK-SD-NEXT: orr x0, x8, x10476; CHECK-SD-NEXT: ret477;478; CHECK-GI-LABEL: fshr_i64:479; CHECK-GI: // %bb.0: // %entry480; CHECK-GI-NEXT: mov w8, #63 // =0x3f481; CHECK-GI-NEXT: lsl x9, x0, #1482; CHECK-GI-NEXT: and x10, x2, #0x3f483; CHECK-GI-NEXT: bic x8, x8, x2484; CHECK-GI-NEXT: lsl x8, x9, x8485; CHECK-GI-NEXT: lsr x9, x1, x10486; CHECK-GI-NEXT: orr x0, x8, x9487; CHECK-GI-NEXT: ret488entry:489 %d = call i64 @llvm.fshr(i64 %a, i64 %b, i64 %c)490 ret i64 %d491}492 493define i128 @fshl_i128(i128 %a, i128 %b, i128 %c) {494; CHECK-SD-LABEL: fshl_i128:495; CHECK-SD: // %bb.0: // %entry496; CHECK-SD-NEXT: tst x4, #0x40497; CHECK-SD-NEXT: mvn w11, w4498; CHECK-SD-NEXT: csel x8, x3, x0, ne499; CHECK-SD-NEXT: csel x9, x2, x3, ne500; CHECK-SD-NEXT: csel x12, x0, x1, ne501; CHECK-SD-NEXT: lsr x9, x9, #1502; CHECK-SD-NEXT: lsr x10, x8, #1503; CHECK-SD-NEXT: lsl x8, x8, x4504; CHECK-SD-NEXT: lsl x12, x12, x4505; CHECK-SD-NEXT: lsr x9, x9, x11506; CHECK-SD-NEXT: lsr x10, x10, x11507; CHECK-SD-NEXT: orr x0, x8, x9508; CHECK-SD-NEXT: orr x1, x12, x10509; CHECK-SD-NEXT: ret510;511; CHECK-GI-LABEL: fshl_i128:512; CHECK-GI: // %bb.0: // %entry513; CHECK-GI-NEXT: mov w8, #64 // =0x40514; CHECK-GI-NEXT: and x9, x4, #0x7f515; CHECK-GI-NEXT: mov w10, #127 // =0x7f516; CHECK-GI-NEXT: sub x12, x8, x9517; CHECK-GI-NEXT: lsl x13, x1, x9518; CHECK-GI-NEXT: bic x10, x10, x4519; CHECK-GI-NEXT: lsr x12, x0, x12520; CHECK-GI-NEXT: sub x14, x9, #64521; CHECK-GI-NEXT: lsl x15, x0, x9522; CHECK-GI-NEXT: extr x16, x3, x2, #1523; CHECK-GI-NEXT: cmp x9, #64524; CHECK-GI-NEXT: sub x8, x8, x10525; CHECK-GI-NEXT: orr x9, x12, x13526; CHECK-GI-NEXT: lsr x12, x3, #1527; CHECK-GI-NEXT: lsl x13, x0, x14528; CHECK-GI-NEXT: csel x14, x15, xzr, lo529; CHECK-GI-NEXT: sub x15, x10, #64530; CHECK-GI-NEXT: lsr x17, x16, x10531; CHECK-GI-NEXT: lsl x8, x12, x8532; CHECK-GI-NEXT: csel x9, x9, x13, lo533; CHECK-GI-NEXT: tst x4, #0x7f534; CHECK-GI-NEXT: lsr x13, x12, x15535; CHECK-GI-NEXT: mvn x11, x4536; CHECK-GI-NEXT: csel x9, x1, x9, eq537; CHECK-GI-NEXT: orr x8, x17, x8538; CHECK-GI-NEXT: cmp x10, #64539; CHECK-GI-NEXT: lsr x12, x12, x10540; CHECK-GI-NEXT: csel x8, x8, x13, lo541; CHECK-GI-NEXT: tst x11, #0x7f542; CHECK-GI-NEXT: csel x8, x16, x8, eq543; CHECK-GI-NEXT: cmp x10, #64544; CHECK-GI-NEXT: csel x10, x12, xzr, lo545; CHECK-GI-NEXT: orr x0, x14, x8546; CHECK-GI-NEXT: orr x1, x9, x10547; CHECK-GI-NEXT: ret548entry:549 %d = call i128 @llvm.fshl(i128 %a, i128 %b, i128 %c)550 ret i128 %d551}552 553define i128 @fshr_i128(i128 %a, i128 %b, i128 %c) {554; CHECK-SD-LABEL: fshr_i128:555; CHECK-SD: // %bb.0: // %entry556; CHECK-SD-NEXT: tst x4, #0x40557; CHECK-SD-NEXT: mvn w12, w4558; CHECK-SD-NEXT: csel x8, x3, x0, eq559; CHECK-SD-NEXT: csel x9, x0, x1, eq560; CHECK-SD-NEXT: csel x10, x2, x3, eq561; CHECK-SD-NEXT: lsl x11, x8, #1562; CHECK-SD-NEXT: lsl x9, x9, #1563; CHECK-SD-NEXT: lsr x10, x10, x4564; CHECK-SD-NEXT: lsr x8, x8, x4565; CHECK-SD-NEXT: lsl x11, x11, x12566; CHECK-SD-NEXT: lsl x9, x9, x12567; CHECK-SD-NEXT: orr x0, x11, x10568; CHECK-SD-NEXT: orr x1, x9, x8569; CHECK-SD-NEXT: ret570;571; CHECK-GI-LABEL: fshr_i128:572; CHECK-GI: // %bb.0: // %entry573; CHECK-GI-NEXT: mov w8, #127 // =0x7f574; CHECK-GI-NEXT: lsl x9, x0, #1575; CHECK-GI-NEXT: extr x10, x1, x0, #63576; CHECK-GI-NEXT: bic x8, x8, x4577; CHECK-GI-NEXT: mov w11, #64 // =0x40578; CHECK-GI-NEXT: and x14, x4, #0x7f579; CHECK-GI-NEXT: sub x12, x11, x8580; CHECK-GI-NEXT: lsl x13, x10, x8581; CHECK-GI-NEXT: lsl x16, x9, x8582; CHECK-GI-NEXT: lsr x12, x9, x12583; CHECK-GI-NEXT: sub x17, x8, #64584; CHECK-GI-NEXT: cmp x8, #64585; CHECK-GI-NEXT: lsl x8, x9, x17586; CHECK-GI-NEXT: sub x11, x11, x14587; CHECK-GI-NEXT: mvn x15, x4588; CHECK-GI-NEXT: orr x12, x12, x13589; CHECK-GI-NEXT: csel x9, x16, xzr, lo590; CHECK-GI-NEXT: sub x13, x14, #64591; CHECK-GI-NEXT: lsr x16, x2, x14592; CHECK-GI-NEXT: lsl x11, x3, x11593; CHECK-GI-NEXT: csel x8, x12, x8, lo594; CHECK-GI-NEXT: tst x15, #0x7f595; CHECK-GI-NEXT: lsr x12, x3, x13596; CHECK-GI-NEXT: csel x8, x10, x8, eq597; CHECK-GI-NEXT: orr x10, x16, x11598; CHECK-GI-NEXT: cmp x14, #64599; CHECK-GI-NEXT: lsr x11, x3, x14600; CHECK-GI-NEXT: csel x10, x10, x12, lo601; CHECK-GI-NEXT: tst x4, #0x7f602; CHECK-GI-NEXT: csel x10, x2, x10, eq603; CHECK-GI-NEXT: cmp x14, #64604; CHECK-GI-NEXT: csel x11, x11, xzr, lo605; CHECK-GI-NEXT: orr x0, x9, x10606; CHECK-GI-NEXT: orr x1, x8, x11607; CHECK-GI-NEXT: ret608entry:609 %d = call i128 @llvm.fshr(i128 %a, i128 %b, i128 %c)610 ret i128 %d611}612 613define i8 @rotl_i8_c(i8 %a) {614; CHECK-LABEL: rotl_i8_c:615; CHECK: // %bb.0: // %entry616; CHECK-NEXT: ubfx w8, w0, #5, #3617; CHECK-NEXT: orr w0, w8, w0, lsl #3618; CHECK-NEXT: ret619entry:620 %d = call i8 @llvm.fshl(i8 %a, i8 %a, i8 3)621 ret i8 %d622}623 624define i8 @rotr_i8_c(i8 %a) {625; CHECK-SD-LABEL: rotr_i8_c:626; CHECK-SD: // %bb.0: // %entry627; CHECK-SD-NEXT: lsl w8, w0, #5628; CHECK-SD-NEXT: bfxil w8, w0, #3, #5629; CHECK-SD-NEXT: mov w0, w8630; CHECK-SD-NEXT: ret631;632; CHECK-GI-LABEL: rotr_i8_c:633; CHECK-GI: // %bb.0: // %entry634; CHECK-GI-NEXT: ubfx w8, w0, #3, #5635; CHECK-GI-NEXT: orr w0, w8, w0, lsl #5636; CHECK-GI-NEXT: ret637entry:638 %d = call i8 @llvm.fshr(i8 %a, i8 %a, i8 3)639 ret i8 %d640}641 642define i16 @rotl_i16_c(i16 %a) {643; CHECK-LABEL: rotl_i16_c:644; CHECK: // %bb.0: // %entry645; CHECK-NEXT: ubfx w8, w0, #13, #3646; CHECK-NEXT: orr w0, w8, w0, lsl #3647; CHECK-NEXT: ret648entry:649 %d = call i16 @llvm.fshl(i16 %a, i16 %a, i16 3)650 ret i16 %d651}652 653define i16 @rotr_i16_c(i16 %a) {654; CHECK-SD-LABEL: rotr_i16_c:655; CHECK-SD: // %bb.0: // %entry656; CHECK-SD-NEXT: lsl w8, w0, #13657; CHECK-SD-NEXT: bfxil w8, w0, #3, #13658; CHECK-SD-NEXT: mov w0, w8659; CHECK-SD-NEXT: ret660;661; CHECK-GI-LABEL: rotr_i16_c:662; CHECK-GI: // %bb.0: // %entry663; CHECK-GI-NEXT: ubfx w8, w0, #3, #13664; CHECK-GI-NEXT: orr w0, w8, w0, lsl #13665; CHECK-GI-NEXT: ret666entry:667 %d = call i16 @llvm.fshr(i16 %a, i16 %a, i16 3)668 ret i16 %d669}670 671define i32 @rotl_i32_c(i32 %a) {672; CHECK-LABEL: rotl_i32_c:673; CHECK: // %bb.0: // %entry674; CHECK-NEXT: ror w0, w0, #29675; CHECK-NEXT: ret676entry:677 %d = call i32 @llvm.fshl(i32 %a, i32 %a, i32 3)678 ret i32 %d679}680 681define i32 @rotr_i32_c(i32 %a) {682; CHECK-LABEL: rotr_i32_c:683; CHECK: // %bb.0: // %entry684; CHECK-NEXT: ror w0, w0, #3685; CHECK-NEXT: ret686entry:687 %d = call i32 @llvm.fshr(i32 %a, i32 %a, i32 3)688 ret i32 %d689}690 691define i64 @rotl_i64_c(i64 %a) {692; CHECK-LABEL: rotl_i64_c:693; CHECK: // %bb.0: // %entry694; CHECK-NEXT: ror x0, x0, #61695; CHECK-NEXT: ret696entry:697 %d = call i64 @llvm.fshl(i64 %a, i64 %a, i64 3)698 ret i64 %d699}700 701define i64 @rotr_i64_c(i64 %a) {702; CHECK-LABEL: rotr_i64_c:703; CHECK: // %bb.0: // %entry704; CHECK-NEXT: ror x0, x0, #3705; CHECK-NEXT: ret706entry:707 %d = call i64 @llvm.fshr(i64 %a, i64 %a, i64 3)708 ret i64 %d709}710 711define i128 @rotl_i128_c(i128 %a) {712; CHECK-SD-LABEL: rotl_i128_c:713; CHECK-SD: // %bb.0: // %entry714; CHECK-SD-NEXT: extr x8, x0, x1, #61715; CHECK-SD-NEXT: extr x1, x1, x0, #61716; CHECK-SD-NEXT: mov x0, x8717; CHECK-SD-NEXT: ret718;719; CHECK-GI-LABEL: rotl_i128_c:720; CHECK-GI: // %bb.0: // %entry721; CHECK-GI-NEXT: extr x8, x1, x0, #61722; CHECK-GI-NEXT: extr x0, x0, x1, #61723; CHECK-GI-NEXT: mov x1, x8724; CHECK-GI-NEXT: ret725entry:726 %d = call i128 @llvm.fshl(i128 %a, i128 %a, i128 3)727 ret i128 %d728}729 730define i128 @rotr_i128_c(i128 %a) {731; CHECK-LABEL: rotr_i128_c:732; CHECK: // %bb.0: // %entry733; CHECK-NEXT: extr x8, x1, x0, #3734; CHECK-NEXT: extr x1, x0, x1, #3735; CHECK-NEXT: mov x0, x8736; CHECK-NEXT: ret737entry:738 %d = call i128 @llvm.fshr(i128 %a, i128 %a, i128 3)739 ret i128 %d740}741 742define i8 @fshl_i8_c(i8 %a, i8 %b) {743; CHECK-SD-LABEL: fshl_i8_c:744; CHECK-SD: // %bb.0: // %entry745; CHECK-SD-NEXT: lsl w8, w1, #24746; CHECK-SD-NEXT: extr w0, w0, w8, #29747; CHECK-SD-NEXT: ret748;749; CHECK-GI-LABEL: fshl_i8_c:750; CHECK-GI: // %bb.0: // %entry751; CHECK-GI-NEXT: ubfx w8, w1, #5, #3752; CHECK-GI-NEXT: orr w0, w8, w0, lsl #3753; CHECK-GI-NEXT: ret754entry:755 %d = call i8 @llvm.fshl(i8 %a, i8 %b, i8 3)756 ret i8 %d757}758 759define i8 @fshr_i8_c(i8 %a, i8 %b) {760; CHECK-SD-LABEL: fshr_i8_c:761; CHECK-SD: // %bb.0: // %entry762; CHECK-SD-NEXT: lsl w8, w1, #24763; CHECK-SD-NEXT: extr w0, w0, w8, #27764; CHECK-SD-NEXT: ret765;766; CHECK-GI-LABEL: fshr_i8_c:767; CHECK-GI: // %bb.0: // %entry768; CHECK-GI-NEXT: ubfx w8, w1, #3, #5769; CHECK-GI-NEXT: orr w0, w8, w0, lsl #5770; CHECK-GI-NEXT: ret771entry:772 %d = call i8 @llvm.fshr(i8 %a, i8 %b, i8 3)773 ret i8 %d774}775 776define i16 @fshl_i16_c(i16 %a, i16 %b) {777; CHECK-SD-LABEL: fshl_i16_c:778; CHECK-SD: // %bb.0: // %entry779; CHECK-SD-NEXT: lsl w8, w1, #16780; CHECK-SD-NEXT: extr w0, w0, w8, #29781; CHECK-SD-NEXT: ret782;783; CHECK-GI-LABEL: fshl_i16_c:784; CHECK-GI: // %bb.0: // %entry785; CHECK-GI-NEXT: ubfx w8, w1, #13, #3786; CHECK-GI-NEXT: orr w0, w8, w0, lsl #3787; CHECK-GI-NEXT: ret788entry:789 %d = call i16 @llvm.fshl(i16 %a, i16 %b, i16 3)790 ret i16 %d791}792 793define i16 @fshr_i16_c(i16 %a, i16 %b) {794; CHECK-SD-LABEL: fshr_i16_c:795; CHECK-SD: // %bb.0: // %entry796; CHECK-SD-NEXT: lsl w8, w1, #16797; CHECK-SD-NEXT: extr w0, w0, w8, #19798; CHECK-SD-NEXT: ret799;800; CHECK-GI-LABEL: fshr_i16_c:801; CHECK-GI: // %bb.0: // %entry802; CHECK-GI-NEXT: ubfx w8, w1, #3, #13803; CHECK-GI-NEXT: orr w0, w8, w0, lsl #13804; CHECK-GI-NEXT: ret805entry:806 %d = call i16 @llvm.fshr(i16 %a, i16 %b, i16 3)807 ret i16 %d808}809 810define i32 @fshl_i32_c(i32 %a, i32 %b) {811; CHECK-LABEL: fshl_i32_c:812; CHECK: // %bb.0: // %entry813; CHECK-NEXT: extr w0, w0, w1, #29814; CHECK-NEXT: ret815entry:816 %d = call i32 @llvm.fshl(i32 %a, i32 %b, i32 3)817 ret i32 %d818}819 820define i32 @fshr_i32_c(i32 %a, i32 %b) {821; CHECK-LABEL: fshr_i32_c:822; CHECK: // %bb.0: // %entry823; CHECK-NEXT: extr w0, w0, w1, #3824; CHECK-NEXT: ret825entry:826 %d = call i32 @llvm.fshr(i32 %a, i32 %b, i32 3)827 ret i32 %d828}829 830define i64 @fshl_i64_c(i64 %a, i64 %b) {831; CHECK-LABEL: fshl_i64_c:832; CHECK: // %bb.0: // %entry833; CHECK-NEXT: extr x0, x0, x1, #61834; CHECK-NEXT: ret835entry:836 %d = call i64 @llvm.fshl(i64 %a, i64 %b, i64 3)837 ret i64 %d838}839 840define i64 @fshr_i64_c(i64 %a, i64 %b) {841; CHECK-LABEL: fshr_i64_c:842; CHECK: // %bb.0: // %entry843; CHECK-NEXT: extr x0, x0, x1, #3844; CHECK-NEXT: ret845entry:846 %d = call i64 @llvm.fshr(i64 %a, i64 %b, i64 3)847 ret i64 %d848}849 850define i128 @fshl_i128_c(i128 %a, i128 %b) {851; CHECK-SD-LABEL: fshl_i128_c:852; CHECK-SD: // %bb.0: // %entry853; CHECK-SD-NEXT: extr x8, x0, x3, #61854; CHECK-SD-NEXT: extr x1, x1, x0, #61855; CHECK-SD-NEXT: mov x0, x8856; CHECK-SD-NEXT: ret857;858; CHECK-GI-LABEL: fshl_i128_c:859; CHECK-GI: // %bb.0: // %entry860; CHECK-GI-NEXT: extr x1, x1, x0, #61861; CHECK-GI-NEXT: extr x0, x0, x3, #61862; CHECK-GI-NEXT: ret863entry:864 %d = call i128 @llvm.fshl(i128 %a, i128 %b, i128 3)865 ret i128 %d866}867 868define i128 @fshr_i128_c(i128 %a, i128 %b) {869; CHECK-LABEL: fshr_i128_c:870; CHECK: // %bb.0: // %entry871; CHECK-NEXT: extr x8, x3, x2, #3872; CHECK-NEXT: extr x1, x0, x3, #3873; CHECK-NEXT: mov x0, x8874; CHECK-NEXT: ret875entry:876 %d = call i128 @llvm.fshr(i128 %a, i128 %b, i128 3)877 ret i128 %d878}879 880define <8 x i8> @rotl_v8i8(<8 x i8> %a, <8 x i8> %c) {881; CHECK-LABEL: rotl_v8i8:882; CHECK: // %bb.0: // %entry883; CHECK-NEXT: movi v2.8b, #7884; CHECK-NEXT: neg v3.8b, v1.8b885; CHECK-NEXT: and v3.8b, v3.8b, v2.8b886; CHECK-NEXT: and v1.8b, v1.8b, v2.8b887; CHECK-NEXT: neg v2.8b, v3.8b888; CHECK-NEXT: ushl v1.8b, v0.8b, v1.8b889; CHECK-NEXT: ushl v0.8b, v0.8b, v2.8b890; CHECK-NEXT: orr v0.8b, v1.8b, v0.8b891; CHECK-NEXT: ret892entry:893 %d = call <8 x i8> @llvm.fshl(<8 x i8> %a, <8 x i8> %a, <8 x i8> %c)894 ret <8 x i8> %d895}896 897define <8 x i8> @rotr_v8i8(<8 x i8> %a, <8 x i8> %c) {898; CHECK-SD-LABEL: rotr_v8i8:899; CHECK-SD: // %bb.0: // %entry900; CHECK-SD-NEXT: movi v2.8b, #7901; CHECK-SD-NEXT: neg v3.8b, v1.8b902; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b903; CHECK-SD-NEXT: and v2.8b, v3.8b, v2.8b904; CHECK-SD-NEXT: neg v1.8b, v1.8b905; CHECK-SD-NEXT: ushl v2.8b, v0.8b, v2.8b906; CHECK-SD-NEXT: ushl v0.8b, v0.8b, v1.8b907; CHECK-SD-NEXT: orr v0.8b, v0.8b, v2.8b908; CHECK-SD-NEXT: ret909;910; CHECK-GI-LABEL: rotr_v8i8:911; CHECK-GI: // %bb.0: // %entry912; CHECK-GI-NEXT: movi v2.8b, #7913; CHECK-GI-NEXT: neg v3.8b, v1.8b914; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b915; CHECK-GI-NEXT: and v2.8b, v3.8b, v2.8b916; CHECK-GI-NEXT: neg v1.8b, v1.8b917; CHECK-GI-NEXT: ushl v1.8b, v0.8b, v1.8b918; CHECK-GI-NEXT: ushl v0.8b, v0.8b, v2.8b919; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b920; CHECK-GI-NEXT: ret921entry:922 %d = call <8 x i8> @llvm.fshr(<8 x i8> %a, <8 x i8> %a, <8 x i8> %c)923 ret <8 x i8> %d924}925 926define <16 x i8> @rotl_v16i8(<16 x i8> %a, <16 x i8> %c) {927; CHECK-LABEL: rotl_v16i8:928; CHECK: // %bb.0: // %entry929; CHECK-NEXT: movi v2.16b, #7930; CHECK-NEXT: neg v3.16b, v1.16b931; CHECK-NEXT: and v3.16b, v3.16b, v2.16b932; CHECK-NEXT: and v1.16b, v1.16b, v2.16b933; CHECK-NEXT: neg v2.16b, v3.16b934; CHECK-NEXT: ushl v1.16b, v0.16b, v1.16b935; CHECK-NEXT: ushl v0.16b, v0.16b, v2.16b936; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b937; CHECK-NEXT: ret938entry:939 %d = call <16 x i8> @llvm.fshl(<16 x i8> %a, <16 x i8> %a, <16 x i8> %c)940 ret <16 x i8> %d941}942 943define <16 x i8> @rotr_v16i8(<16 x i8> %a, <16 x i8> %c) {944; CHECK-SD-LABEL: rotr_v16i8:945; CHECK-SD: // %bb.0: // %entry946; CHECK-SD-NEXT: movi v2.16b, #7947; CHECK-SD-NEXT: neg v3.16b, v1.16b948; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b949; CHECK-SD-NEXT: and v2.16b, v3.16b, v2.16b950; CHECK-SD-NEXT: neg v1.16b, v1.16b951; CHECK-SD-NEXT: ushl v2.16b, v0.16b, v2.16b952; CHECK-SD-NEXT: ushl v0.16b, v0.16b, v1.16b953; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b954; CHECK-SD-NEXT: ret955;956; CHECK-GI-LABEL: rotr_v16i8:957; CHECK-GI: // %bb.0: // %entry958; CHECK-GI-NEXT: movi v2.16b, #7959; CHECK-GI-NEXT: neg v3.16b, v1.16b960; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b961; CHECK-GI-NEXT: and v2.16b, v3.16b, v2.16b962; CHECK-GI-NEXT: neg v1.16b, v1.16b963; CHECK-GI-NEXT: ushl v1.16b, v0.16b, v1.16b964; CHECK-GI-NEXT: ushl v0.16b, v0.16b, v2.16b965; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b966; CHECK-GI-NEXT: ret967entry:968 %d = call <16 x i8> @llvm.fshr(<16 x i8> %a, <16 x i8> %a, <16 x i8> %c)969 ret <16 x i8> %d970}971 972define <4 x i16> @rotl_v4i16(<4 x i16> %a, <4 x i16> %c) {973; CHECK-LABEL: rotl_v4i16:974; CHECK: // %bb.0: // %entry975; CHECK-NEXT: movi v2.4h, #15976; CHECK-NEXT: neg v3.4h, v1.4h977; CHECK-NEXT: and v3.8b, v3.8b, v2.8b978; CHECK-NEXT: and v1.8b, v1.8b, v2.8b979; CHECK-NEXT: neg v2.4h, v3.4h980; CHECK-NEXT: ushl v1.4h, v0.4h, v1.4h981; CHECK-NEXT: ushl v0.4h, v0.4h, v2.4h982; CHECK-NEXT: orr v0.8b, v1.8b, v0.8b983; CHECK-NEXT: ret984entry:985 %d = call <4 x i16> @llvm.fshl(<4 x i16> %a, <4 x i16> %a, <4 x i16> %c)986 ret <4 x i16> %d987}988 989define <4 x i16> @rotr_v4i16(<4 x i16> %a, <4 x i16> %c) {990; CHECK-SD-LABEL: rotr_v4i16:991; CHECK-SD: // %bb.0: // %entry992; CHECK-SD-NEXT: movi v2.4h, #15993; CHECK-SD-NEXT: neg v3.4h, v1.4h994; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b995; CHECK-SD-NEXT: and v2.8b, v3.8b, v2.8b996; CHECK-SD-NEXT: neg v1.4h, v1.4h997; CHECK-SD-NEXT: ushl v2.4h, v0.4h, v2.4h998; CHECK-SD-NEXT: ushl v0.4h, v0.4h, v1.4h999; CHECK-SD-NEXT: orr v0.8b, v0.8b, v2.8b1000; CHECK-SD-NEXT: ret1001;1002; CHECK-GI-LABEL: rotr_v4i16:1003; CHECK-GI: // %bb.0: // %entry1004; CHECK-GI-NEXT: movi v2.4h, #151005; CHECK-GI-NEXT: neg v3.4h, v1.4h1006; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b1007; CHECK-GI-NEXT: and v2.8b, v3.8b, v2.8b1008; CHECK-GI-NEXT: neg v1.4h, v1.4h1009; CHECK-GI-NEXT: ushl v1.4h, v0.4h, v1.4h1010; CHECK-GI-NEXT: ushl v0.4h, v0.4h, v2.4h1011; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b1012; CHECK-GI-NEXT: ret1013entry:1014 %d = call <4 x i16> @llvm.fshr(<4 x i16> %a, <4 x i16> %a, <4 x i16> %c)1015 ret <4 x i16> %d1016}1017 1018define <7 x i16> @rotl_v7i16(<7 x i16> %a, <7 x i16> %c) {1019; CHECK-SD-LABEL: rotl_v7i16:1020; CHECK-SD: // %bb.0: // %entry1021; CHECK-SD-NEXT: movi v2.8h, #151022; CHECK-SD-NEXT: neg v3.8h, v1.8h1023; CHECK-SD-NEXT: and v3.16b, v3.16b, v2.16b1024; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b1025; CHECK-SD-NEXT: neg v2.8h, v3.8h1026; CHECK-SD-NEXT: ushl v1.8h, v0.8h, v1.8h1027; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h1028; CHECK-SD-NEXT: orr v0.16b, v1.16b, v0.16b1029; CHECK-SD-NEXT: ret1030;1031; CHECK-GI-LABEL: rotl_v7i16:1032; CHECK-GI: // %bb.0: // %entry1033; CHECK-GI-NEXT: mov w8, #0 // =0x01034; CHECK-GI-NEXT: mov w9, #15 // =0xf1035; CHECK-GI-NEXT: fmov s2, w81036; CHECK-GI-NEXT: fmov s3, w91037; CHECK-GI-NEXT: mov v2.h[1], w81038; CHECK-GI-NEXT: mov v3.h[1], w91039; CHECK-GI-NEXT: mov v2.h[2], w81040; CHECK-GI-NEXT: mov v3.h[2], w91041; CHECK-GI-NEXT: mov v2.h[3], w81042; CHECK-GI-NEXT: mov v3.h[3], w91043; CHECK-GI-NEXT: mov v2.h[4], w81044; CHECK-GI-NEXT: mov v3.h[4], w91045; CHECK-GI-NEXT: mov v2.h[5], w81046; CHECK-GI-NEXT: mov v3.h[5], w91047; CHECK-GI-NEXT: mov v2.h[6], w81048; CHECK-GI-NEXT: mov v3.h[6], w91049; CHECK-GI-NEXT: sub v2.8h, v2.8h, v1.8h1050; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b1051; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b1052; CHECK-GI-NEXT: ushl v1.8h, v0.8h, v1.8h1053; CHECK-GI-NEXT: neg v2.8h, v2.8h1054; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h1055; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b1056; CHECK-GI-NEXT: ret1057entry:1058 %d = call <7 x i16> @llvm.fshl(<7 x i16> %a, <7 x i16> %a, <7 x i16> %c)1059 ret <7 x i16> %d1060}1061 1062define <7 x i16> @rotr_v7i16(<7 x i16> %a, <7 x i16> %c) {1063; CHECK-SD-LABEL: rotr_v7i16:1064; CHECK-SD: // %bb.0: // %entry1065; CHECK-SD-NEXT: movi v2.8h, #151066; CHECK-SD-NEXT: neg v3.8h, v1.8h1067; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b1068; CHECK-SD-NEXT: and v2.16b, v3.16b, v2.16b1069; CHECK-SD-NEXT: neg v1.8h, v1.8h1070; CHECK-SD-NEXT: ushl v2.8h, v0.8h, v2.8h1071; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v1.8h1072; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b1073; CHECK-SD-NEXT: ret1074;1075; CHECK-GI-LABEL: rotr_v7i16:1076; CHECK-GI: // %bb.0: // %entry1077; CHECK-GI-NEXT: mov w8, #0 // =0x01078; CHECK-GI-NEXT: mov w9, #15 // =0xf1079; CHECK-GI-NEXT: fmov s2, w81080; CHECK-GI-NEXT: fmov s3, w91081; CHECK-GI-NEXT: mov v2.h[1], w81082; CHECK-GI-NEXT: mov v3.h[1], w91083; CHECK-GI-NEXT: mov v2.h[2], w81084; CHECK-GI-NEXT: mov v3.h[2], w91085; CHECK-GI-NEXT: mov v2.h[3], w81086; CHECK-GI-NEXT: mov v3.h[3], w91087; CHECK-GI-NEXT: mov v2.h[4], w81088; CHECK-GI-NEXT: mov v3.h[4], w91089; CHECK-GI-NEXT: mov v2.h[5], w81090; CHECK-GI-NEXT: mov v3.h[5], w91091; CHECK-GI-NEXT: mov v2.h[6], w81092; CHECK-GI-NEXT: mov v3.h[6], w91093; CHECK-GI-NEXT: sub v2.8h, v2.8h, v1.8h1094; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b1095; CHECK-GI-NEXT: neg v1.8h, v1.8h1096; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b1097; CHECK-GI-NEXT: ushl v1.8h, v0.8h, v1.8h1098; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h1099; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b1100; CHECK-GI-NEXT: ret1101entry:1102 %d = call <7 x i16> @llvm.fshr(<7 x i16> %a, <7 x i16> %a, <7 x i16> %c)1103 ret <7 x i16> %d1104}1105 1106define <8 x i16> @rotl_v8i16(<8 x i16> %a, <8 x i16> %c) {1107; CHECK-LABEL: rotl_v8i16:1108; CHECK: // %bb.0: // %entry1109; CHECK-NEXT: movi v2.8h, #151110; CHECK-NEXT: neg v3.8h, v1.8h1111; CHECK-NEXT: and v3.16b, v3.16b, v2.16b1112; CHECK-NEXT: and v1.16b, v1.16b, v2.16b1113; CHECK-NEXT: neg v2.8h, v3.8h1114; CHECK-NEXT: ushl v1.8h, v0.8h, v1.8h1115; CHECK-NEXT: ushl v0.8h, v0.8h, v2.8h1116; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b1117; CHECK-NEXT: ret1118entry:1119 %d = call <8 x i16> @llvm.fshl(<8 x i16> %a, <8 x i16> %a, <8 x i16> %c)1120 ret <8 x i16> %d1121}1122 1123define <8 x i16> @rotr_v8i16(<8 x i16> %a, <8 x i16> %c) {1124; CHECK-SD-LABEL: rotr_v8i16:1125; CHECK-SD: // %bb.0: // %entry1126; CHECK-SD-NEXT: movi v2.8h, #151127; CHECK-SD-NEXT: neg v3.8h, v1.8h1128; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b1129; CHECK-SD-NEXT: and v2.16b, v3.16b, v2.16b1130; CHECK-SD-NEXT: neg v1.8h, v1.8h1131; CHECK-SD-NEXT: ushl v2.8h, v0.8h, v2.8h1132; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v1.8h1133; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b1134; CHECK-SD-NEXT: ret1135;1136; CHECK-GI-LABEL: rotr_v8i16:1137; CHECK-GI: // %bb.0: // %entry1138; CHECK-GI-NEXT: movi v2.8h, #151139; CHECK-GI-NEXT: neg v3.8h, v1.8h1140; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b1141; CHECK-GI-NEXT: and v2.16b, v3.16b, v2.16b1142; CHECK-GI-NEXT: neg v1.8h, v1.8h1143; CHECK-GI-NEXT: ushl v1.8h, v0.8h, v1.8h1144; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h1145; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b1146; CHECK-GI-NEXT: ret1147entry:1148 %d = call <8 x i16> @llvm.fshr(<8 x i16> %a, <8 x i16> %a, <8 x i16> %c)1149 ret <8 x i16> %d1150}1151 1152define <16 x i16> @rotl_v16i16(<16 x i16> %a, <16 x i16> %c) {1153; CHECK-LABEL: rotl_v16i16:1154; CHECK: // %bb.0: // %entry1155; CHECK-NEXT: movi v4.8h, #151156; CHECK-NEXT: neg v5.8h, v2.8h1157; CHECK-NEXT: neg v6.8h, v3.8h1158; CHECK-NEXT: and v5.16b, v5.16b, v4.16b1159; CHECK-NEXT: and v6.16b, v6.16b, v4.16b1160; CHECK-NEXT: and v2.16b, v2.16b, v4.16b1161; CHECK-NEXT: and v3.16b, v3.16b, v4.16b1162; CHECK-NEXT: neg v4.8h, v5.8h1163; CHECK-NEXT: neg v5.8h, v6.8h1164; CHECK-NEXT: ushl v2.8h, v0.8h, v2.8h1165; CHECK-NEXT: ushl v3.8h, v1.8h, v3.8h1166; CHECK-NEXT: ushl v0.8h, v0.8h, v4.8h1167; CHECK-NEXT: ushl v1.8h, v1.8h, v5.8h1168; CHECK-NEXT: orr v0.16b, v2.16b, v0.16b1169; CHECK-NEXT: orr v1.16b, v3.16b, v1.16b1170; CHECK-NEXT: ret1171entry:1172 %d = call <16 x i16> @llvm.fshl(<16 x i16> %a, <16 x i16> %a, <16 x i16> %c)1173 ret <16 x i16> %d1174}1175 1176define <16 x i16> @rotr_v16i16(<16 x i16> %a, <16 x i16> %c) {1177; CHECK-SD-LABEL: rotr_v16i16:1178; CHECK-SD: // %bb.0: // %entry1179; CHECK-SD-NEXT: movi v4.8h, #151180; CHECK-SD-NEXT: neg v5.8h, v2.8h1181; CHECK-SD-NEXT: neg v6.8h, v3.8h1182; CHECK-SD-NEXT: and v2.16b, v2.16b, v4.16b1183; CHECK-SD-NEXT: and v3.16b, v3.16b, v4.16b1184; CHECK-SD-NEXT: and v5.16b, v5.16b, v4.16b1185; CHECK-SD-NEXT: and v4.16b, v6.16b, v4.16b1186; CHECK-SD-NEXT: neg v2.8h, v2.8h1187; CHECK-SD-NEXT: neg v3.8h, v3.8h1188; CHECK-SD-NEXT: ushl v5.8h, v0.8h, v5.8h1189; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h1190; CHECK-SD-NEXT: ushl v2.8h, v1.8h, v4.8h1191; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v3.8h1192; CHECK-SD-NEXT: orr v0.16b, v0.16b, v5.16b1193; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b1194; CHECK-SD-NEXT: ret1195;1196; CHECK-GI-LABEL: rotr_v16i16:1197; CHECK-GI: // %bb.0: // %entry1198; CHECK-GI-NEXT: movi v4.8h, #151199; CHECK-GI-NEXT: neg v6.8h, v3.8h1200; CHECK-GI-NEXT: and v5.16b, v2.16b, v4.16b1201; CHECK-GI-NEXT: neg v2.8h, v2.8h1202; CHECK-GI-NEXT: and v3.16b, v3.16b, v4.16b1203; CHECK-GI-NEXT: neg v5.8h, v5.8h1204; CHECK-GI-NEXT: and v2.16b, v2.16b, v4.16b1205; CHECK-GI-NEXT: and v4.16b, v6.16b, v4.16b1206; CHECK-GI-NEXT: neg v3.8h, v3.8h1207; CHECK-GI-NEXT: ushl v5.8h, v0.8h, v5.8h1208; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h1209; CHECK-GI-NEXT: ushl v3.8h, v1.8h, v3.8h1210; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v4.8h1211; CHECK-GI-NEXT: orr v0.16b, v5.16b, v0.16b1212; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b1213; CHECK-GI-NEXT: ret1214entry:1215 %d = call <16 x i16> @llvm.fshr(<16 x i16> %a, <16 x i16> %a, <16 x i16> %c)1216 ret <16 x i16> %d1217}1218 1219define <2 x i32> @rotl_v2i32(<2 x i32> %a, <2 x i32> %c) {1220; CHECK-LABEL: rotl_v2i32:1221; CHECK: // %bb.0: // %entry1222; CHECK-NEXT: movi v2.2s, #311223; CHECK-NEXT: neg v3.2s, v1.2s1224; CHECK-NEXT: and v3.8b, v3.8b, v2.8b1225; CHECK-NEXT: and v1.8b, v1.8b, v2.8b1226; CHECK-NEXT: neg v2.2s, v3.2s1227; CHECK-NEXT: ushl v1.2s, v0.2s, v1.2s1228; CHECK-NEXT: ushl v0.2s, v0.2s, v2.2s1229; CHECK-NEXT: orr v0.8b, v1.8b, v0.8b1230; CHECK-NEXT: ret1231entry:1232 %d = call <2 x i32> @llvm.fshl(<2 x i32> %a, <2 x i32> %a, <2 x i32> %c)1233 ret <2 x i32> %d1234}1235 1236define <2 x i32> @rotr_v2i32(<2 x i32> %a, <2 x i32> %c) {1237; CHECK-SD-LABEL: rotr_v2i32:1238; CHECK-SD: // %bb.0: // %entry1239; CHECK-SD-NEXT: movi v2.2s, #311240; CHECK-SD-NEXT: neg v3.2s, v1.2s1241; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b1242; CHECK-SD-NEXT: and v2.8b, v3.8b, v2.8b1243; CHECK-SD-NEXT: neg v1.2s, v1.2s1244; CHECK-SD-NEXT: ushl v2.2s, v0.2s, v2.2s1245; CHECK-SD-NEXT: ushl v0.2s, v0.2s, v1.2s1246; CHECK-SD-NEXT: orr v0.8b, v0.8b, v2.8b1247; CHECK-SD-NEXT: ret1248;1249; CHECK-GI-LABEL: rotr_v2i32:1250; CHECK-GI: // %bb.0: // %entry1251; CHECK-GI-NEXT: movi v2.2s, #311252; CHECK-GI-NEXT: neg v3.2s, v1.2s1253; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b1254; CHECK-GI-NEXT: and v2.8b, v3.8b, v2.8b1255; CHECK-GI-NEXT: neg v1.2s, v1.2s1256; CHECK-GI-NEXT: ushl v1.2s, v0.2s, v1.2s1257; CHECK-GI-NEXT: ushl v0.2s, v0.2s, v2.2s1258; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b1259; CHECK-GI-NEXT: ret1260entry:1261 %d = call <2 x i32> @llvm.fshr(<2 x i32> %a, <2 x i32> %a, <2 x i32> %c)1262 ret <2 x i32> %d1263}1264 1265define <4 x i32> @rotl_v4i32(<4 x i32> %a, <4 x i32> %c) {1266; CHECK-LABEL: rotl_v4i32:1267; CHECK: // %bb.0: // %entry1268; CHECK-NEXT: movi v2.4s, #311269; CHECK-NEXT: neg v3.4s, v1.4s1270; CHECK-NEXT: and v3.16b, v3.16b, v2.16b1271; CHECK-NEXT: and v1.16b, v1.16b, v2.16b1272; CHECK-NEXT: neg v2.4s, v3.4s1273; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s1274; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s1275; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b1276; CHECK-NEXT: ret1277entry:1278 %d = call <4 x i32> @llvm.fshl(<4 x i32> %a, <4 x i32> %a, <4 x i32> %c)1279 ret <4 x i32> %d1280}1281 1282define <4 x i32> @rotr_v4i32(<4 x i32> %a, <4 x i32> %c) {1283; CHECK-SD-LABEL: rotr_v4i32:1284; CHECK-SD: // %bb.0: // %entry1285; CHECK-SD-NEXT: movi v2.4s, #311286; CHECK-SD-NEXT: neg v3.4s, v1.4s1287; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b1288; CHECK-SD-NEXT: and v2.16b, v3.16b, v2.16b1289; CHECK-SD-NEXT: neg v1.4s, v1.4s1290; CHECK-SD-NEXT: ushl v2.4s, v0.4s, v2.4s1291; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v1.4s1292; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b1293; CHECK-SD-NEXT: ret1294;1295; CHECK-GI-LABEL: rotr_v4i32:1296; CHECK-GI: // %bb.0: // %entry1297; CHECK-GI-NEXT: movi v2.4s, #311298; CHECK-GI-NEXT: neg v3.4s, v1.4s1299; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b1300; CHECK-GI-NEXT: and v2.16b, v3.16b, v2.16b1301; CHECK-GI-NEXT: neg v1.4s, v1.4s1302; CHECK-GI-NEXT: ushl v1.4s, v0.4s, v1.4s1303; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v2.4s1304; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b1305; CHECK-GI-NEXT: ret1306entry:1307 %d = call <4 x i32> @llvm.fshr(<4 x i32> %a, <4 x i32> %a, <4 x i32> %c)1308 ret <4 x i32> %d1309}1310 1311define <7 x i32> @rotl_v7i32(<7 x i32> %a, <7 x i32> %c) {1312; CHECK-SD-LABEL: rotl_v7i32:1313; CHECK-SD: // %bb.0: // %entry1314; CHECK-SD-NEXT: fmov s0, w71315; CHECK-SD-NEXT: mov x8, sp1316; CHECK-SD-NEXT: ldr s1, [sp, #24]1317; CHECK-SD-NEXT: fmov s2, w01318; CHECK-SD-NEXT: add x9, sp, #401319; CHECK-SD-NEXT: fmov s5, w41320; CHECK-SD-NEXT: movi v3.4s, #311321; CHECK-SD-NEXT: ld1 { v0.s }[1], [x8]1322; CHECK-SD-NEXT: add x8, sp, #81323; CHECK-SD-NEXT: mov v2.s[1], w11324; CHECK-SD-NEXT: mov v5.s[1], w51325; CHECK-SD-NEXT: ld1 { v0.s }[2], [x8]1326; CHECK-SD-NEXT: add x8, sp, #321327; CHECK-SD-NEXT: ld1 { v1.s }[1], [x8]1328; CHECK-SD-NEXT: add x8, sp, #161329; CHECK-SD-NEXT: mov v2.s[2], w21330; CHECK-SD-NEXT: mov v5.s[2], w61331; CHECK-SD-NEXT: ld1 { v0.s }[3], [x8]1332; CHECK-SD-NEXT: ld1 { v1.s }[2], [x9]1333; CHECK-SD-NEXT: neg v4.4s, v0.4s1334; CHECK-SD-NEXT: mov v2.s[3], w31335; CHECK-SD-NEXT: and v0.16b, v0.16b, v3.16b1336; CHECK-SD-NEXT: neg v6.4s, v1.4s1337; CHECK-SD-NEXT: and v1.16b, v1.16b, v3.16b1338; CHECK-SD-NEXT: and v4.16b, v4.16b, v3.16b1339; CHECK-SD-NEXT: and v6.16b, v6.16b, v3.16b1340; CHECK-SD-NEXT: ushl v0.4s, v2.4s, v0.4s1341; CHECK-SD-NEXT: ushl v1.4s, v5.4s, v1.4s1342; CHECK-SD-NEXT: neg v4.4s, v4.4s1343; CHECK-SD-NEXT: neg v3.4s, v6.4s1344; CHECK-SD-NEXT: ushl v2.4s, v2.4s, v4.4s1345; CHECK-SD-NEXT: ushl v3.4s, v5.4s, v3.4s1346; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b1347; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b1348; CHECK-SD-NEXT: mov w1, v0.s[1]1349; CHECK-SD-NEXT: mov w2, v0.s[2]1350; CHECK-SD-NEXT: mov w3, v0.s[3]1351; CHECK-SD-NEXT: mov w5, v1.s[1]1352; CHECK-SD-NEXT: mov w6, v1.s[2]1353; CHECK-SD-NEXT: fmov w0, s01354; CHECK-SD-NEXT: fmov w4, s11355; CHECK-SD-NEXT: ret1356;1357; CHECK-GI-LABEL: rotl_v7i32:1358; CHECK-GI: // %bb.0: // %entry1359; CHECK-GI-NEXT: ldr s0, [sp, #24]1360; CHECK-GI-NEXT: movi d1, #00000000000000001361; CHECK-GI-NEXT: fmov s3, w71362; CHECK-GI-NEXT: ldr s2, [sp, #32]1363; CHECK-GI-NEXT: mov x8, sp1364; CHECK-GI-NEXT: fmov s4, w71365; CHECK-GI-NEXT: mov v6.16b, v0.16b1366; CHECK-GI-NEXT: ldr s7, [sp]1367; CHECK-GI-NEXT: ldr s5, [sp, #40]1368; CHECK-GI-NEXT: ld1 { v3.s }[1], [x8]1369; CHECK-GI-NEXT: add x8, sp, #81370; CHECK-GI-NEXT: fmov s16, w01371; CHECK-GI-NEXT: mov v1.s[1], wzr1372; CHECK-GI-NEXT: mov v4.s[1], v7.s[0]1373; CHECK-GI-NEXT: ldr s7, [sp, #8]1374; CHECK-GI-NEXT: mov v6.s[1], v2.s[0]1375; CHECK-GI-NEXT: fmov s17, w01376; CHECK-GI-NEXT: add x9, sp, #161377; CHECK-GI-NEXT: ld1 { v3.s }[2], [x8]1378; CHECK-GI-NEXT: mov w8, #31 // =0x1f1379; CHECK-GI-NEXT: mov v16.s[1], w11380; CHECK-GI-NEXT: fmov s18, w81381; CHECK-GI-NEXT: mov v0.s[1], v2.s[0]1382; CHECK-GI-NEXT: fmov s2, w41383; CHECK-GI-NEXT: mov v1.s[2], wzr1384; CHECK-GI-NEXT: mov v4.s[2], v7.s[0]1385; CHECK-GI-NEXT: ldr s7, [sp, #16]1386; CHECK-GI-NEXT: mov v6.s[2], v5.s[0]1387; CHECK-GI-NEXT: ld1 { v3.s }[3], [x9]1388; CHECK-GI-NEXT: mov v17.s[1], w11389; CHECK-GI-NEXT: mov v18.s[1], w81390; CHECK-GI-NEXT: movi v19.4s, #311391; CHECK-GI-NEXT: mov v16.s[2], w21392; CHECK-GI-NEXT: mov v2.s[1], w51393; CHECK-GI-NEXT: mov v0.s[2], v5.s[0]1394; CHECK-GI-NEXT: mov v4.s[3], v7.s[0]1395; CHECK-GI-NEXT: fmov s7, w41396; CHECK-GI-NEXT: neg v3.4s, v3.4s1397; CHECK-GI-NEXT: sub v1.4s, v1.4s, v6.4s1398; CHECK-GI-NEXT: fmov s6, w81399; CHECK-GI-NEXT: mov v17.s[2], w21400; CHECK-GI-NEXT: mov v18.s[2], w81401; CHECK-GI-NEXT: mov v16.s[3], w31402; CHECK-GI-NEXT: mov v7.s[1], w51403; CHECK-GI-NEXT: and v3.16b, v3.16b, v19.16b1404; CHECK-GI-NEXT: mov v2.s[2], w61405; CHECK-GI-NEXT: mov v6.s[1], w81406; CHECK-GI-NEXT: and v4.16b, v4.16b, v19.16b1407; CHECK-GI-NEXT: mov v17.s[3], w31408; CHECK-GI-NEXT: and v1.16b, v1.16b, v18.16b1409; CHECK-GI-NEXT: neg v3.4s, v3.4s1410; CHECK-GI-NEXT: mov v7.s[2], w61411; CHECK-GI-NEXT: mov v6.s[2], w81412; CHECK-GI-NEXT: neg v1.4s, v1.4s1413; CHECK-GI-NEXT: ushl v4.4s, v17.4s, v4.4s1414; CHECK-GI-NEXT: ushl v3.4s, v16.4s, v3.4s1415; CHECK-GI-NEXT: and v0.16b, v0.16b, v6.16b1416; CHECK-GI-NEXT: ushl v1.4s, v2.4s, v1.4s1417; CHECK-GI-NEXT: orr v2.16b, v4.16b, v3.16b1418; CHECK-GI-NEXT: ushl v0.4s, v7.4s, v0.4s1419; CHECK-GI-NEXT: mov s3, v2.s[2]1420; CHECK-GI-NEXT: mov s4, v2.s[3]1421; CHECK-GI-NEXT: fmov w0, s21422; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b1423; CHECK-GI-NEXT: mov s1, v2.s[1]1424; CHECK-GI-NEXT: fmov w2, s31425; CHECK-GI-NEXT: fmov w3, s41426; CHECK-GI-NEXT: mov s5, v0.s[1]1427; CHECK-GI-NEXT: mov s6, v0.s[2]1428; CHECK-GI-NEXT: fmov w4, s01429; CHECK-GI-NEXT: fmov w1, s11430; CHECK-GI-NEXT: fmov w5, s51431; CHECK-GI-NEXT: fmov w6, s61432; CHECK-GI-NEXT: ret1433entry:1434 %d = call <7 x i32> @llvm.fshl(<7 x i32> %a, <7 x i32> %a, <7 x i32> %c)1435 ret <7 x i32> %d1436}1437 1438define <7 x i32> @rotr_v7i32(<7 x i32> %a, <7 x i32> %c) {1439; CHECK-SD-LABEL: rotr_v7i32:1440; CHECK-SD: // %bb.0: // %entry1441; CHECK-SD-NEXT: fmov s0, w71442; CHECK-SD-NEXT: mov x8, sp1443; CHECK-SD-NEXT: fmov s2, w01444; CHECK-SD-NEXT: ldr s1, [sp, #24]1445; CHECK-SD-NEXT: add x9, sp, #321446; CHECK-SD-NEXT: fmov s4, w41447; CHECK-SD-NEXT: movi v3.4s, #311448; CHECK-SD-NEXT: ld1 { v0.s }[1], [x8]1449; CHECK-SD-NEXT: add x8, sp, #81450; CHECK-SD-NEXT: mov v2.s[1], w11451; CHECK-SD-NEXT: ld1 { v1.s }[1], [x9]1452; CHECK-SD-NEXT: add x9, sp, #401453; CHECK-SD-NEXT: mov v4.s[1], w51454; CHECK-SD-NEXT: ld1 { v0.s }[2], [x8]1455; CHECK-SD-NEXT: add x8, sp, #161456; CHECK-SD-NEXT: ld1 { v1.s }[2], [x9]1457; CHECK-SD-NEXT: mov v2.s[2], w21458; CHECK-SD-NEXT: mov v4.s[2], w61459; CHECK-SD-NEXT: ld1 { v0.s }[3], [x8]1460; CHECK-SD-NEXT: neg v6.4s, v1.4s1461; CHECK-SD-NEXT: and v1.16b, v1.16b, v3.16b1462; CHECK-SD-NEXT: mov v2.s[3], w31463; CHECK-SD-NEXT: neg v5.4s, v0.4s1464; CHECK-SD-NEXT: and v0.16b, v0.16b, v3.16b1465; CHECK-SD-NEXT: neg v1.4s, v1.4s1466; CHECK-SD-NEXT: and v5.16b, v5.16b, v3.16b1467; CHECK-SD-NEXT: neg v0.4s, v0.4s1468; CHECK-SD-NEXT: and v3.16b, v6.16b, v3.16b1469; CHECK-SD-NEXT: ushl v1.4s, v4.4s, v1.4s1470; CHECK-SD-NEXT: ushl v5.4s, v2.4s, v5.4s1471; CHECK-SD-NEXT: ushl v0.4s, v2.4s, v0.4s1472; CHECK-SD-NEXT: ushl v2.4s, v4.4s, v3.4s1473; CHECK-SD-NEXT: orr v0.16b, v0.16b, v5.16b1474; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b1475; CHECK-SD-NEXT: mov w1, v0.s[1]1476; CHECK-SD-NEXT: mov w2, v0.s[2]1477; CHECK-SD-NEXT: mov w3, v0.s[3]1478; CHECK-SD-NEXT: mov w5, v1.s[1]1479; CHECK-SD-NEXT: mov w6, v1.s[2]1480; CHECK-SD-NEXT: fmov w0, s01481; CHECK-SD-NEXT: fmov w4, s11482; CHECK-SD-NEXT: ret1483;1484; CHECK-GI-LABEL: rotr_v7i32:1485; CHECK-GI: // %bb.0: // %entry1486; CHECK-GI-NEXT: fmov s1, w71487; CHECK-GI-NEXT: ldr s3, [sp]1488; CHECK-GI-NEXT: fmov s2, w71489; CHECK-GI-NEXT: mov x8, sp1490; CHECK-GI-NEXT: ldr s6, [sp, #8]1491; CHECK-GI-NEXT: movi d0, #00000000000000001492; CHECK-GI-NEXT: ldr s7, [sp, #32]1493; CHECK-GI-NEXT: fmov s16, w01494; CHECK-GI-NEXT: fmov s17, w01495; CHECK-GI-NEXT: mov v1.s[1], v3.s[0]1496; CHECK-GI-NEXT: ldr s3, [sp, #24]1497; CHECK-GI-NEXT: ld1 { v2.s }[1], [x8]1498; CHECK-GI-NEXT: mov w8, #31 // =0x1f1499; CHECK-GI-NEXT: add x9, sp, #81500; CHECK-GI-NEXT: ldr s5, [sp, #40]1501; CHECK-GI-NEXT: mov v4.16b, v3.16b1502; CHECK-GI-NEXT: mov v3.s[1], v7.s[0]1503; CHECK-GI-NEXT: mov v0.s[1], wzr1504; CHECK-GI-NEXT: fmov s18, w81505; CHECK-GI-NEXT: ld1 { v2.s }[2], [x9]1506; CHECK-GI-NEXT: mov v17.s[1], w11507; CHECK-GI-NEXT: mov v1.s[2], v6.s[0]1508; CHECK-GI-NEXT: fmov s6, w81509; CHECK-GI-NEXT: mov v16.s[1], w11510; CHECK-GI-NEXT: mov v4.s[1], v7.s[0]1511; CHECK-GI-NEXT: ldr s7, [sp, #16]1512; CHECK-GI-NEXT: fmov s19, w41513; CHECK-GI-NEXT: mov v18.s[1], w81514; CHECK-GI-NEXT: mov v3.s[2], v5.s[0]1515; CHECK-GI-NEXT: add x10, sp, #161516; CHECK-GI-NEXT: mov v6.s[1], w81517; CHECK-GI-NEXT: mov v0.s[2], wzr1518; CHECK-GI-NEXT: ld1 { v2.s }[3], [x10]1519; CHECK-GI-NEXT: mov v1.s[3], v7.s[0]1520; CHECK-GI-NEXT: movi v7.4s, #311521; CHECK-GI-NEXT: mov v17.s[2], w21522; CHECK-GI-NEXT: mov v4.s[2], v5.s[0]1523; CHECK-GI-NEXT: fmov s5, w41524; CHECK-GI-NEXT: mov v16.s[2], w21525; CHECK-GI-NEXT: mov v19.s[1], w51526; CHECK-GI-NEXT: mov v18.s[2], w81527; CHECK-GI-NEXT: neg v2.4s, v2.4s1528; CHECK-GI-NEXT: mov v6.s[2], w81529; CHECK-GI-NEXT: mov v5.s[1], w51530; CHECK-GI-NEXT: and v1.16b, v1.16b, v7.16b1531; CHECK-GI-NEXT: mov v17.s[3], w31532; CHECK-GI-NEXT: sub v0.4s, v0.4s, v4.4s1533; CHECK-GI-NEXT: mov v16.s[3], w31534; CHECK-GI-NEXT: and v2.16b, v2.16b, v7.16b1535; CHECK-GI-NEXT: mov v19.s[2], w61536; CHECK-GI-NEXT: and v3.16b, v3.16b, v6.16b1537; CHECK-GI-NEXT: neg v1.4s, v1.4s1538; CHECK-GI-NEXT: mov v5.s[2], w61539; CHECK-GI-NEXT: and v0.16b, v0.16b, v18.16b1540; CHECK-GI-NEXT: ushl v2.4s, v16.4s, v2.4s1541; CHECK-GI-NEXT: neg v3.4s, v3.4s1542; CHECK-GI-NEXT: ushl v1.4s, v17.4s, v1.4s1543; CHECK-GI-NEXT: ushl v0.4s, v5.4s, v0.4s1544; CHECK-GI-NEXT: ushl v3.4s, v19.4s, v3.4s1545; CHECK-GI-NEXT: orr v1.16b, v1.16b, v2.16b1546; CHECK-GI-NEXT: orr v0.16b, v3.16b, v0.16b1547; CHECK-GI-NEXT: mov s2, v1.s[1]1548; CHECK-GI-NEXT: mov s3, v1.s[2]1549; CHECK-GI-NEXT: mov s4, v1.s[3]1550; CHECK-GI-NEXT: fmov w0, s11551; CHECK-GI-NEXT: mov s5, v0.s[1]1552; CHECK-GI-NEXT: mov s6, v0.s[2]1553; CHECK-GI-NEXT: fmov w4, s01554; CHECK-GI-NEXT: fmov w1, s21555; CHECK-GI-NEXT: fmov w2, s31556; CHECK-GI-NEXT: fmov w3, s41557; CHECK-GI-NEXT: fmov w5, s51558; CHECK-GI-NEXT: fmov w6, s61559; CHECK-GI-NEXT: ret1560entry:1561 %d = call <7 x i32> @llvm.fshr(<7 x i32> %a, <7 x i32> %a, <7 x i32> %c)1562 ret <7 x i32> %d1563}1564 1565define <8 x i32> @rotl_v8i32(<8 x i32> %a, <8 x i32> %c) {1566; CHECK-LABEL: rotl_v8i32:1567; CHECK: // %bb.0: // %entry1568; CHECK-NEXT: movi v4.4s, #311569; CHECK-NEXT: neg v5.4s, v2.4s1570; CHECK-NEXT: neg v6.4s, v3.4s1571; CHECK-NEXT: and v5.16b, v5.16b, v4.16b1572; CHECK-NEXT: and v6.16b, v6.16b, v4.16b1573; CHECK-NEXT: and v2.16b, v2.16b, v4.16b1574; CHECK-NEXT: and v3.16b, v3.16b, v4.16b1575; CHECK-NEXT: neg v4.4s, v5.4s1576; CHECK-NEXT: neg v5.4s, v6.4s1577; CHECK-NEXT: ushl v2.4s, v0.4s, v2.4s1578; CHECK-NEXT: ushl v3.4s, v1.4s, v3.4s1579; CHECK-NEXT: ushl v0.4s, v0.4s, v4.4s1580; CHECK-NEXT: ushl v1.4s, v1.4s, v5.4s1581; CHECK-NEXT: orr v0.16b, v2.16b, v0.16b1582; CHECK-NEXT: orr v1.16b, v3.16b, v1.16b1583; CHECK-NEXT: ret1584entry:1585 %d = call <8 x i32> @llvm.fshl(<8 x i32> %a, <8 x i32> %a, <8 x i32> %c)1586 ret <8 x i32> %d1587}1588 1589define <8 x i32> @rotr_v8i32(<8 x i32> %a, <8 x i32> %c) {1590; CHECK-SD-LABEL: rotr_v8i32:1591; CHECK-SD: // %bb.0: // %entry1592; CHECK-SD-NEXT: movi v4.4s, #311593; CHECK-SD-NEXT: neg v5.4s, v2.4s1594; CHECK-SD-NEXT: neg v6.4s, v3.4s1595; CHECK-SD-NEXT: and v2.16b, v2.16b, v4.16b1596; CHECK-SD-NEXT: and v3.16b, v3.16b, v4.16b1597; CHECK-SD-NEXT: and v5.16b, v5.16b, v4.16b1598; CHECK-SD-NEXT: and v4.16b, v6.16b, v4.16b1599; CHECK-SD-NEXT: neg v2.4s, v2.4s1600; CHECK-SD-NEXT: neg v3.4s, v3.4s1601; CHECK-SD-NEXT: ushl v5.4s, v0.4s, v5.4s1602; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v2.4s1603; CHECK-SD-NEXT: ushl v2.4s, v1.4s, v4.4s1604; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v3.4s1605; CHECK-SD-NEXT: orr v0.16b, v0.16b, v5.16b1606; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b1607; CHECK-SD-NEXT: ret1608;1609; CHECK-GI-LABEL: rotr_v8i32:1610; CHECK-GI: // %bb.0: // %entry1611; CHECK-GI-NEXT: movi v4.4s, #311612; CHECK-GI-NEXT: neg v6.4s, v3.4s1613; CHECK-GI-NEXT: and v5.16b, v2.16b, v4.16b1614; CHECK-GI-NEXT: neg v2.4s, v2.4s1615; CHECK-GI-NEXT: and v3.16b, v3.16b, v4.16b1616; CHECK-GI-NEXT: neg v5.4s, v5.4s1617; CHECK-GI-NEXT: and v2.16b, v2.16b, v4.16b1618; CHECK-GI-NEXT: and v4.16b, v6.16b, v4.16b1619; CHECK-GI-NEXT: neg v3.4s, v3.4s1620; CHECK-GI-NEXT: ushl v5.4s, v0.4s, v5.4s1621; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v2.4s1622; CHECK-GI-NEXT: ushl v3.4s, v1.4s, v3.4s1623; CHECK-GI-NEXT: ushl v1.4s, v1.4s, v4.4s1624; CHECK-GI-NEXT: orr v0.16b, v5.16b, v0.16b1625; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b1626; CHECK-GI-NEXT: ret1627entry:1628 %d = call <8 x i32> @llvm.fshr(<8 x i32> %a, <8 x i32> %a, <8 x i32> %c)1629 ret <8 x i32> %d1630}1631 1632define <2 x i64> @rotl_v2i64(<2 x i64> %a, <2 x i64> %c) {1633; CHECK-SD-LABEL: rotl_v2i64:1634; CHECK-SD: // %bb.0: // %entry1635; CHECK-SD-NEXT: mov w8, #63 // =0x3f1636; CHECK-SD-NEXT: neg v3.2d, v1.2d1637; CHECK-SD-NEXT: dup v2.2d, x81638; CHECK-SD-NEXT: and v3.16b, v3.16b, v2.16b1639; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b1640; CHECK-SD-NEXT: neg v2.2d, v3.2d1641; CHECK-SD-NEXT: ushl v1.2d, v0.2d, v1.2d1642; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v2.2d1643; CHECK-SD-NEXT: orr v0.16b, v1.16b, v0.16b1644; CHECK-SD-NEXT: ret1645;1646; CHECK-GI-LABEL: rotl_v2i64:1647; CHECK-GI: // %bb.0: // %entry1648; CHECK-GI-NEXT: adrp x8, .LCPI60_01649; CHECK-GI-NEXT: neg v2.2d, v1.2d1650; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI60_0]1651; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b1652; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b1653; CHECK-GI-NEXT: neg v2.2d, v2.2d1654; CHECK-GI-NEXT: ushl v1.2d, v0.2d, v1.2d1655; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v2.2d1656; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b1657; CHECK-GI-NEXT: ret1658entry:1659 %d = call <2 x i64> @llvm.fshl(<2 x i64> %a, <2 x i64> %a, <2 x i64> %c)1660 ret <2 x i64> %d1661}1662 1663define <2 x i64> @rotr_v2i64(<2 x i64> %a, <2 x i64> %c) {1664; CHECK-SD-LABEL: rotr_v2i64:1665; CHECK-SD: // %bb.0: // %entry1666; CHECK-SD-NEXT: mov w8, #63 // =0x3f1667; CHECK-SD-NEXT: neg v3.2d, v1.2d1668; CHECK-SD-NEXT: dup v2.2d, x81669; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b1670; CHECK-SD-NEXT: and v2.16b, v3.16b, v2.16b1671; CHECK-SD-NEXT: neg v1.2d, v1.2d1672; CHECK-SD-NEXT: ushl v2.2d, v0.2d, v2.2d1673; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v1.2d1674; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b1675; CHECK-SD-NEXT: ret1676;1677; CHECK-GI-LABEL: rotr_v2i64:1678; CHECK-GI: // %bb.0: // %entry1679; CHECK-GI-NEXT: adrp x8, .LCPI61_01680; CHECK-GI-NEXT: neg v3.2d, v1.2d1681; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI61_0]1682; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b1683; CHECK-GI-NEXT: and v2.16b, v3.16b, v2.16b1684; CHECK-GI-NEXT: neg v1.2d, v1.2d1685; CHECK-GI-NEXT: ushl v1.2d, v0.2d, v1.2d1686; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v2.2d1687; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b1688; CHECK-GI-NEXT: ret1689entry:1690 %d = call <2 x i64> @llvm.fshr(<2 x i64> %a, <2 x i64> %a, <2 x i64> %c)1691 ret <2 x i64> %d1692}1693 1694define <4 x i64> @rotl_v4i64(<4 x i64> %a, <4 x i64> %c) {1695; CHECK-SD-LABEL: rotl_v4i64:1696; CHECK-SD: // %bb.0: // %entry1697; CHECK-SD-NEXT: mov w8, #63 // =0x3f1698; CHECK-SD-NEXT: neg v5.2d, v2.2d1699; CHECK-SD-NEXT: neg v6.2d, v3.2d1700; CHECK-SD-NEXT: dup v4.2d, x81701; CHECK-SD-NEXT: and v5.16b, v5.16b, v4.16b1702; CHECK-SD-NEXT: and v6.16b, v6.16b, v4.16b1703; CHECK-SD-NEXT: and v2.16b, v2.16b, v4.16b1704; CHECK-SD-NEXT: and v3.16b, v3.16b, v4.16b1705; CHECK-SD-NEXT: neg v4.2d, v5.2d1706; CHECK-SD-NEXT: neg v5.2d, v6.2d1707; CHECK-SD-NEXT: ushl v2.2d, v0.2d, v2.2d1708; CHECK-SD-NEXT: ushl v3.2d, v1.2d, v3.2d1709; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v4.2d1710; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v5.2d1711; CHECK-SD-NEXT: orr v0.16b, v2.16b, v0.16b1712; CHECK-SD-NEXT: orr v1.16b, v3.16b, v1.16b1713; CHECK-SD-NEXT: ret1714;1715; CHECK-GI-LABEL: rotl_v4i64:1716; CHECK-GI: // %bb.0: // %entry1717; CHECK-GI-NEXT: adrp x8, .LCPI62_01718; CHECK-GI-NEXT: neg v4.2d, v2.2d1719; CHECK-GI-NEXT: neg v5.2d, v3.2d1720; CHECK-GI-NEXT: ldr q6, [x8, :lo12:.LCPI62_0]1721; CHECK-GI-NEXT: and v4.16b, v4.16b, v6.16b1722; CHECK-GI-NEXT: and v5.16b, v5.16b, v6.16b1723; CHECK-GI-NEXT: and v2.16b, v2.16b, v6.16b1724; CHECK-GI-NEXT: and v3.16b, v3.16b, v6.16b1725; CHECK-GI-NEXT: neg v4.2d, v4.2d1726; CHECK-GI-NEXT: neg v5.2d, v5.2d1727; CHECK-GI-NEXT: ushl v2.2d, v0.2d, v2.2d1728; CHECK-GI-NEXT: ushl v3.2d, v1.2d, v3.2d1729; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v4.2d1730; CHECK-GI-NEXT: ushl v1.2d, v1.2d, v5.2d1731; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b1732; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b1733; CHECK-GI-NEXT: ret1734entry:1735 %d = call <4 x i64> @llvm.fshl(<4 x i64> %a, <4 x i64> %a, <4 x i64> %c)1736 ret <4 x i64> %d1737}1738 1739define <4 x i64> @rotr_v4i64(<4 x i64> %a, <4 x i64> %c) {1740; CHECK-SD-LABEL: rotr_v4i64:1741; CHECK-SD: // %bb.0: // %entry1742; CHECK-SD-NEXT: mov w8, #63 // =0x3f1743; CHECK-SD-NEXT: neg v5.2d, v2.2d1744; CHECK-SD-NEXT: neg v6.2d, v3.2d1745; CHECK-SD-NEXT: dup v4.2d, x81746; CHECK-SD-NEXT: and v2.16b, v2.16b, v4.16b1747; CHECK-SD-NEXT: and v3.16b, v3.16b, v4.16b1748; CHECK-SD-NEXT: and v5.16b, v5.16b, v4.16b1749; CHECK-SD-NEXT: and v4.16b, v6.16b, v4.16b1750; CHECK-SD-NEXT: neg v2.2d, v2.2d1751; CHECK-SD-NEXT: neg v3.2d, v3.2d1752; CHECK-SD-NEXT: ushl v5.2d, v0.2d, v5.2d1753; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v2.2d1754; CHECK-SD-NEXT: ushl v2.2d, v1.2d, v4.2d1755; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v3.2d1756; CHECK-SD-NEXT: orr v0.16b, v0.16b, v5.16b1757; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b1758; CHECK-SD-NEXT: ret1759;1760; CHECK-GI-LABEL: rotr_v4i64:1761; CHECK-GI: // %bb.0: // %entry1762; CHECK-GI-NEXT: adrp x8, .LCPI63_01763; CHECK-GI-NEXT: neg v6.2d, v3.2d1764; CHECK-GI-NEXT: ldr q4, [x8, :lo12:.LCPI63_0]1765; CHECK-GI-NEXT: and v5.16b, v2.16b, v4.16b1766; CHECK-GI-NEXT: neg v2.2d, v2.2d1767; CHECK-GI-NEXT: and v3.16b, v3.16b, v4.16b1768; CHECK-GI-NEXT: neg v5.2d, v5.2d1769; CHECK-GI-NEXT: and v2.16b, v2.16b, v4.16b1770; CHECK-GI-NEXT: and v4.16b, v6.16b, v4.16b1771; CHECK-GI-NEXT: neg v3.2d, v3.2d1772; CHECK-GI-NEXT: ushl v5.2d, v0.2d, v5.2d1773; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v2.2d1774; CHECK-GI-NEXT: ushl v3.2d, v1.2d, v3.2d1775; CHECK-GI-NEXT: ushl v1.2d, v1.2d, v4.2d1776; CHECK-GI-NEXT: orr v0.16b, v5.16b, v0.16b1777; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b1778; CHECK-GI-NEXT: ret1779entry:1780 %d = call <4 x i64> @llvm.fshr(<4 x i64> %a, <4 x i64> %a, <4 x i64> %c)1781 ret <4 x i64> %d1782}1783 1784define <2 x i128> @rotl_v2i128(<2 x i128> %a, <2 x i128> %c) {1785; CHECK-SD-LABEL: rotl_v2i128:1786; CHECK-SD: // %bb.0: // %entry1787; CHECK-SD-NEXT: tst x4, #0x401788; CHECK-SD-NEXT: mvn w9, w41789; CHECK-SD-NEXT: csel x8, x1, x0, ne1790; CHECK-SD-NEXT: csel x10, x0, x1, ne1791; CHECK-SD-NEXT: tst x6, #0x401792; CHECK-SD-NEXT: lsl x11, x8, x41793; CHECK-SD-NEXT: lsr x12, x10, #11794; CHECK-SD-NEXT: lsr x8, x8, #11795; CHECK-SD-NEXT: csel x13, x3, x2, ne1796; CHECK-SD-NEXT: csel x14, x2, x3, ne1797; CHECK-SD-NEXT: lsl x10, x10, x41798; CHECK-SD-NEXT: lsr x15, x14, #11799; CHECK-SD-NEXT: lsr x16, x13, #11800; CHECK-SD-NEXT: lsr x12, x12, x91801; CHECK-SD-NEXT: lsr x8, x8, x91802; CHECK-SD-NEXT: lsl x9, x13, x61803; CHECK-SD-NEXT: mvn w13, w61804; CHECK-SD-NEXT: lsr x15, x15, x131805; CHECK-SD-NEXT: lsl x14, x14, x61806; CHECK-SD-NEXT: lsr x13, x16, x131807; CHECK-SD-NEXT: orr x0, x11, x121808; CHECK-SD-NEXT: orr x1, x10, x81809; CHECK-SD-NEXT: orr x2, x9, x151810; CHECK-SD-NEXT: orr x3, x14, x131811; CHECK-SD-NEXT: ret1812;1813; CHECK-GI-LABEL: rotl_v2i128:1814; CHECK-GI: // %bb.0: // %entry1815; CHECK-GI-NEXT: and x8, x4, #0x7f1816; CHECK-GI-NEXT: mov w9, #64 // =0x401817; CHECK-GI-NEXT: neg x13, x41818; CHECK-GI-NEXT: sub x10, x9, x81819; CHECK-GI-NEXT: lsl x12, x1, x81820; CHECK-GI-NEXT: sub x11, x8, #641821; CHECK-GI-NEXT: lsr x10, x0, x101822; CHECK-GI-NEXT: lsl x14, x0, x81823; CHECK-GI-NEXT: lsl x11, x0, x111824; CHECK-GI-NEXT: cmp x8, #641825; CHECK-GI-NEXT: neg x15, x61826; CHECK-GI-NEXT: orr x8, x10, x121827; CHECK-GI-NEXT: and x10, x6, #0x7f1828; CHECK-GI-NEXT: csel x12, x14, xzr, lo1829; CHECK-GI-NEXT: sub x14, x9, x101830; CHECK-GI-NEXT: csel x8, x8, x11, lo1831; CHECK-GI-NEXT: tst x4, #0x7f1832; CHECK-GI-NEXT: sub x11, x10, #641833; CHECK-GI-NEXT: lsl x16, x2, x101834; CHECK-GI-NEXT: lsr x14, x2, x141835; CHECK-GI-NEXT: lsl x17, x3, x101836; CHECK-GI-NEXT: csel x8, x1, x8, eq1837; CHECK-GI-NEXT: lsl x11, x2, x111838; CHECK-GI-NEXT: cmp x10, #641839; CHECK-GI-NEXT: and x4, x15, #0x7f1840; CHECK-GI-NEXT: orr x10, x14, x171841; CHECK-GI-NEXT: csel x14, x16, xzr, lo1842; CHECK-GI-NEXT: and x16, x13, #0x7f1843; CHECK-GI-NEXT: csel x10, x10, x11, lo1844; CHECK-GI-NEXT: sub x11, x9, x161845; CHECK-GI-NEXT: sub x17, x16, #641846; CHECK-GI-NEXT: lsr x18, x0, x161847; CHECK-GI-NEXT: lsl x11, x1, x111848; CHECK-GI-NEXT: tst x6, #0x7f1849; CHECK-GI-NEXT: lsr x17, x1, x171850; CHECK-GI-NEXT: csel x10, x3, x10, eq1851; CHECK-GI-NEXT: cmp x16, #641852; CHECK-GI-NEXT: orr x11, x18, x111853; CHECK-GI-NEXT: sub x9, x9, x41854; CHECK-GI-NEXT: lsr x1, x1, x161855; CHECK-GI-NEXT: csel x11, x11, x17, lo1856; CHECK-GI-NEXT: tst x13, #0x7f1857; CHECK-GI-NEXT: sub x13, x4, #641858; CHECK-GI-NEXT: lsr x17, x2, x41859; CHECK-GI-NEXT: lsl x9, x3, x91860; CHECK-GI-NEXT: csel x11, x0, x11, eq1861; CHECK-GI-NEXT: cmp x16, #641862; CHECK-GI-NEXT: lsr x13, x3, x131863; CHECK-GI-NEXT: orr x0, x12, x111864; CHECK-GI-NEXT: csel x16, x1, xzr, lo1865; CHECK-GI-NEXT: orr x9, x17, x91866; CHECK-GI-NEXT: cmp x4, #641867; CHECK-GI-NEXT: lsr x17, x3, x41868; CHECK-GI-NEXT: csel x9, x9, x13, lo1869; CHECK-GI-NEXT: tst x15, #0x7f1870; CHECK-GI-NEXT: csel x9, x2, x9, eq1871; CHECK-GI-NEXT: cmp x4, #641872; CHECK-GI-NEXT: orr x1, x8, x161873; CHECK-GI-NEXT: csel x13, x17, xzr, lo1874; CHECK-GI-NEXT: orr x2, x14, x91875; CHECK-GI-NEXT: orr x3, x10, x131876; CHECK-GI-NEXT: ret1877entry:1878 %d = call <2 x i128> @llvm.fshl(<2 x i128> %a, <2 x i128> %a, <2 x i128> %c)1879 ret <2 x i128> %d1880}1881 1882define <2 x i128> @rotr_v2i128(<2 x i128> %a, <2 x i128> %c) {1883; CHECK-SD-LABEL: rotr_v2i128:1884; CHECK-SD: // %bb.0: // %entry1885; CHECK-SD-NEXT: tst x4, #0x401886; CHECK-SD-NEXT: mvn w9, w41887; CHECK-SD-NEXT: csel x8, x0, x1, eq1888; CHECK-SD-NEXT: csel x10, x1, x0, eq1889; CHECK-SD-NEXT: tst x6, #0x401890; CHECK-SD-NEXT: lsr x11, x8, x41891; CHECK-SD-NEXT: lsl x12, x10, #11892; CHECK-SD-NEXT: lsl x8, x8, #11893; CHECK-SD-NEXT: csel x13, x2, x3, eq1894; CHECK-SD-NEXT: csel x14, x3, x2, eq1895; CHECK-SD-NEXT: lsr x10, x10, x41896; CHECK-SD-NEXT: lsl x15, x14, #11897; CHECK-SD-NEXT: lsl x16, x13, #11898; CHECK-SD-NEXT: lsl x12, x12, x91899; CHECK-SD-NEXT: lsl x8, x8, x91900; CHECK-SD-NEXT: lsr x9, x13, x61901; CHECK-SD-NEXT: mvn w13, w61902; CHECK-SD-NEXT: lsl x15, x15, x131903; CHECK-SD-NEXT: lsr x14, x14, x61904; CHECK-SD-NEXT: lsl x13, x16, x131905; CHECK-SD-NEXT: orr x0, x12, x111906; CHECK-SD-NEXT: orr x1, x8, x101907; CHECK-SD-NEXT: orr x2, x15, x91908; CHECK-SD-NEXT: orr x3, x13, x141909; CHECK-SD-NEXT: ret1910;1911; CHECK-GI-LABEL: rotr_v2i128:1912; CHECK-GI: // %bb.0: // %entry1913; CHECK-GI-NEXT: and x8, x4, #0x7f1914; CHECK-GI-NEXT: mov w9, #64 // =0x401915; CHECK-GI-NEXT: and x14, x6, #0x7f1916; CHECK-GI-NEXT: sub x10, x9, x81917; CHECK-GI-NEXT: sub x11, x8, #641918; CHECK-GI-NEXT: lsr x12, x0, x81919; CHECK-GI-NEXT: lsl x10, x1, x101920; CHECK-GI-NEXT: lsr x11, x1, x111921; CHECK-GI-NEXT: cmp x8, #641922; CHECK-GI-NEXT: sub x15, x9, x141923; CHECK-GI-NEXT: neg x13, x41924; CHECK-GI-NEXT: lsr x17, x3, x141925; CHECK-GI-NEXT: orr x10, x12, x101926; CHECK-GI-NEXT: lsr x12, x1, x81927; CHECK-GI-NEXT: lsl x15, x3, x151928; CHECK-GI-NEXT: csel x10, x10, x11, lo1929; CHECK-GI-NEXT: tst x4, #0x7f1930; CHECK-GI-NEXT: sub x11, x14, #641931; CHECK-GI-NEXT: csel x10, x0, x10, eq1932; CHECK-GI-NEXT: cmp x8, #641933; CHECK-GI-NEXT: lsr x8, x2, x141934; CHECK-GI-NEXT: lsr x11, x3, x111935; CHECK-GI-NEXT: csel x12, x12, xzr, lo1936; CHECK-GI-NEXT: cmp x14, #641937; CHECK-GI-NEXT: orr x8, x8, x151938; CHECK-GI-NEXT: neg x16, x61939; CHECK-GI-NEXT: csel x8, x8, x11, lo1940; CHECK-GI-NEXT: tst x6, #0x7f1941; CHECK-GI-NEXT: and x11, x13, #0x7f1942; CHECK-GI-NEXT: csel x8, x2, x8, eq1943; CHECK-GI-NEXT: cmp x14, #641944; CHECK-GI-NEXT: sub x14, x9, x111945; CHECK-GI-NEXT: sub x15, x11, #641946; CHECK-GI-NEXT: lsr x14, x0, x141947; CHECK-GI-NEXT: lsl x18, x1, x111948; CHECK-GI-NEXT: lsl x4, x0, x111949; CHECK-GI-NEXT: lsl x15, x0, x151950; CHECK-GI-NEXT: and x0, x16, #0x7f1951; CHECK-GI-NEXT: csel x17, x17, xzr, lo1952; CHECK-GI-NEXT: orr x14, x14, x181953; CHECK-GI-NEXT: cmp x11, #641954; CHECK-GI-NEXT: sub x9, x9, x01955; CHECK-GI-NEXT: csel x14, x14, x15, lo1956; CHECK-GI-NEXT: sub x15, x0, #641957; CHECK-GI-NEXT: lsr x9, x2, x91958; CHECK-GI-NEXT: lsl x18, x3, x01959; CHECK-GI-NEXT: csel x11, x4, xzr, lo1960; CHECK-GI-NEXT: tst x13, #0x7f1961; CHECK-GI-NEXT: lsl x13, x2, x01962; CHECK-GI-NEXT: lsl x15, x2, x151963; CHECK-GI-NEXT: csel x14, x1, x14, eq1964; CHECK-GI-NEXT: orr x9, x9, x181965; CHECK-GI-NEXT: cmp x0, #641966; CHECK-GI-NEXT: csel x13, x13, xzr, lo1967; CHECK-GI-NEXT: csel x9, x9, x15, lo1968; CHECK-GI-NEXT: tst x16, #0x7f1969; CHECK-GI-NEXT: csel x9, x3, x9, eq1970; CHECK-GI-NEXT: orr x0, x10, x111971; CHECK-GI-NEXT: orr x1, x12, x141972; CHECK-GI-NEXT: orr x2, x8, x131973; CHECK-GI-NEXT: orr x3, x17, x91974; CHECK-GI-NEXT: ret1975entry:1976 %d = call <2 x i128> @llvm.fshr(<2 x i128> %a, <2 x i128> %a, <2 x i128> %c)1977 ret <2 x i128> %d1978}1979 1980define <8 x i8> @fshl_v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {1981; CHECK-LABEL: fshl_v8i8:1982; CHECK: // %bb.0: // %entry1983; CHECK-NEXT: movi v3.8b, #71984; CHECK-NEXT: ushr v1.8b, v1.8b, #11985; CHECK-NEXT: bic v4.8b, v3.8b, v2.8b1986; CHECK-NEXT: and v2.8b, v2.8b, v3.8b1987; CHECK-NEXT: neg v3.8b, v4.8b1988; CHECK-NEXT: ushl v0.8b, v0.8b, v2.8b1989; CHECK-NEXT: ushl v1.8b, v1.8b, v3.8b1990; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b1991; CHECK-NEXT: ret1992entry:1993 %d = call <8 x i8> @llvm.fshl(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c)1994 ret <8 x i8> %d1995}1996 1997define <8 x i8> @fshr_v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {1998; CHECK-SD-LABEL: fshr_v8i8:1999; CHECK-SD: // %bb.0: // %entry2000; CHECK-SD-NEXT: movi v3.8b, #72001; CHECK-SD-NEXT: add v0.8b, v0.8b, v0.8b2002; CHECK-SD-NEXT: and v4.8b, v2.8b, v3.8b2003; CHECK-SD-NEXT: bic v2.8b, v3.8b, v2.8b2004; CHECK-SD-NEXT: neg v3.8b, v4.8b2005; CHECK-SD-NEXT: ushl v0.8b, v0.8b, v2.8b2006; CHECK-SD-NEXT: ushl v1.8b, v1.8b, v3.8b2007; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b2008; CHECK-SD-NEXT: ret2009;2010; CHECK-GI-LABEL: fshr_v8i8:2011; CHECK-GI: // %bb.0: // %entry2012; CHECK-GI-NEXT: movi v3.8b, #72013; CHECK-GI-NEXT: shl v0.8b, v0.8b, #12014; CHECK-GI-NEXT: and v4.8b, v2.8b, v3.8b2015; CHECK-GI-NEXT: bic v2.8b, v3.8b, v2.8b2016; CHECK-GI-NEXT: neg v3.8b, v4.8b2017; CHECK-GI-NEXT: ushl v0.8b, v0.8b, v2.8b2018; CHECK-GI-NEXT: ushl v1.8b, v1.8b, v3.8b2019; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2020; CHECK-GI-NEXT: ret2021entry:2022 %d = call <8 x i8> @llvm.fshr(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c)2023 ret <8 x i8> %d2024}2025 2026define <16 x i8> @fshl_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {2027; CHECK-LABEL: fshl_v16i8:2028; CHECK: // %bb.0: // %entry2029; CHECK-NEXT: movi v3.16b, #72030; CHECK-NEXT: ushr v1.16b, v1.16b, #12031; CHECK-NEXT: bic v4.16b, v3.16b, v2.16b2032; CHECK-NEXT: and v2.16b, v2.16b, v3.16b2033; CHECK-NEXT: neg v3.16b, v4.16b2034; CHECK-NEXT: ushl v0.16b, v0.16b, v2.16b2035; CHECK-NEXT: ushl v1.16b, v1.16b, v3.16b2036; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b2037; CHECK-NEXT: ret2038entry:2039 %d = call <16 x i8> @llvm.fshl(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)2040 ret <16 x i8> %d2041}2042 2043define <16 x i8> @fshr_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {2044; CHECK-SD-LABEL: fshr_v16i8:2045; CHECK-SD: // %bb.0: // %entry2046; CHECK-SD-NEXT: movi v3.16b, #72047; CHECK-SD-NEXT: add v0.16b, v0.16b, v0.16b2048; CHECK-SD-NEXT: and v4.16b, v2.16b, v3.16b2049; CHECK-SD-NEXT: bic v2.16b, v3.16b, v2.16b2050; CHECK-SD-NEXT: neg v3.16b, v4.16b2051; CHECK-SD-NEXT: ushl v0.16b, v0.16b, v2.16b2052; CHECK-SD-NEXT: ushl v1.16b, v1.16b, v3.16b2053; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b2054; CHECK-SD-NEXT: ret2055;2056; CHECK-GI-LABEL: fshr_v16i8:2057; CHECK-GI: // %bb.0: // %entry2058; CHECK-GI-NEXT: movi v3.16b, #72059; CHECK-GI-NEXT: shl v0.16b, v0.16b, #12060; CHECK-GI-NEXT: and v4.16b, v2.16b, v3.16b2061; CHECK-GI-NEXT: bic v2.16b, v3.16b, v2.16b2062; CHECK-GI-NEXT: neg v3.16b, v4.16b2063; CHECK-GI-NEXT: ushl v0.16b, v0.16b, v2.16b2064; CHECK-GI-NEXT: ushl v1.16b, v1.16b, v3.16b2065; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2066; CHECK-GI-NEXT: ret2067entry:2068 %d = call <16 x i8> @llvm.fshr(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)2069 ret <16 x i8> %d2070}2071 2072define <4 x i16> @fshl_v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) {2073; CHECK-LABEL: fshl_v4i16:2074; CHECK: // %bb.0: // %entry2075; CHECK-NEXT: movi v3.4h, #152076; CHECK-NEXT: ushr v1.4h, v1.4h, #12077; CHECK-NEXT: bic v4.8b, v3.8b, v2.8b2078; CHECK-NEXT: and v2.8b, v2.8b, v3.8b2079; CHECK-NEXT: neg v3.4h, v4.4h2080; CHECK-NEXT: ushl v0.4h, v0.4h, v2.4h2081; CHECK-NEXT: ushl v1.4h, v1.4h, v3.4h2082; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b2083; CHECK-NEXT: ret2084entry:2085 %d = call <4 x i16> @llvm.fshl(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c)2086 ret <4 x i16> %d2087}2088 2089define <4 x i16> @fshr_v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) {2090; CHECK-SD-LABEL: fshr_v4i16:2091; CHECK-SD: // %bb.0: // %entry2092; CHECK-SD-NEXT: movi v3.4h, #152093; CHECK-SD-NEXT: add v0.4h, v0.4h, v0.4h2094; CHECK-SD-NEXT: and v4.8b, v2.8b, v3.8b2095; CHECK-SD-NEXT: bic v2.8b, v3.8b, v2.8b2096; CHECK-SD-NEXT: neg v3.4h, v4.4h2097; CHECK-SD-NEXT: ushl v0.4h, v0.4h, v2.4h2098; CHECK-SD-NEXT: ushl v1.4h, v1.4h, v3.4h2099; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b2100; CHECK-SD-NEXT: ret2101;2102; CHECK-GI-LABEL: fshr_v4i16:2103; CHECK-GI: // %bb.0: // %entry2104; CHECK-GI-NEXT: movi v3.4h, #152105; CHECK-GI-NEXT: shl v0.4h, v0.4h, #12106; CHECK-GI-NEXT: and v4.8b, v2.8b, v3.8b2107; CHECK-GI-NEXT: bic v2.8b, v3.8b, v2.8b2108; CHECK-GI-NEXT: neg v3.4h, v4.4h2109; CHECK-GI-NEXT: ushl v0.4h, v0.4h, v2.4h2110; CHECK-GI-NEXT: ushl v1.4h, v1.4h, v3.4h2111; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2112; CHECK-GI-NEXT: ret2113entry:2114 %d = call <4 x i16> @llvm.fshr(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c)2115 ret <4 x i16> %d2116}2117 2118define <7 x i16> @fshl_v7i16(<7 x i16> %a, <7 x i16> %b, <7 x i16> %c) {2119; CHECK-SD-LABEL: fshl_v7i16:2120; CHECK-SD: // %bb.0: // %entry2121; CHECK-SD-NEXT: movi v3.8h, #152122; CHECK-SD-NEXT: ushr v1.8h, v1.8h, #12123; CHECK-SD-NEXT: bic v4.16b, v3.16b, v2.16b2124; CHECK-SD-NEXT: and v2.16b, v2.16b, v3.16b2125; CHECK-SD-NEXT: neg v3.8h, v4.8h2126; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h2127; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v3.8h2128; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b2129; CHECK-SD-NEXT: ret2130;2131; CHECK-GI-LABEL: fshl_v7i16:2132; CHECK-GI: // %bb.0: // %entry2133; CHECK-GI-NEXT: mov w8, #65535 // =0xffff2134; CHECK-GI-NEXT: mov w9, #15 // =0xf2135; CHECK-GI-NEXT: mov w10, #1 // =0x12136; CHECK-GI-NEXT: fmov s3, w82137; CHECK-GI-NEXT: fmov s4, w92138; CHECK-GI-NEXT: fmov s5, w102139; CHECK-GI-NEXT: mov v3.h[1], w82140; CHECK-GI-NEXT: mov v4.h[1], w92141; CHECK-GI-NEXT: mov v5.h[1], w102142; CHECK-GI-NEXT: mov v3.h[2], w82143; CHECK-GI-NEXT: mov v4.h[2], w92144; CHECK-GI-NEXT: mov v5.h[2], w102145; CHECK-GI-NEXT: mov v3.h[3], w82146; CHECK-GI-NEXT: mov v4.h[3], w92147; CHECK-GI-NEXT: mov v5.h[3], w102148; CHECK-GI-NEXT: mov v3.h[4], w82149; CHECK-GI-NEXT: mov v4.h[4], w92150; CHECK-GI-NEXT: mov v5.h[4], w102151; CHECK-GI-NEXT: mov v3.h[5], w82152; CHECK-GI-NEXT: mov v4.h[5], w92153; CHECK-GI-NEXT: mov v5.h[5], w102154; CHECK-GI-NEXT: mov v3.h[6], w82155; CHECK-GI-NEXT: mov v4.h[6], w92156; CHECK-GI-NEXT: mov v5.h[6], w102157; CHECK-GI-NEXT: eor v3.16b, v2.16b, v3.16b2158; CHECK-GI-NEXT: neg v5.8h, v5.8h2159; CHECK-GI-NEXT: and v2.16b, v2.16b, v4.16b2160; CHECK-GI-NEXT: and v3.16b, v3.16b, v4.16b2161; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v5.8h2162; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h2163; CHECK-GI-NEXT: neg v3.8h, v3.8h2164; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v3.8h2165; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2166; CHECK-GI-NEXT: ret2167entry:2168 %d = call <7 x i16> @llvm.fshl(<7 x i16> %a, <7 x i16> %b, <7 x i16> %c)2169 ret <7 x i16> %d2170}2171 2172define <7 x i16> @fshr_v7i16(<7 x i16> %a, <7 x i16> %b, <7 x i16> %c) {2173; CHECK-SD-LABEL: fshr_v7i16:2174; CHECK-SD: // %bb.0: // %entry2175; CHECK-SD-NEXT: movi v3.8h, #152176; CHECK-SD-NEXT: add v0.8h, v0.8h, v0.8h2177; CHECK-SD-NEXT: and v4.16b, v2.16b, v3.16b2178; CHECK-SD-NEXT: bic v2.16b, v3.16b, v2.16b2179; CHECK-SD-NEXT: neg v3.8h, v4.8h2180; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h2181; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v3.8h2182; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b2183; CHECK-SD-NEXT: ret2184;2185; CHECK-GI-LABEL: fshr_v7i16:2186; CHECK-GI: // %bb.0: // %entry2187; CHECK-GI-NEXT: mov w8, #15 // =0xf2188; CHECK-GI-NEXT: mov w9, #65535 // =0xffff2189; CHECK-GI-NEXT: mov w10, #1 // =0x12190; CHECK-GI-NEXT: fmov s3, w82191; CHECK-GI-NEXT: fmov s4, w92192; CHECK-GI-NEXT: fmov s5, w102193; CHECK-GI-NEXT: mov v3.h[1], w82194; CHECK-GI-NEXT: mov v4.h[1], w92195; CHECK-GI-NEXT: mov v5.h[1], w102196; CHECK-GI-NEXT: mov v3.h[2], w82197; CHECK-GI-NEXT: mov v4.h[2], w92198; CHECK-GI-NEXT: mov v5.h[2], w102199; CHECK-GI-NEXT: mov v3.h[3], w82200; CHECK-GI-NEXT: mov v4.h[3], w92201; CHECK-GI-NEXT: mov v5.h[3], w102202; CHECK-GI-NEXT: mov v3.h[4], w82203; CHECK-GI-NEXT: mov v4.h[4], w92204; CHECK-GI-NEXT: mov v5.h[4], w102205; CHECK-GI-NEXT: mov v3.h[5], w82206; CHECK-GI-NEXT: mov v4.h[5], w92207; CHECK-GI-NEXT: mov v5.h[5], w102208; CHECK-GI-NEXT: mov v3.h[6], w82209; CHECK-GI-NEXT: mov v4.h[6], w92210; CHECK-GI-NEXT: mov v5.h[6], w102211; CHECK-GI-NEXT: eor v4.16b, v2.16b, v4.16b2212; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b2213; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v5.8h2214; CHECK-GI-NEXT: and v3.16b, v4.16b, v3.16b2215; CHECK-GI-NEXT: neg v2.8h, v2.8h2216; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v3.8h2217; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v2.8h2218; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2219; CHECK-GI-NEXT: ret2220entry:2221 %d = call <7 x i16> @llvm.fshr(<7 x i16> %a, <7 x i16> %b, <7 x i16> %c)2222 ret <7 x i16> %d2223}2224 2225define <8 x i16> @fshl_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {2226; CHECK-LABEL: fshl_v8i16:2227; CHECK: // %bb.0: // %entry2228; CHECK-NEXT: movi v3.8h, #152229; CHECK-NEXT: ushr v1.8h, v1.8h, #12230; CHECK-NEXT: bic v4.16b, v3.16b, v2.16b2231; CHECK-NEXT: and v2.16b, v2.16b, v3.16b2232; CHECK-NEXT: neg v3.8h, v4.8h2233; CHECK-NEXT: ushl v0.8h, v0.8h, v2.8h2234; CHECK-NEXT: ushl v1.8h, v1.8h, v3.8h2235; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b2236; CHECK-NEXT: ret2237entry:2238 %d = call <8 x i16> @llvm.fshl(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c)2239 ret <8 x i16> %d2240}2241 2242define <8 x i16> @fshr_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {2243; CHECK-SD-LABEL: fshr_v8i16:2244; CHECK-SD: // %bb.0: // %entry2245; CHECK-SD-NEXT: movi v3.8h, #152246; CHECK-SD-NEXT: add v0.8h, v0.8h, v0.8h2247; CHECK-SD-NEXT: and v4.16b, v2.16b, v3.16b2248; CHECK-SD-NEXT: bic v2.16b, v3.16b, v2.16b2249; CHECK-SD-NEXT: neg v3.8h, v4.8h2250; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h2251; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v3.8h2252; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b2253; CHECK-SD-NEXT: ret2254;2255; CHECK-GI-LABEL: fshr_v8i16:2256; CHECK-GI: // %bb.0: // %entry2257; CHECK-GI-NEXT: movi v3.8h, #152258; CHECK-GI-NEXT: shl v0.8h, v0.8h, #12259; CHECK-GI-NEXT: and v4.16b, v2.16b, v3.16b2260; CHECK-GI-NEXT: bic v2.16b, v3.16b, v2.16b2261; CHECK-GI-NEXT: neg v3.8h, v4.8h2262; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h2263; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v3.8h2264; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2265; CHECK-GI-NEXT: ret2266entry:2267 %d = call <8 x i16> @llvm.fshr(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c)2268 ret <8 x i16> %d2269}2270 2271define <16 x i16> @fshl_v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c) {2272; CHECK-LABEL: fshl_v16i16:2273; CHECK: // %bb.0: // %entry2274; CHECK-NEXT: movi v6.8h, #152275; CHECK-NEXT: ushr v2.8h, v2.8h, #12276; CHECK-NEXT: ushr v3.8h, v3.8h, #12277; CHECK-NEXT: bic v7.16b, v6.16b, v4.16b2278; CHECK-NEXT: bic v16.16b, v6.16b, v5.16b2279; CHECK-NEXT: and v4.16b, v4.16b, v6.16b2280; CHECK-NEXT: and v5.16b, v5.16b, v6.16b2281; CHECK-NEXT: neg v6.8h, v7.8h2282; CHECK-NEXT: neg v7.8h, v16.8h2283; CHECK-NEXT: ushl v0.8h, v0.8h, v4.8h2284; CHECK-NEXT: ushl v1.8h, v1.8h, v5.8h2285; CHECK-NEXT: ushl v2.8h, v2.8h, v6.8h2286; CHECK-NEXT: ushl v3.8h, v3.8h, v7.8h2287; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b2288; CHECK-NEXT: orr v1.16b, v1.16b, v3.16b2289; CHECK-NEXT: ret2290entry:2291 %d = call <16 x i16> @llvm.fshl(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c)2292 ret <16 x i16> %d2293}2294 2295define <16 x i16> @fshr_v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c) {2296; CHECK-SD-LABEL: fshr_v16i16:2297; CHECK-SD: // %bb.0: // %entry2298; CHECK-SD-NEXT: movi v6.8h, #152299; CHECK-SD-NEXT: add v0.8h, v0.8h, v0.8h2300; CHECK-SD-NEXT: add v1.8h, v1.8h, v1.8h2301; CHECK-SD-NEXT: and v7.16b, v4.16b, v6.16b2302; CHECK-SD-NEXT: and v16.16b, v5.16b, v6.16b2303; CHECK-SD-NEXT: bic v4.16b, v6.16b, v4.16b2304; CHECK-SD-NEXT: bic v5.16b, v6.16b, v5.16b2305; CHECK-SD-NEXT: neg v6.8h, v7.8h2306; CHECK-SD-NEXT: neg v7.8h, v16.8h2307; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v4.8h2308; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v5.8h2309; CHECK-SD-NEXT: ushl v2.8h, v2.8h, v6.8h2310; CHECK-SD-NEXT: ushl v3.8h, v3.8h, v7.8h2311; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b2312; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b2313; CHECK-SD-NEXT: ret2314;2315; CHECK-GI-LABEL: fshr_v16i16:2316; CHECK-GI: // %bb.0: // %entry2317; CHECK-GI-NEXT: movi v6.8h, #152318; CHECK-GI-NEXT: shl v0.8h, v0.8h, #12319; CHECK-GI-NEXT: shl v1.8h, v1.8h, #12320; CHECK-GI-NEXT: and v7.16b, v4.16b, v6.16b2321; CHECK-GI-NEXT: and v16.16b, v5.16b, v6.16b2322; CHECK-GI-NEXT: bic v4.16b, v6.16b, v4.16b2323; CHECK-GI-NEXT: bic v5.16b, v6.16b, v5.16b2324; CHECK-GI-NEXT: neg v6.8h, v7.8h2325; CHECK-GI-NEXT: neg v7.8h, v16.8h2326; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v4.8h2327; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v5.8h2328; CHECK-GI-NEXT: ushl v2.8h, v2.8h, v6.8h2329; CHECK-GI-NEXT: ushl v3.8h, v3.8h, v7.8h2330; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b2331; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b2332; CHECK-GI-NEXT: ret2333entry:2334 %d = call <16 x i16> @llvm.fshr(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c)2335 ret <16 x i16> %d2336}2337 2338define <2 x i32> @fshl_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {2339; CHECK-LABEL: fshl_v2i32:2340; CHECK: // %bb.0: // %entry2341; CHECK-NEXT: movi v3.2s, #312342; CHECK-NEXT: ushr v1.2s, v1.2s, #12343; CHECK-NEXT: bic v4.8b, v3.8b, v2.8b2344; CHECK-NEXT: and v2.8b, v2.8b, v3.8b2345; CHECK-NEXT: neg v3.2s, v4.2s2346; CHECK-NEXT: ushl v0.2s, v0.2s, v2.2s2347; CHECK-NEXT: ushl v1.2s, v1.2s, v3.2s2348; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b2349; CHECK-NEXT: ret2350entry:2351 %d = call <2 x i32> @llvm.fshl(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c)2352 ret <2 x i32> %d2353}2354 2355define <2 x i32> @fshr_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) {2356; CHECK-SD-LABEL: fshr_v2i32:2357; CHECK-SD: // %bb.0: // %entry2358; CHECK-SD-NEXT: movi v3.2s, #312359; CHECK-SD-NEXT: add v0.2s, v0.2s, v0.2s2360; CHECK-SD-NEXT: and v4.8b, v2.8b, v3.8b2361; CHECK-SD-NEXT: bic v2.8b, v3.8b, v2.8b2362; CHECK-SD-NEXT: neg v3.2s, v4.2s2363; CHECK-SD-NEXT: ushl v0.2s, v0.2s, v2.2s2364; CHECK-SD-NEXT: ushl v1.2s, v1.2s, v3.2s2365; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b2366; CHECK-SD-NEXT: ret2367;2368; CHECK-GI-LABEL: fshr_v2i32:2369; CHECK-GI: // %bb.0: // %entry2370; CHECK-GI-NEXT: movi v3.2s, #312371; CHECK-GI-NEXT: shl v0.2s, v0.2s, #12372; CHECK-GI-NEXT: and v4.8b, v2.8b, v3.8b2373; CHECK-GI-NEXT: bic v2.8b, v3.8b, v2.8b2374; CHECK-GI-NEXT: neg v3.2s, v4.2s2375; CHECK-GI-NEXT: ushl v0.2s, v0.2s, v2.2s2376; CHECK-GI-NEXT: ushl v1.2s, v1.2s, v3.2s2377; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b2378; CHECK-GI-NEXT: ret2379entry:2380 %d = call <2 x i32> @llvm.fshr(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c)2381 ret <2 x i32> %d2382}2383 2384define <4 x i32> @fshl_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {2385; CHECK-LABEL: fshl_v4i32:2386; CHECK: // %bb.0: // %entry2387; CHECK-NEXT: movi v3.4s, #312388; CHECK-NEXT: ushr v1.4s, v1.4s, #12389; CHECK-NEXT: bic v4.16b, v3.16b, v2.16b2390; CHECK-NEXT: and v2.16b, v2.16b, v3.16b2391; CHECK-NEXT: neg v3.4s, v4.4s2392; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s2393; CHECK-NEXT: ushl v1.4s, v1.4s, v3.4s2394; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b2395; CHECK-NEXT: ret2396entry:2397 %d = call <4 x i32> @llvm.fshl(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)2398 ret <4 x i32> %d2399}2400 2401define <4 x i32> @fshr_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {2402; CHECK-SD-LABEL: fshr_v4i32:2403; CHECK-SD: // %bb.0: // %entry2404; CHECK-SD-NEXT: movi v3.4s, #312405; CHECK-SD-NEXT: add v0.4s, v0.4s, v0.4s2406; CHECK-SD-NEXT: and v4.16b, v2.16b, v3.16b2407; CHECK-SD-NEXT: bic v2.16b, v3.16b, v2.16b2408; CHECK-SD-NEXT: neg v3.4s, v4.4s2409; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v2.4s2410; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v3.4s2411; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b2412; CHECK-SD-NEXT: ret2413;2414; CHECK-GI-LABEL: fshr_v4i32:2415; CHECK-GI: // %bb.0: // %entry2416; CHECK-GI-NEXT: movi v3.4s, #312417; CHECK-GI-NEXT: shl v0.4s, v0.4s, #12418; CHECK-GI-NEXT: and v4.16b, v2.16b, v3.16b2419; CHECK-GI-NEXT: bic v2.16b, v3.16b, v2.16b2420; CHECK-GI-NEXT: neg v3.4s, v4.4s2421; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v2.4s2422; CHECK-GI-NEXT: ushl v1.4s, v1.4s, v3.4s2423; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2424; CHECK-GI-NEXT: ret2425entry:2426 %d = call <4 x i32> @llvm.fshr(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)2427 ret <4 x i32> %d2428}2429 2430define <7 x i32> @fshl_v7i32(<7 x i32> %a, <7 x i32> %b, <7 x i32> %c) {2431; CHECK-SD-LABEL: fshl_v7i32:2432; CHECK-SD: // %bb.0: // %entry2433; CHECK-SD-NEXT: ldr s0, [sp, #48]2434; CHECK-SD-NEXT: add x8, sp, #562435; CHECK-SD-NEXT: fmov s3, w72436; CHECK-SD-NEXT: fmov s4, w02437; CHECK-SD-NEXT: ldr s2, [sp, #80]2438; CHECK-SD-NEXT: mov x9, sp2439; CHECK-SD-NEXT: ld1 { v0.s }[1], [x8]2440; CHECK-SD-NEXT: add x10, sp, #882441; CHECK-SD-NEXT: ldr s1, [sp, #24]2442; CHECK-SD-NEXT: ld1 { v3.s }[1], [x9]2443; CHECK-SD-NEXT: add x9, sp, #642444; CHECK-SD-NEXT: ld1 { v2.s }[1], [x10]2445; CHECK-SD-NEXT: mov v4.s[1], w12446; CHECK-SD-NEXT: add x8, sp, #322447; CHECK-SD-NEXT: fmov s5, w42448; CHECK-SD-NEXT: ld1 { v0.s }[2], [x9]2449; CHECK-SD-NEXT: ld1 { v1.s }[1], [x8]2450; CHECK-SD-NEXT: add x8, sp, #82451; CHECK-SD-NEXT: add x9, sp, #722452; CHECK-SD-NEXT: movi v6.4s, #312453; CHECK-SD-NEXT: add x10, sp, #962454; CHECK-SD-NEXT: ld1 { v3.s }[2], [x8]2455; CHECK-SD-NEXT: ld1 { v2.s }[2], [x10]2456; CHECK-SD-NEXT: mov v5.s[1], w52457; CHECK-SD-NEXT: ld1 { v0.s }[3], [x9]2458; CHECK-SD-NEXT: mov v4.s[2], w22459; CHECK-SD-NEXT: add x8, sp, #162460; CHECK-SD-NEXT: add x9, sp, #402461; CHECK-SD-NEXT: ld1 { v3.s }[3], [x8]2462; CHECK-SD-NEXT: ld1 { v1.s }[2], [x9]2463; CHECK-SD-NEXT: bic v16.16b, v6.16b, v2.16b2464; CHECK-SD-NEXT: bic v7.16b, v6.16b, v0.16b2465; CHECK-SD-NEXT: mov v5.s[2], w62466; CHECK-SD-NEXT: and v0.16b, v0.16b, v6.16b2467; CHECK-SD-NEXT: mov v4.s[3], w32468; CHECK-SD-NEXT: and v2.16b, v2.16b, v6.16b2469; CHECK-SD-NEXT: ushr v3.4s, v3.4s, #12470; CHECK-SD-NEXT: ushr v1.4s, v1.4s, #12471; CHECK-SD-NEXT: neg v6.4s, v16.4s2472; CHECK-SD-NEXT: neg v7.4s, v7.4s2473; CHECK-SD-NEXT: ushl v2.4s, v5.4s, v2.4s2474; CHECK-SD-NEXT: ushl v0.4s, v4.4s, v0.4s2475; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v6.4s2476; CHECK-SD-NEXT: ushl v3.4s, v3.4s, v7.4s2477; CHECK-SD-NEXT: orr v1.16b, v2.16b, v1.16b2478; CHECK-SD-NEXT: orr v0.16b, v0.16b, v3.16b2479; CHECK-SD-NEXT: mov w5, v1.s[1]2480; CHECK-SD-NEXT: mov w6, v1.s[2]2481; CHECK-SD-NEXT: fmov w4, s12482; CHECK-SD-NEXT: mov w1, v0.s[1]2483; CHECK-SD-NEXT: mov w2, v0.s[2]2484; CHECK-SD-NEXT: mov w3, v0.s[3]2485; CHECK-SD-NEXT: fmov w0, s02486; CHECK-SD-NEXT: ret2487;2488; CHECK-GI-LABEL: fshl_v7i32:2489; CHECK-GI: // %bb.0: // %entry2490; CHECK-GI-NEXT: ldr s17, [sp, #48]2491; CHECK-GI-NEXT: add x8, sp, #562492; CHECK-GI-NEXT: add x9, sp, #642493; CHECK-GI-NEXT: ldr s4, [sp, #48]2494; CHECK-GI-NEXT: ldr s21, [sp, #56]2495; CHECK-GI-NEXT: mov w10, #-1 // =0xffffffff2496; CHECK-GI-NEXT: ld1 { v17.s }[1], [x8]2497; CHECK-GI-NEXT: ldr s20, [x9]2498; CHECK-GI-NEXT: add x8, sp, #722499; CHECK-GI-NEXT: mov v4.s[1], v21.s[0]2500; CHECK-GI-NEXT: fmov s21, w72501; CHECK-GI-NEXT: ldr s6, [sp]2502; CHECK-GI-NEXT: ld1 { v20.s }[1], [x8]2503; CHECK-GI-NEXT: ldr s19, [sp, #64]2504; CHECK-GI-NEXT: ldr s7, [sp, #80]2505; CHECK-GI-NEXT: ldr s22, [sp, #88]2506; CHECK-GI-NEXT: mov w9, #31 // =0x1f2507; CHECK-GI-NEXT: mov w11, #1 // =0x12508; CHECK-GI-NEXT: mov v21.s[1], v6.s[0]2509; CHECK-GI-NEXT: fmov s6, w92510; CHECK-GI-NEXT: ldr s18, [sp, #96]2511; CHECK-GI-NEXT: zip1 v17.2d, v17.2d, v20.2d2512; CHECK-GI-NEXT: fmov s20, w102513; CHECK-GI-NEXT: mov v7.s[1], v22.s[0]2514; CHECK-GI-NEXT: mov v4.s[2], v19.s[0]2515; CHECK-GI-NEXT: fmov s19, w112516; CHECK-GI-NEXT: fmov s23, w02517; CHECK-GI-NEXT: mov v6.s[1], w92518; CHECK-GI-NEXT: fmov s24, w92519; CHECK-GI-NEXT: ldr s2, [sp, #8]2520; CHECK-GI-NEXT: mov v20.s[1], w102521; CHECK-GI-NEXT: ldr s0, [sp, #24]2522; CHECK-GI-NEXT: ldr s5, [sp, #32]2523; CHECK-GI-NEXT: mov v19.s[1], w112524; CHECK-GI-NEXT: mov v7.s[2], v18.s[0]2525; CHECK-GI-NEXT: ldr s16, [sp, #72]2526; CHECK-GI-NEXT: mov v23.s[1], w12527; CHECK-GI-NEXT: ldr s18, [sp, #80]2528; CHECK-GI-NEXT: mov v21.s[2], v2.s[0]2529; CHECK-GI-NEXT: mov v24.s[1], w92530; CHECK-GI-NEXT: mov v0.s[1], v5.s[0]2531; CHECK-GI-NEXT: fmov s5, w42532; CHECK-GI-NEXT: mov v20.s[2], w102533; CHECK-GI-NEXT: add x8, sp, #882534; CHECK-GI-NEXT: movi v22.4s, #312535; CHECK-GI-NEXT: mov v4.s[3], v16.s[0]2536; CHECK-GI-NEXT: mov v6.s[2], w92537; CHECK-GI-NEXT: mov v19.s[2], w112538; CHECK-GI-NEXT: ldr s1, [sp, #16]2539; CHECK-GI-NEXT: ldr s3, [sp, #40]2540; CHECK-GI-NEXT: ld1 { v18.s }[1], [x8]2541; CHECK-GI-NEXT: mov v23.s[2], w22542; CHECK-GI-NEXT: mov v5.s[1], w52543; CHECK-GI-NEXT: add x8, sp, #962544; CHECK-GI-NEXT: eor v2.16b, v7.16b, v20.16b2545; CHECK-GI-NEXT: mov v21.s[3], v1.s[0]2546; CHECK-GI-NEXT: mov v24.s[2], w92547; CHECK-GI-NEXT: mov v0.s[2], v3.s[0]2548; CHECK-GI-NEXT: bic v1.16b, v22.16b, v4.16b2549; CHECK-GI-NEXT: ld1 { v18.s }[2], [x8]2550; CHECK-GI-NEXT: neg v3.4s, v19.4s2551; CHECK-GI-NEXT: and v4.16b, v17.16b, v22.16b2552; CHECK-GI-NEXT: and v2.16b, v2.16b, v6.16b2553; CHECK-GI-NEXT: mov v23.s[3], w32554; CHECK-GI-NEXT: mov v5.s[2], w62555; CHECK-GI-NEXT: ushr v6.4s, v21.4s, #12556; CHECK-GI-NEXT: neg v1.4s, v1.4s2557; CHECK-GI-NEXT: and v7.16b, v18.16b, v24.16b2558; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v3.4s2559; CHECK-GI-NEXT: neg v2.4s, v2.4s2560; CHECK-GI-NEXT: ushl v3.4s, v23.4s, v4.4s2561; CHECK-GI-NEXT: ushl v1.4s, v6.4s, v1.4s2562; CHECK-GI-NEXT: ushl v4.4s, v5.4s, v7.4s2563; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v2.4s2564; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b2565; CHECK-GI-NEXT: orr v0.16b, v4.16b, v0.16b2566; CHECK-GI-NEXT: mov s2, v1.s[1]2567; CHECK-GI-NEXT: mov s3, v1.s[2]2568; CHECK-GI-NEXT: mov s4, v1.s[3]2569; CHECK-GI-NEXT: fmov w0, s12570; CHECK-GI-NEXT: mov s5, v0.s[1]2571; CHECK-GI-NEXT: mov s6, v0.s[2]2572; CHECK-GI-NEXT: fmov w4, s02573; CHECK-GI-NEXT: fmov w1, s22574; CHECK-GI-NEXT: fmov w2, s32575; CHECK-GI-NEXT: fmov w3, s42576; CHECK-GI-NEXT: fmov w5, s52577; CHECK-GI-NEXT: fmov w6, s62578; CHECK-GI-NEXT: ret2579entry:2580 %d = call <7 x i32> @llvm.fshl(<7 x i32> %a, <7 x i32> %b, <7 x i32> %c)2581 ret <7 x i32> %d2582}2583 2584define <7 x i32> @fshr_v7i32(<7 x i32> %a, <7 x i32> %b, <7 x i32> %c) {2585; CHECK-SD-LABEL: fshr_v7i32:2586; CHECK-SD: // %bb.0: // %entry2587; CHECK-SD-NEXT: fmov s1, w02588; CHECK-SD-NEXT: ldr s0, [sp, #48]2589; CHECK-SD-NEXT: add x8, sp, #562590; CHECK-SD-NEXT: ldr s2, [sp, #80]2591; CHECK-SD-NEXT: fmov s3, w42592; CHECK-SD-NEXT: add x9, sp, #642593; CHECK-SD-NEXT: ld1 { v0.s }[1], [x8]2594; CHECK-SD-NEXT: add x8, sp, #882595; CHECK-SD-NEXT: fmov s4, w72596; CHECK-SD-NEXT: mov v1.s[1], w12597; CHECK-SD-NEXT: ld1 { v2.s }[1], [x8]2598; CHECK-SD-NEXT: mov x10, sp2599; CHECK-SD-NEXT: mov v3.s[1], w52600; CHECK-SD-NEXT: add x8, sp, #722601; CHECK-SD-NEXT: movi v5.4s, #312602; CHECK-SD-NEXT: ld1 { v0.s }[2], [x9]2603; CHECK-SD-NEXT: add x9, sp, #962604; CHECK-SD-NEXT: ld1 { v4.s }[1], [x10]2605; CHECK-SD-NEXT: ld1 { v2.s }[2], [x9]2606; CHECK-SD-NEXT: ldr s6, [sp, #24]2607; CHECK-SD-NEXT: add x9, sp, #82608; CHECK-SD-NEXT: mov v1.s[2], w22609; CHECK-SD-NEXT: ld1 { v0.s }[3], [x8]2610; CHECK-SD-NEXT: add x8, sp, #322611; CHECK-SD-NEXT: mov v3.s[2], w62612; CHECK-SD-NEXT: ld1 { v4.s }[2], [x9]2613; CHECK-SD-NEXT: ld1 { v6.s }[1], [x8]2614; CHECK-SD-NEXT: bic v16.16b, v5.16b, v2.16b2615; CHECK-SD-NEXT: and v2.16b, v2.16b, v5.16b2616; CHECK-SD-NEXT: add x8, sp, #402617; CHECK-SD-NEXT: add x9, sp, #162618; CHECK-SD-NEXT: mov v1.s[3], w32619; CHECK-SD-NEXT: and v7.16b, v0.16b, v5.16b2620; CHECK-SD-NEXT: bic v0.16b, v5.16b, v0.16b2621; CHECK-SD-NEXT: ld1 { v4.s }[3], [x9]2622; CHECK-SD-NEXT: ld1 { v6.s }[2], [x8]2623; CHECK-SD-NEXT: add v3.4s, v3.4s, v3.4s2624; CHECK-SD-NEXT: neg v2.4s, v2.4s2625; CHECK-SD-NEXT: neg v5.4s, v7.4s2626; CHECK-SD-NEXT: add v1.4s, v1.4s, v1.4s2627; CHECK-SD-NEXT: ushl v3.4s, v3.4s, v16.4s2628; CHECK-SD-NEXT: ushl v2.4s, v6.4s, v2.4s2629; CHECK-SD-NEXT: ushl v0.4s, v1.4s, v0.4s2630; CHECK-SD-NEXT: ushl v1.4s, v4.4s, v5.4s2631; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b2632; CHECK-SD-NEXT: orr v1.16b, v3.16b, v2.16b2633; CHECK-SD-NEXT: mov w1, v0.s[1]2634; CHECK-SD-NEXT: mov w2, v0.s[2]2635; CHECK-SD-NEXT: mov w3, v0.s[3]2636; CHECK-SD-NEXT: mov w5, v1.s[1]2637; CHECK-SD-NEXT: mov w6, v1.s[2]2638; CHECK-SD-NEXT: fmov w0, s02639; CHECK-SD-NEXT: fmov w4, s12640; CHECK-SD-NEXT: ret2641;2642; CHECK-GI-LABEL: fshr_v7i32:2643; CHECK-GI: // %bb.0: // %entry2644; CHECK-GI-NEXT: ldr s4, [sp, #48]2645; CHECK-GI-NEXT: add x8, sp, #562646; CHECK-GI-NEXT: ldr s2, [sp, #48]2647; CHECK-GI-NEXT: ldr s18, [sp, #56]2648; CHECK-GI-NEXT: ldr s5, [sp, #80]2649; CHECK-GI-NEXT: add x9, sp, #722650; CHECK-GI-NEXT: ld1 { v4.s }[1], [x8]2651; CHECK-GI-NEXT: ldr s19, [sp, #88]2652; CHECK-GI-NEXT: add x8, sp, #642653; CHECK-GI-NEXT: mov v2.s[1], v18.s[0]2654; CHECK-GI-NEXT: ldr s20, [sp, #64]2655; CHECK-GI-NEXT: ldr s21, [sp, #96]2656; CHECK-GI-NEXT: mov v5.s[1], v19.s[0]2657; CHECK-GI-NEXT: fmov s19, w02658; CHECK-GI-NEXT: ldr s7, [sp, #80]2659; CHECK-GI-NEXT: ld1 { v4.s }[2], [x8]2660; CHECK-GI-NEXT: mov w8, #31 // =0x1f2661; CHECK-GI-NEXT: ldr s16, [sp]2662; CHECK-GI-NEXT: fmov s22, w82663; CHECK-GI-NEXT: add x10, sp, #882664; CHECK-GI-NEXT: fmov s23, w82665; CHECK-GI-NEXT: mov v2.s[2], v20.s[0]2666; CHECK-GI-NEXT: ld1 { v7.s }[1], [x10]2667; CHECK-GI-NEXT: mov v19.s[1], w12668; CHECK-GI-NEXT: ld1 { v4.s }[3], [x9]2669; CHECK-GI-NEXT: mov w9, #-1 // =0xffffffff2670; CHECK-GI-NEXT: mov v5.s[2], v21.s[0]2671; CHECK-GI-NEXT: fmov s20, w92672; CHECK-GI-NEXT: fmov s21, w72673; CHECK-GI-NEXT: mov w10, #1 // =0x12674; CHECK-GI-NEXT: mov v22.s[1], w82675; CHECK-GI-NEXT: fmov s24, w102676; CHECK-GI-NEXT: mov v23.s[1], w82677; CHECK-GI-NEXT: mov v19.s[2], w22678; CHECK-GI-NEXT: ldr s6, [sp, #8]2679; CHECK-GI-NEXT: ldr s0, [sp, #24]2680; CHECK-GI-NEXT: mov v20.s[1], w92681; CHECK-GI-NEXT: mov v21.s[1], v16.s[0]2682; CHECK-GI-NEXT: fmov s16, w42683; CHECK-GI-NEXT: mov v24.s[1], w102684; CHECK-GI-NEXT: ldr s3, [sp, #32]2685; CHECK-GI-NEXT: movi v18.4s, #312686; CHECK-GI-NEXT: add x11, sp, #962687; CHECK-GI-NEXT: mov v22.s[2], w82688; CHECK-GI-NEXT: ldr s17, [sp, #72]2689; CHECK-GI-NEXT: mov v16.s[1], w52690; CHECK-GI-NEXT: ld1 { v7.s }[2], [x11]2691; CHECK-GI-NEXT: mov v0.s[1], v3.s[0]2692; CHECK-GI-NEXT: mov v20.s[2], w92693; CHECK-GI-NEXT: mov v21.s[2], v6.s[0]2694; CHECK-GI-NEXT: mov v2.s[3], v17.s[0]2695; CHECK-GI-NEXT: mov v19.s[3], w32696; CHECK-GI-NEXT: mov v23.s[2], w82697; CHECK-GI-NEXT: mov v24.s[2], w102698; CHECK-GI-NEXT: ldr s1, [sp, #16]2699; CHECK-GI-NEXT: and v4.16b, v4.16b, v18.16b2700; CHECK-GI-NEXT: ldr s3, [sp, #40]2701; CHECK-GI-NEXT: mov v16.s[2], w62702; CHECK-GI-NEXT: and v6.16b, v7.16b, v22.16b2703; CHECK-GI-NEXT: eor v5.16b, v5.16b, v20.16b2704; CHECK-GI-NEXT: mov v21.s[3], v1.s[0]2705; CHECK-GI-NEXT: mov v0.s[2], v3.s[0]2706; CHECK-GI-NEXT: bic v2.16b, v18.16b, v2.16b2707; CHECK-GI-NEXT: shl v1.4s, v19.4s, #12708; CHECK-GI-NEXT: neg v4.4s, v4.4s2709; CHECK-GI-NEXT: neg v6.4s, v6.4s2710; CHECK-GI-NEXT: and v3.16b, v5.16b, v23.16b2711; CHECK-GI-NEXT: ushl v5.4s, v16.4s, v24.4s2712; CHECK-GI-NEXT: ushl v1.4s, v1.4s, v2.4s2713; CHECK-GI-NEXT: ushl v2.4s, v21.4s, v4.4s2714; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v6.4s2715; CHECK-GI-NEXT: ushl v3.4s, v5.4s, v3.4s2716; CHECK-GI-NEXT: orr v1.16b, v1.16b, v2.16b2717; CHECK-GI-NEXT: orr v0.16b, v3.16b, v0.16b2718; CHECK-GI-NEXT: mov s2, v1.s[1]2719; CHECK-GI-NEXT: mov s3, v1.s[2]2720; CHECK-GI-NEXT: mov s4, v1.s[3]2721; CHECK-GI-NEXT: fmov w0, s12722; CHECK-GI-NEXT: mov s5, v0.s[1]2723; CHECK-GI-NEXT: mov s6, v0.s[2]2724; CHECK-GI-NEXT: fmov w4, s02725; CHECK-GI-NEXT: fmov w1, s22726; CHECK-GI-NEXT: fmov w2, s32727; CHECK-GI-NEXT: fmov w3, s42728; CHECK-GI-NEXT: fmov w5, s52729; CHECK-GI-NEXT: fmov w6, s62730; CHECK-GI-NEXT: ret2731entry:2732 %d = call <7 x i32> @llvm.fshr(<7 x i32> %a, <7 x i32> %b, <7 x i32> %c)2733 ret <7 x i32> %d2734}2735 2736define <8 x i32> @fshl_v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c) {2737; CHECK-LABEL: fshl_v8i32:2738; CHECK: // %bb.0: // %entry2739; CHECK-NEXT: movi v6.4s, #312740; CHECK-NEXT: ushr v2.4s, v2.4s, #12741; CHECK-NEXT: ushr v3.4s, v3.4s, #12742; CHECK-NEXT: bic v7.16b, v6.16b, v4.16b2743; CHECK-NEXT: bic v16.16b, v6.16b, v5.16b2744; CHECK-NEXT: and v4.16b, v4.16b, v6.16b2745; CHECK-NEXT: and v5.16b, v5.16b, v6.16b2746; CHECK-NEXT: neg v6.4s, v7.4s2747; CHECK-NEXT: neg v7.4s, v16.4s2748; CHECK-NEXT: ushl v0.4s, v0.4s, v4.4s2749; CHECK-NEXT: ushl v1.4s, v1.4s, v5.4s2750; CHECK-NEXT: ushl v2.4s, v2.4s, v6.4s2751; CHECK-NEXT: ushl v3.4s, v3.4s, v7.4s2752; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b2753; CHECK-NEXT: orr v1.16b, v1.16b, v3.16b2754; CHECK-NEXT: ret2755entry:2756 %d = call <8 x i32> @llvm.fshl(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c)2757 ret <8 x i32> %d2758}2759 2760define <8 x i32> @fshr_v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c) {2761; CHECK-SD-LABEL: fshr_v8i32:2762; CHECK-SD: // %bb.0: // %entry2763; CHECK-SD-NEXT: movi v6.4s, #312764; CHECK-SD-NEXT: add v0.4s, v0.4s, v0.4s2765; CHECK-SD-NEXT: add v1.4s, v1.4s, v1.4s2766; CHECK-SD-NEXT: and v7.16b, v4.16b, v6.16b2767; CHECK-SD-NEXT: and v16.16b, v5.16b, v6.16b2768; CHECK-SD-NEXT: bic v4.16b, v6.16b, v4.16b2769; CHECK-SD-NEXT: bic v5.16b, v6.16b, v5.16b2770; CHECK-SD-NEXT: neg v6.4s, v7.4s2771; CHECK-SD-NEXT: neg v7.4s, v16.4s2772; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v4.4s2773; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v5.4s2774; CHECK-SD-NEXT: ushl v2.4s, v2.4s, v6.4s2775; CHECK-SD-NEXT: ushl v3.4s, v3.4s, v7.4s2776; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b2777; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b2778; CHECK-SD-NEXT: ret2779;2780; CHECK-GI-LABEL: fshr_v8i32:2781; CHECK-GI: // %bb.0: // %entry2782; CHECK-GI-NEXT: movi v6.4s, #312783; CHECK-GI-NEXT: shl v0.4s, v0.4s, #12784; CHECK-GI-NEXT: shl v1.4s, v1.4s, #12785; CHECK-GI-NEXT: and v7.16b, v4.16b, v6.16b2786; CHECK-GI-NEXT: and v16.16b, v5.16b, v6.16b2787; CHECK-GI-NEXT: bic v4.16b, v6.16b, v4.16b2788; CHECK-GI-NEXT: bic v5.16b, v6.16b, v5.16b2789; CHECK-GI-NEXT: neg v6.4s, v7.4s2790; CHECK-GI-NEXT: neg v7.4s, v16.4s2791; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v4.4s2792; CHECK-GI-NEXT: ushl v1.4s, v1.4s, v5.4s2793; CHECK-GI-NEXT: ushl v2.4s, v2.4s, v6.4s2794; CHECK-GI-NEXT: ushl v3.4s, v3.4s, v7.4s2795; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b2796; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b2797; CHECK-GI-NEXT: ret2798entry:2799 %d = call <8 x i32> @llvm.fshr(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c)2800 ret <8 x i32> %d2801}2802 2803define <2 x i64> @fshl_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {2804; CHECK-SD-LABEL: fshl_v2i64:2805; CHECK-SD: // %bb.0: // %entry2806; CHECK-SD-NEXT: mov w8, #63 // =0x3f2807; CHECK-SD-NEXT: ushr v1.2d, v1.2d, #12808; CHECK-SD-NEXT: dup v3.2d, x82809; CHECK-SD-NEXT: bic v4.16b, v3.16b, v2.16b2810; CHECK-SD-NEXT: and v2.16b, v2.16b, v3.16b2811; CHECK-SD-NEXT: neg v3.2d, v4.2d2812; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v2.2d2813; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v3.2d2814; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b2815; CHECK-SD-NEXT: ret2816;2817; CHECK-GI-LABEL: fshl_v2i64:2818; CHECK-GI: // %bb.0: // %entry2819; CHECK-GI-NEXT: adrp x8, .LCPI86_02820; CHECK-GI-NEXT: ushr v1.2d, v1.2d, #12821; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI86_0]2822; CHECK-GI-NEXT: bic v4.16b, v3.16b, v2.16b2823; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b2824; CHECK-GI-NEXT: neg v3.2d, v4.2d2825; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v2.2d2826; CHECK-GI-NEXT: ushl v1.2d, v1.2d, v3.2d2827; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2828; CHECK-GI-NEXT: ret2829entry:2830 %d = call <2 x i64> @llvm.fshl(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)2831 ret <2 x i64> %d2832}2833 2834define <2 x i64> @fshr_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {2835; CHECK-SD-LABEL: fshr_v2i64:2836; CHECK-SD: // %bb.0: // %entry2837; CHECK-SD-NEXT: mov w8, #63 // =0x3f2838; CHECK-SD-NEXT: add v0.2d, v0.2d, v0.2d2839; CHECK-SD-NEXT: dup v3.2d, x82840; CHECK-SD-NEXT: and v4.16b, v2.16b, v3.16b2841; CHECK-SD-NEXT: bic v2.16b, v3.16b, v2.16b2842; CHECK-SD-NEXT: neg v3.2d, v4.2d2843; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v2.2d2844; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v3.2d2845; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b2846; CHECK-SD-NEXT: ret2847;2848; CHECK-GI-LABEL: fshr_v2i64:2849; CHECK-GI: // %bb.0: // %entry2850; CHECK-GI-NEXT: adrp x8, .LCPI87_02851; CHECK-GI-NEXT: shl v0.2d, v0.2d, #12852; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI87_0]2853; CHECK-GI-NEXT: and v4.16b, v2.16b, v3.16b2854; CHECK-GI-NEXT: bic v2.16b, v3.16b, v2.16b2855; CHECK-GI-NEXT: neg v3.2d, v4.2d2856; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v2.2d2857; CHECK-GI-NEXT: ushl v1.2d, v1.2d, v3.2d2858; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b2859; CHECK-GI-NEXT: ret2860entry:2861 %d = call <2 x i64> @llvm.fshr(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)2862 ret <2 x i64> %d2863}2864 2865define <4 x i64> @fshl_v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c) {2866; CHECK-SD-LABEL: fshl_v4i64:2867; CHECK-SD: // %bb.0: // %entry2868; CHECK-SD-NEXT: mov w8, #63 // =0x3f2869; CHECK-SD-NEXT: ushr v2.2d, v2.2d, #12870; CHECK-SD-NEXT: ushr v3.2d, v3.2d, #12871; CHECK-SD-NEXT: dup v6.2d, x82872; CHECK-SD-NEXT: bic v7.16b, v6.16b, v4.16b2873; CHECK-SD-NEXT: bic v16.16b, v6.16b, v5.16b2874; CHECK-SD-NEXT: and v4.16b, v4.16b, v6.16b2875; CHECK-SD-NEXT: and v5.16b, v5.16b, v6.16b2876; CHECK-SD-NEXT: neg v6.2d, v7.2d2877; CHECK-SD-NEXT: neg v7.2d, v16.2d2878; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v4.2d2879; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v5.2d2880; CHECK-SD-NEXT: ushl v2.2d, v2.2d, v6.2d2881; CHECK-SD-NEXT: ushl v3.2d, v3.2d, v7.2d2882; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b2883; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b2884; CHECK-SD-NEXT: ret2885;2886; CHECK-GI-LABEL: fshl_v4i64:2887; CHECK-GI: // %bb.0: // %entry2888; CHECK-GI-NEXT: adrp x8, .LCPI88_02889; CHECK-GI-NEXT: ushr v2.2d, v2.2d, #12890; CHECK-GI-NEXT: ushr v3.2d, v3.2d, #12891; CHECK-GI-NEXT: ldr q6, [x8, :lo12:.LCPI88_0]2892; CHECK-GI-NEXT: bic v7.16b, v6.16b, v4.16b2893; CHECK-GI-NEXT: bic v16.16b, v6.16b, v5.16b2894; CHECK-GI-NEXT: and v4.16b, v4.16b, v6.16b2895; CHECK-GI-NEXT: and v5.16b, v5.16b, v6.16b2896; CHECK-GI-NEXT: neg v6.2d, v7.2d2897; CHECK-GI-NEXT: neg v7.2d, v16.2d2898; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v4.2d2899; CHECK-GI-NEXT: ushl v1.2d, v1.2d, v5.2d2900; CHECK-GI-NEXT: ushl v2.2d, v2.2d, v6.2d2901; CHECK-GI-NEXT: ushl v3.2d, v3.2d, v7.2d2902; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b2903; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b2904; CHECK-GI-NEXT: ret2905entry:2906 %d = call <4 x i64> @llvm.fshl(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c)2907 ret <4 x i64> %d2908}2909 2910define <4 x i64> @fshr_v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c) {2911; CHECK-SD-LABEL: fshr_v4i64:2912; CHECK-SD: // %bb.0: // %entry2913; CHECK-SD-NEXT: mov w8, #63 // =0x3f2914; CHECK-SD-NEXT: add v0.2d, v0.2d, v0.2d2915; CHECK-SD-NEXT: add v1.2d, v1.2d, v1.2d2916; CHECK-SD-NEXT: dup v6.2d, x82917; CHECK-SD-NEXT: and v7.16b, v4.16b, v6.16b2918; CHECK-SD-NEXT: and v16.16b, v5.16b, v6.16b2919; CHECK-SD-NEXT: bic v4.16b, v6.16b, v4.16b2920; CHECK-SD-NEXT: bic v5.16b, v6.16b, v5.16b2921; CHECK-SD-NEXT: neg v6.2d, v7.2d2922; CHECK-SD-NEXT: neg v7.2d, v16.2d2923; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v4.2d2924; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v5.2d2925; CHECK-SD-NEXT: ushl v2.2d, v2.2d, v6.2d2926; CHECK-SD-NEXT: ushl v3.2d, v3.2d, v7.2d2927; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b2928; CHECK-SD-NEXT: orr v1.16b, v1.16b, v3.16b2929; CHECK-SD-NEXT: ret2930;2931; CHECK-GI-LABEL: fshr_v4i64:2932; CHECK-GI: // %bb.0: // %entry2933; CHECK-GI-NEXT: adrp x8, .LCPI89_02934; CHECK-GI-NEXT: shl v0.2d, v0.2d, #12935; CHECK-GI-NEXT: shl v1.2d, v1.2d, #12936; CHECK-GI-NEXT: ldr q6, [x8, :lo12:.LCPI89_0]2937; CHECK-GI-NEXT: and v7.16b, v4.16b, v6.16b2938; CHECK-GI-NEXT: and v16.16b, v5.16b, v6.16b2939; CHECK-GI-NEXT: bic v4.16b, v6.16b, v4.16b2940; CHECK-GI-NEXT: bic v5.16b, v6.16b, v5.16b2941; CHECK-GI-NEXT: neg v6.2d, v7.2d2942; CHECK-GI-NEXT: neg v7.2d, v16.2d2943; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v4.2d2944; CHECK-GI-NEXT: ushl v1.2d, v1.2d, v5.2d2945; CHECK-GI-NEXT: ushl v2.2d, v2.2d, v6.2d2946; CHECK-GI-NEXT: ushl v3.2d, v3.2d, v7.2d2947; CHECK-GI-NEXT: orr v0.16b, v0.16b, v2.16b2948; CHECK-GI-NEXT: orr v1.16b, v1.16b, v3.16b2949; CHECK-GI-NEXT: ret2950entry:2951 %d = call <4 x i64> @llvm.fshr(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c)2952 ret <4 x i64> %d2953}2954 2955define <2 x i128> @fshl_v2i128(<2 x i128> %a, <2 x i128> %b, <2 x i128> %c) {2956; CHECK-SD-LABEL: fshl_v2i128:2957; CHECK-SD: // %bb.0: // %entry2958; CHECK-SD-NEXT: ldr x8, [sp]2959; CHECK-SD-NEXT: ldr x10, [sp, #16]2960; CHECK-SD-NEXT: tst x8, #0x402961; CHECK-SD-NEXT: mvn w13, w82962; CHECK-SD-NEXT: mvn w16, w102963; CHECK-SD-NEXT: csel x9, x5, x0, ne2964; CHECK-SD-NEXT: csel x11, x4, x5, ne2965; CHECK-SD-NEXT: csel x14, x0, x1, ne2966; CHECK-SD-NEXT: lsl x12, x9, x82967; CHECK-SD-NEXT: lsr x11, x11, #12968; CHECK-SD-NEXT: lsr x9, x9, #12969; CHECK-SD-NEXT: tst x10, #0x402970; CHECK-SD-NEXT: lsl x8, x14, x82971; CHECK-SD-NEXT: csel x14, x7, x2, ne2972; CHECK-SD-NEXT: csel x15, x6, x7, ne2973; CHECK-SD-NEXT: lsr x11, x11, x132974; CHECK-SD-NEXT: lsr x9, x9, x132975; CHECK-SD-NEXT: lsr x13, x15, #12976; CHECK-SD-NEXT: lsr x15, x14, #12977; CHECK-SD-NEXT: csel x17, x2, x3, ne2978; CHECK-SD-NEXT: lsl x14, x14, x102979; CHECK-SD-NEXT: orr x0, x12, x112980; CHECK-SD-NEXT: lsr x13, x13, x162981; CHECK-SD-NEXT: lsl x10, x17, x102982; CHECK-SD-NEXT: lsr x15, x15, x162983; CHECK-SD-NEXT: orr x1, x8, x92984; CHECK-SD-NEXT: orr x2, x14, x132985; CHECK-SD-NEXT: orr x3, x10, x152986; CHECK-SD-NEXT: ret2987;2988; CHECK-GI-LABEL: fshl_v2i128:2989; CHECK-GI: // %bb.0: // %entry2990; CHECK-GI-NEXT: str x19, [sp, #-16]! // 8-byte Folded Spill2991; CHECK-GI-NEXT: .cfi_def_cfa_offset 162992; CHECK-GI-NEXT: .cfi_offset w19, -162993; CHECK-GI-NEXT: ldr x11, [sp, #16]2994; CHECK-GI-NEXT: mov w9, #64 // =0x402995; CHECK-GI-NEXT: ldr x12, [sp, #32]2996; CHECK-GI-NEXT: mov w13, #127 // =0x7f2997; CHECK-GI-NEXT: and x8, x11, #0x7f2998; CHECK-GI-NEXT: and x14, x12, #0x7f2999; CHECK-GI-NEXT: mvn x18, x113000; CHECK-GI-NEXT: sub x10, x9, x83001; CHECK-GI-NEXT: sub x15, x8, #643002; CHECK-GI-NEXT: lsl x17, x1, x83003; CHECK-GI-NEXT: lsr x16, x0, x103004; CHECK-GI-NEXT: lsl x15, x0, x153005; CHECK-GI-NEXT: cmp x8, #643006; CHECK-GI-NEXT: lsl x19, x0, x83007; CHECK-GI-NEXT: lsl x0, x3, x143008; CHECK-GI-NEXT: mvn x10, x123009; CHECK-GI-NEXT: orr x16, x16, x173010; CHECK-GI-NEXT: sub x17, x14, #643011; CHECK-GI-NEXT: csel x15, x16, x15, lo3012; CHECK-GI-NEXT: sub x16, x9, x143013; CHECK-GI-NEXT: csel x8, x19, xzr, lo3014; CHECK-GI-NEXT: lsr x16, x2, x163015; CHECK-GI-NEXT: tst x11, #0x7f3016; CHECK-GI-NEXT: lsl x19, x2, x143017; CHECK-GI-NEXT: lsl x17, x2, x173018; CHECK-GI-NEXT: csel x15, x1, x15, eq3019; CHECK-GI-NEXT: cmp x14, #643020; CHECK-GI-NEXT: orr x16, x16, x03021; CHECK-GI-NEXT: bic x11, x13, x113022; CHECK-GI-NEXT: csel x14, x19, xzr, lo3023; CHECK-GI-NEXT: csel x16, x16, x17, lo3024; CHECK-GI-NEXT: tst x12, #0x7f3025; CHECK-GI-NEXT: lsr x17, x5, #13026; CHECK-GI-NEXT: extr x0, x5, x4, #13027; CHECK-GI-NEXT: bic x12, x13, x123028; CHECK-GI-NEXT: csel x13, x3, x16, eq3029; CHECK-GI-NEXT: sub x16, x9, x113030; CHECK-GI-NEXT: sub x1, x11, #643031; CHECK-GI-NEXT: lsr x3, x7, #13032; CHECK-GI-NEXT: lsr x2, x0, x113033; CHECK-GI-NEXT: lsl x16, x17, x163034; CHECK-GI-NEXT: extr x4, x7, x6, #13035; CHECK-GI-NEXT: lsr x1, x17, x13036; CHECK-GI-NEXT: cmp x11, #643037; CHECK-GI-NEXT: sub x9, x9, x123038; CHECK-GI-NEXT: orr x16, x2, x163039; CHECK-GI-NEXT: lsr x17, x17, x113040; CHECK-GI-NEXT: lsl x9, x3, x93041; CHECK-GI-NEXT: csel x16, x16, x1, lo3042; CHECK-GI-NEXT: tst x18, #0x7f3043; CHECK-GI-NEXT: sub x18, x12, #643044; CHECK-GI-NEXT: lsr x1, x4, x123045; CHECK-GI-NEXT: csel x16, x0, x16, eq3046; CHECK-GI-NEXT: cmp x11, #643047; CHECK-GI-NEXT: lsr x11, x3, x183048; CHECK-GI-NEXT: csel x17, x17, xzr, lo3049; CHECK-GI-NEXT: cmp x12, #643050; CHECK-GI-NEXT: orr x9, x1, x93051; CHECK-GI-NEXT: lsr x18, x3, x123052; CHECK-GI-NEXT: orr x0, x8, x163053; CHECK-GI-NEXT: csel x9, x9, x11, lo3054; CHECK-GI-NEXT: tst x10, #0x7f3055; CHECK-GI-NEXT: orr x1, x15, x173056; CHECK-GI-NEXT: csel x9, x4, x9, eq3057; CHECK-GI-NEXT: cmp x12, #643058; CHECK-GI-NEXT: csel x10, x18, xzr, lo3059; CHECK-GI-NEXT: orr x2, x14, x93060; CHECK-GI-NEXT: orr x3, x13, x103061; CHECK-GI-NEXT: ldr x19, [sp], #16 // 8-byte Folded Reload3062; CHECK-GI-NEXT: ret3063entry:3064 %d = call <2 x i128> @llvm.fshl(<2 x i128> %a, <2 x i128> %b, <2 x i128> %c)3065 ret <2 x i128> %d3066}3067 3068define <2 x i128> @fshr_v2i128(<2 x i128> %a, <2 x i128> %b, <2 x i128> %c) {3069; CHECK-SD-LABEL: fshr_v2i128:3070; CHECK-SD: // %bb.0: // %entry3071; CHECK-SD-NEXT: ldr x8, [sp]3072; CHECK-SD-NEXT: ldr x10, [sp, #16]3073; CHECK-SD-NEXT: tst x8, #0x403074; CHECK-SD-NEXT: mvn w13, w83075; CHECK-SD-NEXT: csel x9, x4, x5, eq3076; CHECK-SD-NEXT: csel x11, x5, x0, eq3077; CHECK-SD-NEXT: csel x14, x0, x1, eq3078; CHECK-SD-NEXT: tst x10, #0x403079; CHECK-SD-NEXT: lsr x9, x9, x83080; CHECK-SD-NEXT: lsl x12, x11, #13081; CHECK-SD-NEXT: lsr x8, x11, x83082; CHECK-SD-NEXT: lsl x11, x14, #13083; CHECK-SD-NEXT: csel x14, x7, x2, eq3084; CHECK-SD-NEXT: csel x15, x2, x3, eq3085; CHECK-SD-NEXT: csel x16, x6, x7, eq3086; CHECK-SD-NEXT: lsl x17, x14, #13087; CHECK-SD-NEXT: lsl x15, x15, #13088; CHECK-SD-NEXT: lsl x12, x12, x133089; CHECK-SD-NEXT: lsl x11, x11, x133090; CHECK-SD-NEXT: lsr x13, x16, x103091; CHECK-SD-NEXT: mvn w16, w103092; CHECK-SD-NEXT: lsr x10, x14, x103093; CHECK-SD-NEXT: lsl x17, x17, x163094; CHECK-SD-NEXT: lsl x14, x15, x163095; CHECK-SD-NEXT: orr x0, x12, x93096; CHECK-SD-NEXT: orr x1, x11, x83097; CHECK-SD-NEXT: orr x2, x17, x133098; CHECK-SD-NEXT: orr x3, x14, x103099; CHECK-SD-NEXT: ret3100;3101; CHECK-GI-LABEL: fshr_v2i128:3102; CHECK-GI: // %bb.0: // %entry3103; CHECK-GI-NEXT: ldr x9, [sp]3104; CHECK-GI-NEXT: mov w10, #127 // =0x7f3105; CHECK-GI-NEXT: mov w12, #64 // =0x403106; CHECK-GI-NEXT: lsl x13, x0, #13107; CHECK-GI-NEXT: extr x14, x1, x0, #633108; CHECK-GI-NEXT: ldr x8, [sp, #16]3109; CHECK-GI-NEXT: bic x11, x10, x93110; CHECK-GI-NEXT: mvn x16, x93111; CHECK-GI-NEXT: and x15, x9, #0x7f3112; CHECK-GI-NEXT: sub x17, x12, x113113; CHECK-GI-NEXT: sub x18, x11, #643114; CHECK-GI-NEXT: lsl x0, x14, x113115; CHECK-GI-NEXT: lsr x17, x13, x173116; CHECK-GI-NEXT: lsl x1, x13, x113117; CHECK-GI-NEXT: lsl x13, x13, x183118; CHECK-GI-NEXT: bic x10, x10, x83119; CHECK-GI-NEXT: lsl x18, x2, #13120; CHECK-GI-NEXT: cmp x11, #643121; CHECK-GI-NEXT: orr x17, x17, x03122; CHECK-GI-NEXT: extr x11, x3, x2, #633123; CHECK-GI-NEXT: csel x0, x1, xzr, lo3124; CHECK-GI-NEXT: csel x13, x17, x13, lo3125; CHECK-GI-NEXT: sub x17, x12, x103126; CHECK-GI-NEXT: tst x16, #0x7f3127; CHECK-GI-NEXT: sub x16, x10, #643128; CHECK-GI-NEXT: lsr x17, x18, x173129; CHECK-GI-NEXT: lsl x2, x11, x103130; CHECK-GI-NEXT: lsl x1, x18, x103131; CHECK-GI-NEXT: csel x13, x14, x13, eq3132; CHECK-GI-NEXT: lsl x14, x18, x163133; CHECK-GI-NEXT: cmp x10, #643134; CHECK-GI-NEXT: mvn x10, x83135; CHECK-GI-NEXT: orr x16, x17, x23136; CHECK-GI-NEXT: csel x17, x1, xzr, lo3137; CHECK-GI-NEXT: csel x14, x16, x14, lo3138; CHECK-GI-NEXT: tst x10, #0x7f3139; CHECK-GI-NEXT: sub x10, x12, x153140; CHECK-GI-NEXT: sub x16, x15, #643141; CHECK-GI-NEXT: lsr x18, x4, x153142; CHECK-GI-NEXT: lsl x10, x5, x103143; CHECK-GI-NEXT: csel x11, x11, x14, eq3144; CHECK-GI-NEXT: lsr x14, x5, x163145; CHECK-GI-NEXT: and x1, x8, #0x7f3146; CHECK-GI-NEXT: cmp x15, #643147; CHECK-GI-NEXT: lsr x16, x5, x153148; CHECK-GI-NEXT: orr x10, x18, x103149; CHECK-GI-NEXT: csel x10, x10, x14, lo3150; CHECK-GI-NEXT: tst x9, #0x7f3151; CHECK-GI-NEXT: sub x9, x12, x13152; CHECK-GI-NEXT: sub x12, x1, #643153; CHECK-GI-NEXT: lsr x14, x6, x13154; CHECK-GI-NEXT: lsl x9, x7, x93155; CHECK-GI-NEXT: csel x10, x4, x10, eq3156; CHECK-GI-NEXT: cmp x15, #643157; CHECK-GI-NEXT: lsr x12, x7, x123158; CHECK-GI-NEXT: csel x15, x16, xzr, lo3159; CHECK-GI-NEXT: orr x9, x14, x93160; CHECK-GI-NEXT: cmp x1, #643161; CHECK-GI-NEXT: lsr x14, x7, x13162; CHECK-GI-NEXT: csel x9, x9, x12, lo3163; CHECK-GI-NEXT: tst x8, #0x7f3164; CHECK-GI-NEXT: csel x8, x6, x9, eq3165; CHECK-GI-NEXT: cmp x1, #643166; CHECK-GI-NEXT: orr x0, x0, x103167; CHECK-GI-NEXT: csel x9, x14, xzr, lo3168; CHECK-GI-NEXT: orr x1, x13, x153169; CHECK-GI-NEXT: orr x2, x17, x83170; CHECK-GI-NEXT: orr x3, x11, x93171; CHECK-GI-NEXT: ret3172entry:3173 %d = call <2 x i128> @llvm.fshr(<2 x i128> %a, <2 x i128> %b, <2 x i128> %c)3174 ret <2 x i128> %d3175}3176 3177define <8 x i8> @rotl_v8i8_c(<8 x i8> %a) {3178; CHECK-SD-LABEL: rotl_v8i8_c:3179; CHECK-SD: // %bb.0: // %entry3180; CHECK-SD-NEXT: shl v1.8b, v0.8b, #33181; CHECK-SD-NEXT: usra v1.8b, v0.8b, #53182; CHECK-SD-NEXT: fmov d0, d13183; CHECK-SD-NEXT: ret3184;3185; CHECK-GI-LABEL: rotl_v8i8_c:3186; CHECK-GI: // %bb.0: // %entry3187; CHECK-GI-NEXT: shl v1.8b, v0.8b, #33188; CHECK-GI-NEXT: ushr v0.8b, v0.8b, #53189; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b3190; CHECK-GI-NEXT: ret3191entry:3192 %d = call <8 x i8> @llvm.fshl(<8 x i8> %a, <8 x i8> %a, <8 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)3193 ret <8 x i8> %d3194}3195 3196define <8 x i8> @rotr_v8i8_c(<8 x i8> %a) {3197; CHECK-SD-LABEL: rotr_v8i8_c:3198; CHECK-SD: // %bb.0: // %entry3199; CHECK-SD-NEXT: shl v1.8b, v0.8b, #53200; CHECK-SD-NEXT: usra v1.8b, v0.8b, #33201; CHECK-SD-NEXT: fmov d0, d13202; CHECK-SD-NEXT: ret3203;3204; CHECK-GI-LABEL: rotr_v8i8_c:3205; CHECK-GI: // %bb.0: // %entry3206; CHECK-GI-NEXT: ushr v1.8b, v0.8b, #33207; CHECK-GI-NEXT: shl v0.8b, v0.8b, #53208; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b3209; CHECK-GI-NEXT: ret3210entry:3211 %d = call <8 x i8> @llvm.fshr(<8 x i8> %a, <8 x i8> %a, <8 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)3212 ret <8 x i8> %d3213}3214 3215define <16 x i8> @rotl_v16i8_c(<16 x i8> %a) {3216; CHECK-SD-LABEL: rotl_v16i8_c:3217; CHECK-SD: // %bb.0: // %entry3218; CHECK-SD-NEXT: shl v1.16b, v0.16b, #33219; CHECK-SD-NEXT: usra v1.16b, v0.16b, #53220; CHECK-SD-NEXT: mov v0.16b, v1.16b3221; CHECK-SD-NEXT: ret3222;3223; CHECK-GI-LABEL: rotl_v16i8_c:3224; CHECK-GI: // %bb.0: // %entry3225; CHECK-GI-NEXT: shl v1.16b, v0.16b, #33226; CHECK-GI-NEXT: ushr v0.16b, v0.16b, #53227; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b3228; CHECK-GI-NEXT: ret3229entry:3230 %d = call <16 x i8> @llvm.fshl(<16 x i8> %a, <16 x i8> %a, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)3231 ret <16 x i8> %d3232}3233 3234define <16 x i8> @rotr_v16i8_c(<16 x i8> %a) {3235; CHECK-SD-LABEL: rotr_v16i8_c:3236; CHECK-SD: // %bb.0: // %entry3237; CHECK-SD-NEXT: shl v1.16b, v0.16b, #53238; CHECK-SD-NEXT: usra v1.16b, v0.16b, #33239; CHECK-SD-NEXT: mov v0.16b, v1.16b3240; CHECK-SD-NEXT: ret3241;3242; CHECK-GI-LABEL: rotr_v16i8_c:3243; CHECK-GI: // %bb.0: // %entry3244; CHECK-GI-NEXT: ushr v1.16b, v0.16b, #33245; CHECK-GI-NEXT: shl v0.16b, v0.16b, #53246; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b3247; CHECK-GI-NEXT: ret3248entry:3249 %d = call <16 x i8> @llvm.fshr(<16 x i8> %a, <16 x i8> %a, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)3250 ret <16 x i8> %d3251}3252 3253define <4 x i16> @rotl_v4i16_c(<4 x i16> %a) {3254; CHECK-SD-LABEL: rotl_v4i16_c:3255; CHECK-SD: // %bb.0: // %entry3256; CHECK-SD-NEXT: shl v1.4h, v0.4h, #33257; CHECK-SD-NEXT: usra v1.4h, v0.4h, #133258; CHECK-SD-NEXT: fmov d0, d13259; CHECK-SD-NEXT: ret3260;3261; CHECK-GI-LABEL: rotl_v4i16_c:3262; CHECK-GI: // %bb.0: // %entry3263; CHECK-GI-NEXT: shl v1.4h, v0.4h, #33264; CHECK-GI-NEXT: ushr v0.4h, v0.4h, #133265; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b3266; CHECK-GI-NEXT: ret3267entry:3268 %d = call <4 x i16> @llvm.fshl(<4 x i16> %a, <4 x i16> %a, <4 x i16> <i16 3, i16 3, i16 3, i16 3>)3269 ret <4 x i16> %d3270}3271 3272define <4 x i16> @rotr_v4i16_c(<4 x i16> %a) {3273; CHECK-SD-LABEL: rotr_v4i16_c:3274; CHECK-SD: // %bb.0: // %entry3275; CHECK-SD-NEXT: shl v1.4h, v0.4h, #133276; CHECK-SD-NEXT: usra v1.4h, v0.4h, #33277; CHECK-SD-NEXT: fmov d0, d13278; CHECK-SD-NEXT: ret3279;3280; CHECK-GI-LABEL: rotr_v4i16_c:3281; CHECK-GI: // %bb.0: // %entry3282; CHECK-GI-NEXT: ushr v1.4h, v0.4h, #33283; CHECK-GI-NEXT: shl v0.4h, v0.4h, #133284; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b3285; CHECK-GI-NEXT: ret3286entry:3287 %d = call <4 x i16> @llvm.fshr(<4 x i16> %a, <4 x i16> %a, <4 x i16> <i16 3, i16 3, i16 3, i16 3>)3288 ret <4 x i16> %d3289}3290 3291define <7 x i16> @rotl_v7i16_c(<7 x i16> %a) {3292; CHECK-SD-LABEL: rotl_v7i16_c:3293; CHECK-SD: // %bb.0: // %entry3294; CHECK-SD-NEXT: adrp x8, .LCPI98_03295; CHECK-SD-NEXT: adrp x9, .LCPI98_13296; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI98_0]3297; CHECK-SD-NEXT: ldr q2, [x9, :lo12:.LCPI98_1]3298; CHECK-SD-NEXT: ushl v1.8h, v0.8h, v1.8h3299; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h3300; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b3301; CHECK-SD-NEXT: ret3302;3303; CHECK-GI-LABEL: rotl_v7i16_c:3304; CHECK-GI: // %bb.0: // %entry3305; CHECK-GI-NEXT: mov w8, #13 // =0xd3306; CHECK-GI-NEXT: mov w9, #3 // =0x33307; CHECK-GI-NEXT: fmov s1, w83308; CHECK-GI-NEXT: fmov s2, w93309; CHECK-GI-NEXT: mov v1.h[1], w83310; CHECK-GI-NEXT: mov v2.h[1], w93311; CHECK-GI-NEXT: mov v1.h[2], w83312; CHECK-GI-NEXT: mov v2.h[2], w93313; CHECK-GI-NEXT: mov v1.h[3], w83314; CHECK-GI-NEXT: mov v2.h[3], w93315; CHECK-GI-NEXT: mov v1.h[4], w83316; CHECK-GI-NEXT: mov v2.h[4], w93317; CHECK-GI-NEXT: mov v1.h[5], w83318; CHECK-GI-NEXT: mov v2.h[5], w93319; CHECK-GI-NEXT: mov v1.h[6], w83320; CHECK-GI-NEXT: mov v2.h[6], w93321; CHECK-GI-NEXT: neg v1.8h, v1.8h3322; CHECK-GI-NEXT: ushl v2.8h, v0.8h, v2.8h3323; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v1.8h3324; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b3325; CHECK-GI-NEXT: ret3326entry:3327 %d = call <7 x i16> @llvm.fshl(<7 x i16> %a, <7 x i16> %a, <7 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)3328 ret <7 x i16> %d3329}3330 3331define <7 x i16> @rotr_v7i16_c(<7 x i16> %a) {3332; CHECK-SD-LABEL: rotr_v7i16_c:3333; CHECK-SD: // %bb.0: // %entry3334; CHECK-SD-NEXT: adrp x8, .LCPI99_03335; CHECK-SD-NEXT: adrp x9, .LCPI99_13336; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI99_0]3337; CHECK-SD-NEXT: ldr q2, [x9, :lo12:.LCPI99_1]3338; CHECK-SD-NEXT: ushl v1.8h, v0.8h, v1.8h3339; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h3340; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b3341; CHECK-SD-NEXT: ret3342;3343; CHECK-GI-LABEL: rotr_v7i16_c:3344; CHECK-GI: // %bb.0: // %entry3345; CHECK-GI-NEXT: mov w8, #3 // =0x33346; CHECK-GI-NEXT: mov w9, #13 // =0xd3347; CHECK-GI-NEXT: fmov s1, w83348; CHECK-GI-NEXT: fmov s2, w93349; CHECK-GI-NEXT: mov v1.h[1], w83350; CHECK-GI-NEXT: mov v2.h[1], w93351; CHECK-GI-NEXT: mov v1.h[2], w83352; CHECK-GI-NEXT: mov v2.h[2], w93353; CHECK-GI-NEXT: mov v1.h[3], w83354; CHECK-GI-NEXT: mov v2.h[3], w93355; CHECK-GI-NEXT: mov v1.h[4], w83356; CHECK-GI-NEXT: mov v2.h[4], w93357; CHECK-GI-NEXT: mov v1.h[5], w83358; CHECK-GI-NEXT: mov v2.h[5], w93359; CHECK-GI-NEXT: mov v1.h[6], w83360; CHECK-GI-NEXT: mov v2.h[6], w93361; CHECK-GI-NEXT: neg v1.8h, v1.8h3362; CHECK-GI-NEXT: ushl v1.8h, v0.8h, v1.8h3363; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h3364; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b3365; CHECK-GI-NEXT: ret3366entry:3367 %d = call <7 x i16> @llvm.fshr(<7 x i16> %a, <7 x i16> %a, <7 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)3368 ret <7 x i16> %d3369}3370 3371define <8 x i16> @rotl_v8i16_c(<8 x i16> %a) {3372; CHECK-SD-LABEL: rotl_v8i16_c:3373; CHECK-SD: // %bb.0: // %entry3374; CHECK-SD-NEXT: shl v1.8h, v0.8h, #33375; CHECK-SD-NEXT: usra v1.8h, v0.8h, #133376; CHECK-SD-NEXT: mov v0.16b, v1.16b3377; CHECK-SD-NEXT: ret3378;3379; CHECK-GI-LABEL: rotl_v8i16_c:3380; CHECK-GI: // %bb.0: // %entry3381; CHECK-GI-NEXT: shl v1.8h, v0.8h, #33382; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #133383; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b3384; CHECK-GI-NEXT: ret3385entry:3386 %d = call <8 x i16> @llvm.fshl(<8 x i16> %a, <8 x i16> %a, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)3387 ret <8 x i16> %d3388}3389 3390define <8 x i16> @rotr_v8i16_c(<8 x i16> %a) {3391; CHECK-SD-LABEL: rotr_v8i16_c:3392; CHECK-SD: // %bb.0: // %entry3393; CHECK-SD-NEXT: shl v1.8h, v0.8h, #133394; CHECK-SD-NEXT: usra v1.8h, v0.8h, #33395; CHECK-SD-NEXT: mov v0.16b, v1.16b3396; CHECK-SD-NEXT: ret3397;3398; CHECK-GI-LABEL: rotr_v8i16_c:3399; CHECK-GI: // %bb.0: // %entry3400; CHECK-GI-NEXT: ushr v1.8h, v0.8h, #33401; CHECK-GI-NEXT: shl v0.8h, v0.8h, #133402; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b3403; CHECK-GI-NEXT: ret3404entry:3405 %d = call <8 x i16> @llvm.fshr(<8 x i16> %a, <8 x i16> %a, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)3406 ret <8 x i16> %d3407}3408 3409define <16 x i16> @rotl_v16i16_c(<16 x i16> %a) {3410; CHECK-SD-LABEL: rotl_v16i16_c:3411; CHECK-SD: // %bb.0: // %entry3412; CHECK-SD-NEXT: shl v2.8h, v0.8h, #33413; CHECK-SD-NEXT: shl v3.8h, v1.8h, #33414; CHECK-SD-NEXT: usra v2.8h, v0.8h, #133415; CHECK-SD-NEXT: usra v3.8h, v1.8h, #133416; CHECK-SD-NEXT: mov v0.16b, v2.16b3417; CHECK-SD-NEXT: mov v1.16b, v3.16b3418; CHECK-SD-NEXT: ret3419;3420; CHECK-GI-LABEL: rotl_v16i16_c:3421; CHECK-GI: // %bb.0: // %entry3422; CHECK-GI-NEXT: shl v2.8h, v0.8h, #33423; CHECK-GI-NEXT: shl v3.8h, v1.8h, #33424; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #133425; CHECK-GI-NEXT: ushr v1.8h, v1.8h, #133426; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b3427; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b3428; CHECK-GI-NEXT: ret3429entry:3430 %d = call <16 x i16> @llvm.fshl(<16 x i16> %a, <16 x i16> %a, <16 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)3431 ret <16 x i16> %d3432}3433 3434define <16 x i16> @rotr_v16i16_c(<16 x i16> %a) {3435; CHECK-SD-LABEL: rotr_v16i16_c:3436; CHECK-SD: // %bb.0: // %entry3437; CHECK-SD-NEXT: shl v2.8h, v0.8h, #133438; CHECK-SD-NEXT: shl v3.8h, v1.8h, #133439; CHECK-SD-NEXT: usra v2.8h, v0.8h, #33440; CHECK-SD-NEXT: usra v3.8h, v1.8h, #33441; CHECK-SD-NEXT: mov v0.16b, v2.16b3442; CHECK-SD-NEXT: mov v1.16b, v3.16b3443; CHECK-SD-NEXT: ret3444;3445; CHECK-GI-LABEL: rotr_v16i16_c:3446; CHECK-GI: // %bb.0: // %entry3447; CHECK-GI-NEXT: ushr v2.8h, v0.8h, #33448; CHECK-GI-NEXT: ushr v3.8h, v1.8h, #33449; CHECK-GI-NEXT: shl v0.8h, v0.8h, #133450; CHECK-GI-NEXT: shl v1.8h, v1.8h, #133451; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b3452; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b3453; CHECK-GI-NEXT: ret3454entry:3455 %d = call <16 x i16> @llvm.fshr(<16 x i16> %a, <16 x i16> %a, <16 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)3456 ret <16 x i16> %d3457}3458 3459define <2 x i32> @rotl_v2i32_c(<2 x i32> %a) {3460; CHECK-SD-LABEL: rotl_v2i32_c:3461; CHECK-SD: // %bb.0: // %entry3462; CHECK-SD-NEXT: shl v1.2s, v0.2s, #33463; CHECK-SD-NEXT: usra v1.2s, v0.2s, #293464; CHECK-SD-NEXT: fmov d0, d13465; CHECK-SD-NEXT: ret3466;3467; CHECK-GI-LABEL: rotl_v2i32_c:3468; CHECK-GI: // %bb.0: // %entry3469; CHECK-GI-NEXT: shl v1.2s, v0.2s, #33470; CHECK-GI-NEXT: ushr v0.2s, v0.2s, #293471; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b3472; CHECK-GI-NEXT: ret3473entry:3474 %d = call <2 x i32> @llvm.fshl(<2 x i32> %a, <2 x i32> %a, <2 x i32> <i32 3, i32 3>)3475 ret <2 x i32> %d3476}3477 3478define <2 x i32> @rotr_v2i32_c(<2 x i32> %a) {3479; CHECK-SD-LABEL: rotr_v2i32_c:3480; CHECK-SD: // %bb.0: // %entry3481; CHECK-SD-NEXT: shl v1.2s, v0.2s, #293482; CHECK-SD-NEXT: usra v1.2s, v0.2s, #33483; CHECK-SD-NEXT: fmov d0, d13484; CHECK-SD-NEXT: ret3485;3486; CHECK-GI-LABEL: rotr_v2i32_c:3487; CHECK-GI: // %bb.0: // %entry3488; CHECK-GI-NEXT: ushr v1.2s, v0.2s, #33489; CHECK-GI-NEXT: shl v0.2s, v0.2s, #293490; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b3491; CHECK-GI-NEXT: ret3492entry:3493 %d = call <2 x i32> @llvm.fshr(<2 x i32> %a, <2 x i32> %a, <2 x i32> <i32 3, i32 3>)3494 ret <2 x i32> %d3495}3496 3497define <4 x i32> @rotl_v4i32_c(<4 x i32> %a) {3498; CHECK-SD-LABEL: rotl_v4i32_c:3499; CHECK-SD: // %bb.0: // %entry3500; CHECK-SD-NEXT: shl v1.4s, v0.4s, #33501; CHECK-SD-NEXT: usra v1.4s, v0.4s, #293502; CHECK-SD-NEXT: mov v0.16b, v1.16b3503; CHECK-SD-NEXT: ret3504;3505; CHECK-GI-LABEL: rotl_v4i32_c:3506; CHECK-GI: // %bb.0: // %entry3507; CHECK-GI-NEXT: shl v1.4s, v0.4s, #33508; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #293509; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b3510; CHECK-GI-NEXT: ret3511entry:3512 %d = call <4 x i32> @llvm.fshl(<4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)3513 ret <4 x i32> %d3514}3515 3516define <4 x i32> @rotr_v4i32_c(<4 x i32> %a) {3517; CHECK-SD-LABEL: rotr_v4i32_c:3518; CHECK-SD: // %bb.0: // %entry3519; CHECK-SD-NEXT: shl v1.4s, v0.4s, #293520; CHECK-SD-NEXT: usra v1.4s, v0.4s, #33521; CHECK-SD-NEXT: mov v0.16b, v1.16b3522; CHECK-SD-NEXT: ret3523;3524; CHECK-GI-LABEL: rotr_v4i32_c:3525; CHECK-GI: // %bb.0: // %entry3526; CHECK-GI-NEXT: ushr v1.4s, v0.4s, #33527; CHECK-GI-NEXT: shl v0.4s, v0.4s, #293528; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b3529; CHECK-GI-NEXT: ret3530entry:3531 %d = call <4 x i32> @llvm.fshr(<4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)3532 ret <4 x i32> %d3533}3534 3535define <7 x i32> @rotl_v7i32_c(<7 x i32> %a) {3536; CHECK-SD-LABEL: rotl_v7i32_c:3537; CHECK-SD: // %bb.0: // %entry3538; CHECK-SD-NEXT: fmov s0, w03539; CHECK-SD-NEXT: fmov s1, w43540; CHECK-SD-NEXT: mov v0.s[1], w13541; CHECK-SD-NEXT: mov v1.s[1], w53542; CHECK-SD-NEXT: mov v0.s[2], w23543; CHECK-SD-NEXT: mov v1.s[2], w63544; CHECK-SD-NEXT: mov v0.s[3], w33545; CHECK-SD-NEXT: shl v3.4s, v1.4s, #33546; CHECK-SD-NEXT: usra v3.4s, v1.4s, #293547; CHECK-SD-NEXT: shl v2.4s, v0.4s, #33548; CHECK-SD-NEXT: mov w5, v3.s[1]3549; CHECK-SD-NEXT: mov w6, v3.s[2]3550; CHECK-SD-NEXT: fmov w4, s33551; CHECK-SD-NEXT: usra v2.4s, v0.4s, #293552; CHECK-SD-NEXT: mov w1, v2.s[1]3553; CHECK-SD-NEXT: mov w2, v2.s[2]3554; CHECK-SD-NEXT: mov w3, v2.s[3]3555; CHECK-SD-NEXT: fmov w0, s23556; CHECK-SD-NEXT: ret3557;3558; CHECK-GI-LABEL: rotl_v7i32_c:3559; CHECK-GI: // %bb.0: // %entry3560; CHECK-GI-NEXT: fmov s0, w03561; CHECK-GI-NEXT: fmov s1, w03562; CHECK-GI-NEXT: mov w8, #29 // =0x1d3563; CHECK-GI-NEXT: fmov s2, w83564; CHECK-GI-NEXT: mov w9, #3 // =0x33565; CHECK-GI-NEXT: fmov s3, w43566; CHECK-GI-NEXT: fmov s4, w43567; CHECK-GI-NEXT: fmov s5, w93568; CHECK-GI-NEXT: mov v1.s[1], w13569; CHECK-GI-NEXT: mov v0.s[1], w13570; CHECK-GI-NEXT: mov v2.s[1], w83571; CHECK-GI-NEXT: mov v3.s[1], w53572; CHECK-GI-NEXT: mov v4.s[1], w53573; CHECK-GI-NEXT: mov v5.s[1], w93574; CHECK-GI-NEXT: mov v1.s[2], w23575; CHECK-GI-NEXT: mov v0.s[2], w23576; CHECK-GI-NEXT: mov v2.s[2], w83577; CHECK-GI-NEXT: mov v3.s[2], w63578; CHECK-GI-NEXT: mov v4.s[2], w63579; CHECK-GI-NEXT: mov v5.s[2], w93580; CHECK-GI-NEXT: mov v1.s[3], w33581; CHECK-GI-NEXT: mov v0.s[3], w33582; CHECK-GI-NEXT: neg v2.4s, v2.4s3583; CHECK-GI-NEXT: ushl v4.4s, v4.4s, v5.4s3584; CHECK-GI-NEXT: shl v1.4s, v1.4s, #33585; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #293586; CHECK-GI-NEXT: ushl v2.4s, v3.4s, v2.4s3587; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b3588; CHECK-GI-NEXT: orr v1.16b, v4.16b, v2.16b3589; CHECK-GI-NEXT: mov s2, v0.s[1]3590; CHECK-GI-NEXT: mov s3, v0.s[2]3591; CHECK-GI-NEXT: mov s4, v0.s[3]3592; CHECK-GI-NEXT: mov s5, v1.s[1]3593; CHECK-GI-NEXT: mov s6, v1.s[2]3594; CHECK-GI-NEXT: fmov w0, s03595; CHECK-GI-NEXT: fmov w4, s13596; CHECK-GI-NEXT: fmov w1, s23597; CHECK-GI-NEXT: fmov w2, s33598; CHECK-GI-NEXT: fmov w3, s43599; CHECK-GI-NEXT: fmov w5, s53600; CHECK-GI-NEXT: fmov w6, s63601; CHECK-GI-NEXT: ret3602entry:3603 %d = call <7 x i32> @llvm.fshl(<7 x i32> %a, <7 x i32> %a, <7 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>)3604 ret <7 x i32> %d3605}3606 3607define <7 x i32> @rotr_v7i32_c(<7 x i32> %a) {3608; CHECK-SD-LABEL: rotr_v7i32_c:3609; CHECK-SD: // %bb.0: // %entry3610; CHECK-SD-NEXT: fmov s0, w03611; CHECK-SD-NEXT: fmov s1, w43612; CHECK-SD-NEXT: mov v0.s[1], w13613; CHECK-SD-NEXT: mov v1.s[1], w53614; CHECK-SD-NEXT: mov v0.s[2], w23615; CHECK-SD-NEXT: mov v1.s[2], w63616; CHECK-SD-NEXT: mov v0.s[3], w33617; CHECK-SD-NEXT: shl v3.4s, v1.4s, #293618; CHECK-SD-NEXT: usra v3.4s, v1.4s, #33619; CHECK-SD-NEXT: shl v2.4s, v0.4s, #293620; CHECK-SD-NEXT: mov w5, v3.s[1]3621; CHECK-SD-NEXT: mov w6, v3.s[2]3622; CHECK-SD-NEXT: fmov w4, s33623; CHECK-SD-NEXT: usra v2.4s, v0.4s, #33624; CHECK-SD-NEXT: mov w1, v2.s[1]3625; CHECK-SD-NEXT: mov w2, v2.s[2]3626; CHECK-SD-NEXT: mov w3, v2.s[3]3627; CHECK-SD-NEXT: fmov w0, s23628; CHECK-SD-NEXT: ret3629;3630; CHECK-GI-LABEL: rotr_v7i32_c:3631; CHECK-GI: // %bb.0: // %entry3632; CHECK-GI-NEXT: fmov s0, w03633; CHECK-GI-NEXT: fmov s1, w03634; CHECK-GI-NEXT: mov w8, #3 // =0x33635; CHECK-GI-NEXT: fmov s2, w83636; CHECK-GI-NEXT: mov w9, #29 // =0x1d3637; CHECK-GI-NEXT: fmov s3, w43638; CHECK-GI-NEXT: fmov s4, w43639; CHECK-GI-NEXT: fmov s5, w93640; CHECK-GI-NEXT: mov v1.s[1], w13641; CHECK-GI-NEXT: mov v0.s[1], w13642; CHECK-GI-NEXT: mov v2.s[1], w83643; CHECK-GI-NEXT: mov v3.s[1], w53644; CHECK-GI-NEXT: mov v4.s[1], w53645; CHECK-GI-NEXT: mov v5.s[1], w93646; CHECK-GI-NEXT: mov v1.s[2], w23647; CHECK-GI-NEXT: mov v0.s[2], w23648; CHECK-GI-NEXT: mov v2.s[2], w83649; CHECK-GI-NEXT: mov v3.s[2], w63650; CHECK-GI-NEXT: mov v4.s[2], w63651; CHECK-GI-NEXT: mov v5.s[2], w93652; CHECK-GI-NEXT: mov v1.s[3], w33653; CHECK-GI-NEXT: mov v0.s[3], w33654; CHECK-GI-NEXT: neg v2.4s, v2.4s3655; CHECK-GI-NEXT: ushl v3.4s, v3.4s, v5.4s3656; CHECK-GI-NEXT: ushr v1.4s, v1.4s, #33657; CHECK-GI-NEXT: shl v0.4s, v0.4s, #293658; CHECK-GI-NEXT: ushl v2.4s, v4.4s, v2.4s3659; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b3660; CHECK-GI-NEXT: orr v1.16b, v2.16b, v3.16b3661; CHECK-GI-NEXT: mov s2, v0.s[1]3662; CHECK-GI-NEXT: mov s3, v0.s[2]3663; CHECK-GI-NEXT: mov s4, v0.s[3]3664; CHECK-GI-NEXT: mov s5, v1.s[1]3665; CHECK-GI-NEXT: mov s6, v1.s[2]3666; CHECK-GI-NEXT: fmov w0, s03667; CHECK-GI-NEXT: fmov w4, s13668; CHECK-GI-NEXT: fmov w1, s23669; CHECK-GI-NEXT: fmov w2, s33670; CHECK-GI-NEXT: fmov w3, s43671; CHECK-GI-NEXT: fmov w5, s53672; CHECK-GI-NEXT: fmov w6, s63673; CHECK-GI-NEXT: ret3674entry:3675 %d = call <7 x i32> @llvm.fshr(<7 x i32> %a, <7 x i32> %a, <7 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>)3676 ret <7 x i32> %d3677}3678 3679define <8 x i32> @rotl_v8i32_c(<8 x i32> %a) {3680; CHECK-SD-LABEL: rotl_v8i32_c:3681; CHECK-SD: // %bb.0: // %entry3682; CHECK-SD-NEXT: shl v2.4s, v0.4s, #33683; CHECK-SD-NEXT: shl v3.4s, v1.4s, #33684; CHECK-SD-NEXT: usra v2.4s, v0.4s, #293685; CHECK-SD-NEXT: usra v3.4s, v1.4s, #293686; CHECK-SD-NEXT: mov v0.16b, v2.16b3687; CHECK-SD-NEXT: mov v1.16b, v3.16b3688; CHECK-SD-NEXT: ret3689;3690; CHECK-GI-LABEL: rotl_v8i32_c:3691; CHECK-GI: // %bb.0: // %entry3692; CHECK-GI-NEXT: shl v2.4s, v0.4s, #33693; CHECK-GI-NEXT: shl v3.4s, v1.4s, #33694; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #293695; CHECK-GI-NEXT: ushr v1.4s, v1.4s, #293696; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b3697; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b3698; CHECK-GI-NEXT: ret3699entry:3700 %d = call <8 x i32> @llvm.fshl(<8 x i32> %a, <8 x i32> %a, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>)3701 ret <8 x i32> %d3702}3703 3704define <8 x i32> @rotr_v8i32_c(<8 x i32> %a) {3705; CHECK-SD-LABEL: rotr_v8i32_c:3706; CHECK-SD: // %bb.0: // %entry3707; CHECK-SD-NEXT: shl v2.4s, v0.4s, #293708; CHECK-SD-NEXT: shl v3.4s, v1.4s, #293709; CHECK-SD-NEXT: usra v2.4s, v0.4s, #33710; CHECK-SD-NEXT: usra v3.4s, v1.4s, #33711; CHECK-SD-NEXT: mov v0.16b, v2.16b3712; CHECK-SD-NEXT: mov v1.16b, v3.16b3713; CHECK-SD-NEXT: ret3714;3715; CHECK-GI-LABEL: rotr_v8i32_c:3716; CHECK-GI: // %bb.0: // %entry3717; CHECK-GI-NEXT: ushr v2.4s, v0.4s, #33718; CHECK-GI-NEXT: ushr v3.4s, v1.4s, #33719; CHECK-GI-NEXT: shl v0.4s, v0.4s, #293720; CHECK-GI-NEXT: shl v1.4s, v1.4s, #293721; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b3722; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b3723; CHECK-GI-NEXT: ret3724entry:3725 %d = call <8 x i32> @llvm.fshr(<8 x i32> %a, <8 x i32> %a, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>)3726 ret <8 x i32> %d3727}3728 3729define <2 x i64> @rotl_v2i64_c(<2 x i64> %a) {3730; CHECK-SD-LABEL: rotl_v2i64_c:3731; CHECK-SD: // %bb.0: // %entry3732; CHECK-SD-NEXT: shl v1.2d, v0.2d, #33733; CHECK-SD-NEXT: usra v1.2d, v0.2d, #613734; CHECK-SD-NEXT: mov v0.16b, v1.16b3735; CHECK-SD-NEXT: ret3736;3737; CHECK-GI-LABEL: rotl_v2i64_c:3738; CHECK-GI: // %bb.0: // %entry3739; CHECK-GI-NEXT: shl v1.2d, v0.2d, #33740; CHECK-GI-NEXT: ushr v0.2d, v0.2d, #613741; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b3742; CHECK-GI-NEXT: ret3743entry:3744 %d = call <2 x i64> @llvm.fshl(<2 x i64> %a, <2 x i64> %a, <2 x i64> <i64 3, i64 3>)3745 ret <2 x i64> %d3746}3747 3748define <2 x i64> @rotr_v2i64_c(<2 x i64> %a) {3749; CHECK-SD-LABEL: rotr_v2i64_c:3750; CHECK-SD: // %bb.0: // %entry3751; CHECK-SD-NEXT: shl v1.2d, v0.2d, #613752; CHECK-SD-NEXT: usra v1.2d, v0.2d, #33753; CHECK-SD-NEXT: mov v0.16b, v1.16b3754; CHECK-SD-NEXT: ret3755;3756; CHECK-GI-LABEL: rotr_v2i64_c:3757; CHECK-GI: // %bb.0: // %entry3758; CHECK-GI-NEXT: ushr v1.2d, v0.2d, #33759; CHECK-GI-NEXT: shl v0.2d, v0.2d, #613760; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b3761; CHECK-GI-NEXT: ret3762entry:3763 %d = call <2 x i64> @llvm.fshr(<2 x i64> %a, <2 x i64> %a, <2 x i64> <i64 3, i64 3>)3764 ret <2 x i64> %d3765}3766 3767define <4 x i64> @rotl_v4i64_c(<4 x i64> %a) {3768; CHECK-SD-LABEL: rotl_v4i64_c:3769; CHECK-SD: // %bb.0: // %entry3770; CHECK-SD-NEXT: shl v2.2d, v0.2d, #33771; CHECK-SD-NEXT: shl v3.2d, v1.2d, #33772; CHECK-SD-NEXT: usra v2.2d, v0.2d, #613773; CHECK-SD-NEXT: usra v3.2d, v1.2d, #613774; CHECK-SD-NEXT: mov v0.16b, v2.16b3775; CHECK-SD-NEXT: mov v1.16b, v3.16b3776; CHECK-SD-NEXT: ret3777;3778; CHECK-GI-LABEL: rotl_v4i64_c:3779; CHECK-GI: // %bb.0: // %entry3780; CHECK-GI-NEXT: shl v2.2d, v0.2d, #33781; CHECK-GI-NEXT: shl v3.2d, v1.2d, #33782; CHECK-GI-NEXT: ushr v0.2d, v0.2d, #613783; CHECK-GI-NEXT: ushr v1.2d, v1.2d, #613784; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b3785; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b3786; CHECK-GI-NEXT: ret3787entry:3788 %d = call <4 x i64> @llvm.fshl(<4 x i64> %a, <4 x i64> %a, <4 x i64> <i64 3, i64 3, i64 3, i64 3>)3789 ret <4 x i64> %d3790}3791 3792define <4 x i64> @rotr_v4i64_c(<4 x i64> %a) {3793; CHECK-SD-LABEL: rotr_v4i64_c:3794; CHECK-SD: // %bb.0: // %entry3795; CHECK-SD-NEXT: shl v2.2d, v0.2d, #613796; CHECK-SD-NEXT: shl v3.2d, v1.2d, #613797; CHECK-SD-NEXT: usra v2.2d, v0.2d, #33798; CHECK-SD-NEXT: usra v3.2d, v1.2d, #33799; CHECK-SD-NEXT: mov v0.16b, v2.16b3800; CHECK-SD-NEXT: mov v1.16b, v3.16b3801; CHECK-SD-NEXT: ret3802;3803; CHECK-GI-LABEL: rotr_v4i64_c:3804; CHECK-GI: // %bb.0: // %entry3805; CHECK-GI-NEXT: ushr v2.2d, v0.2d, #33806; CHECK-GI-NEXT: ushr v3.2d, v1.2d, #33807; CHECK-GI-NEXT: shl v0.2d, v0.2d, #613808; CHECK-GI-NEXT: shl v1.2d, v1.2d, #613809; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b3810; CHECK-GI-NEXT: orr v1.16b, v3.16b, v1.16b3811; CHECK-GI-NEXT: ret3812entry:3813 %d = call <4 x i64> @llvm.fshr(<4 x i64> %a, <4 x i64> %a, <4 x i64> <i64 3, i64 3, i64 3, i64 3>)3814 ret <4 x i64> %d3815}3816 3817define <2 x i128> @rotl_v2i128_c(<2 x i128> %a) {3818; CHECK-SD-LABEL: rotl_v2i128_c:3819; CHECK-SD: // %bb.0: // %entry3820; CHECK-SD-NEXT: extr x8, x2, x3, #613821; CHECK-SD-NEXT: extr x9, x0, x1, #613822; CHECK-SD-NEXT: extr x1, x1, x0, #613823; CHECK-SD-NEXT: extr x3, x3, x2, #613824; CHECK-SD-NEXT: mov x0, x93825; CHECK-SD-NEXT: mov x2, x83826; CHECK-SD-NEXT: ret3827;3828; CHECK-GI-LABEL: rotl_v2i128_c:3829; CHECK-GI: // %bb.0: // %entry3830; CHECK-GI-NEXT: extr x8, x0, x1, #613831; CHECK-GI-NEXT: extr x9, x3, x2, #613832; CHECK-GI-NEXT: extr x1, x1, x0, #613833; CHECK-GI-NEXT: extr x2, x2, x3, #613834; CHECK-GI-NEXT: mov x0, x83835; CHECK-GI-NEXT: mov x3, x93836; CHECK-GI-NEXT: ret3837entry:3838 %d = call <2 x i128> @llvm.fshl(<2 x i128> %a, <2 x i128> %a, <2 x i128> <i128 3, i128 3>)3839 ret <2 x i128> %d3840}3841 3842define <2 x i128> @rotr_v2i128_c(<2 x i128> %a) {3843; CHECK-SD-LABEL: rotr_v2i128_c:3844; CHECK-SD: // %bb.0: // %entry3845; CHECK-SD-NEXT: extr x8, x3, x2, #33846; CHECK-SD-NEXT: extr x9, x1, x0, #33847; CHECK-SD-NEXT: extr x1, x0, x1, #33848; CHECK-SD-NEXT: extr x3, x2, x3, #33849; CHECK-SD-NEXT: mov x0, x93850; CHECK-SD-NEXT: mov x2, x83851; CHECK-SD-NEXT: ret3852;3853; CHECK-GI-LABEL: rotr_v2i128_c:3854; CHECK-GI: // %bb.0: // %entry3855; CHECK-GI-NEXT: extr x8, x1, x0, #33856; CHECK-GI-NEXT: extr x9, x3, x2, #33857; CHECK-GI-NEXT: extr x1, x0, x1, #33858; CHECK-GI-NEXT: extr x3, x2, x3, #33859; CHECK-GI-NEXT: mov x0, x83860; CHECK-GI-NEXT: mov x2, x93861; CHECK-GI-NEXT: ret3862entry:3863 %d = call <2 x i128> @llvm.fshr(<2 x i128> %a, <2 x i128> %a, <2 x i128> <i128 3, i128 3>)3864 ret <2 x i128> %d3865}3866 3867define <8 x i8> @fshl_v8i8_c(<8 x i8> %a, <8 x i8> %b) {3868; CHECK-LABEL: fshl_v8i8_c:3869; CHECK: // %bb.0: // %entry3870; CHECK-NEXT: shl v0.8b, v0.8b, #33871; CHECK-NEXT: usra v0.8b, v1.8b, #53872; CHECK-NEXT: ret3873entry:3874 %d = call <8 x i8> @llvm.fshl(<8 x i8> %a, <8 x i8> %b, <8 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)3875 ret <8 x i8> %d3876}3877 3878define <8 x i8> @fshr_v8i8_c(<8 x i8> %a, <8 x i8> %b) {3879; CHECK-LABEL: fshr_v8i8_c:3880; CHECK: // %bb.0: // %entry3881; CHECK-NEXT: shl v0.8b, v0.8b, #53882; CHECK-NEXT: usra v0.8b, v1.8b, #33883; CHECK-NEXT: ret3884entry:3885 %d = call <8 x i8> @llvm.fshr(<8 x i8> %a, <8 x i8> %b, <8 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)3886 ret <8 x i8> %d3887}3888 3889define <16 x i8> @fshl_v16i8_c(<16 x i8> %a, <16 x i8> %b) {3890; CHECK-LABEL: fshl_v16i8_c:3891; CHECK: // %bb.0: // %entry3892; CHECK-NEXT: shl v0.16b, v0.16b, #33893; CHECK-NEXT: usra v0.16b, v1.16b, #53894; CHECK-NEXT: ret3895entry:3896 %d = call <16 x i8> @llvm.fshl(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)3897 ret <16 x i8> %d3898}3899 3900define <16 x i8> @fshr_v16i8_c(<16 x i8> %a, <16 x i8> %b) {3901; CHECK-LABEL: fshr_v16i8_c:3902; CHECK: // %bb.0: // %entry3903; CHECK-NEXT: shl v0.16b, v0.16b, #53904; CHECK-NEXT: usra v0.16b, v1.16b, #33905; CHECK-NEXT: ret3906entry:3907 %d = call <16 x i8> @llvm.fshr(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)3908 ret <16 x i8> %d3909}3910 3911define <4 x i16> @fshl_v4i16_c(<4 x i16> %a, <4 x i16> %b) {3912; CHECK-LABEL: fshl_v4i16_c:3913; CHECK: // %bb.0: // %entry3914; CHECK-NEXT: shl v0.4h, v0.4h, #33915; CHECK-NEXT: usra v0.4h, v1.4h, #133916; CHECK-NEXT: ret3917entry:3918 %d = call <4 x i16> @llvm.fshl(<4 x i16> %a, <4 x i16> %b, <4 x i16> <i16 3, i16 3, i16 3, i16 3>)3919 ret <4 x i16> %d3920}3921 3922define <4 x i16> @fshr_v4i16_c(<4 x i16> %a, <4 x i16> %b) {3923; CHECK-LABEL: fshr_v4i16_c:3924; CHECK: // %bb.0: // %entry3925; CHECK-NEXT: shl v0.4h, v0.4h, #133926; CHECK-NEXT: usra v0.4h, v1.4h, #33927; CHECK-NEXT: ret3928entry:3929 %d = call <4 x i16> @llvm.fshr(<4 x i16> %a, <4 x i16> %b, <4 x i16> <i16 3, i16 3, i16 3, i16 3>)3930 ret <4 x i16> %d3931}3932 3933define <7 x i16> @fshl_v7i16_c(<7 x i16> %a, <7 x i16> %b) {3934; CHECK-SD-LABEL: fshl_v7i16_c:3935; CHECK-SD: // %bb.0: // %entry3936; CHECK-SD-NEXT: adrp x8, .LCPI124_03937; CHECK-SD-NEXT: adrp x9, .LCPI124_13938; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI124_0]3939; CHECK-SD-NEXT: ldr q3, [x9, :lo12:.LCPI124_1]3940; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v2.8h3941; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v3.8h3942; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b3943; CHECK-SD-NEXT: ret3944;3945; CHECK-GI-LABEL: fshl_v7i16_c:3946; CHECK-GI: // %bb.0: // %entry3947; CHECK-GI-NEXT: mov w8, #13 // =0xd3948; CHECK-GI-NEXT: mov w9, #3 // =0x33949; CHECK-GI-NEXT: fmov s2, w83950; CHECK-GI-NEXT: fmov s3, w93951; CHECK-GI-NEXT: mov v2.h[1], w83952; CHECK-GI-NEXT: mov v3.h[1], w93953; CHECK-GI-NEXT: mov v2.h[2], w83954; CHECK-GI-NEXT: mov v3.h[2], w93955; CHECK-GI-NEXT: mov v2.h[3], w83956; CHECK-GI-NEXT: mov v3.h[3], w93957; CHECK-GI-NEXT: mov v2.h[4], w83958; CHECK-GI-NEXT: mov v3.h[4], w93959; CHECK-GI-NEXT: mov v2.h[5], w83960; CHECK-GI-NEXT: mov v3.h[5], w93961; CHECK-GI-NEXT: mov v2.h[6], w83962; CHECK-GI-NEXT: mov v3.h[6], w93963; CHECK-GI-NEXT: neg v2.8h, v2.8h3964; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v3.8h3965; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v2.8h3966; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b3967; CHECK-GI-NEXT: ret3968entry:3969 %d = call <7 x i16> @llvm.fshl(<7 x i16> %a, <7 x i16> %b, <7 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)3970 ret <7 x i16> %d3971}3972 3973define <7 x i16> @fshr_v7i16_c(<7 x i16> %a, <7 x i16> %b) {3974; CHECK-SD-LABEL: fshr_v7i16_c:3975; CHECK-SD: // %bb.0: // %entry3976; CHECK-SD-NEXT: adrp x8, .LCPI125_03977; CHECK-SD-NEXT: adrp x9, .LCPI125_13978; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI125_0]3979; CHECK-SD-NEXT: ldr q3, [x9, :lo12:.LCPI125_1]3980; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v2.8h3981; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v3.8h3982; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b3983; CHECK-SD-NEXT: ret3984;3985; CHECK-GI-LABEL: fshr_v7i16_c:3986; CHECK-GI: // %bb.0: // %entry3987; CHECK-GI-NEXT: mov w8, #3 // =0x33988; CHECK-GI-NEXT: mov w9, #13 // =0xd3989; CHECK-GI-NEXT: fmov s2, w83990; CHECK-GI-NEXT: fmov s3, w93991; CHECK-GI-NEXT: mov v2.h[1], w83992; CHECK-GI-NEXT: mov v3.h[1], w93993; CHECK-GI-NEXT: mov v2.h[2], w83994; CHECK-GI-NEXT: mov v3.h[2], w93995; CHECK-GI-NEXT: mov v2.h[3], w83996; CHECK-GI-NEXT: mov v3.h[3], w93997; CHECK-GI-NEXT: mov v2.h[4], w83998; CHECK-GI-NEXT: mov v3.h[4], w93999; CHECK-GI-NEXT: mov v2.h[5], w84000; CHECK-GI-NEXT: mov v3.h[5], w94001; CHECK-GI-NEXT: mov v2.h[6], w84002; CHECK-GI-NEXT: mov v3.h[6], w94003; CHECK-GI-NEXT: neg v2.8h, v2.8h4004; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v3.8h4005; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v2.8h4006; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b4007; CHECK-GI-NEXT: ret4008entry:4009 %d = call <7 x i16> @llvm.fshr(<7 x i16> %a, <7 x i16> %b, <7 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)4010 ret <7 x i16> %d4011}4012 4013define <8 x i16> @fshl_v8i16_c(<8 x i16> %a, <8 x i16> %b) {4014; CHECK-LABEL: fshl_v8i16_c:4015; CHECK: // %bb.0: // %entry4016; CHECK-NEXT: shl v0.8h, v0.8h, #34017; CHECK-NEXT: usra v0.8h, v1.8h, #134018; CHECK-NEXT: ret4019entry:4020 %d = call <8 x i16> @llvm.fshl(<8 x i16> %a, <8 x i16> %b, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)4021 ret <8 x i16> %d4022}4023 4024define <8 x i16> @fshr_v8i16_c(<8 x i16> %a, <8 x i16> %b) {4025; CHECK-LABEL: fshr_v8i16_c:4026; CHECK: // %bb.0: // %entry4027; CHECK-NEXT: shl v0.8h, v0.8h, #134028; CHECK-NEXT: usra v0.8h, v1.8h, #34029; CHECK-NEXT: ret4030entry:4031 %d = call <8 x i16> @llvm.fshr(<8 x i16> %a, <8 x i16> %b, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)4032 ret <8 x i16> %d4033}4034 4035define <16 x i16> @fshl_v16i16_c(<16 x i16> %a, <16 x i16> %b) {4036; CHECK-SD-LABEL: fshl_v16i16_c:4037; CHECK-SD: // %bb.0: // %entry4038; CHECK-SD-NEXT: shl v1.8h, v1.8h, #34039; CHECK-SD-NEXT: shl v0.8h, v0.8h, #34040; CHECK-SD-NEXT: usra v1.8h, v3.8h, #134041; CHECK-SD-NEXT: usra v0.8h, v2.8h, #134042; CHECK-SD-NEXT: ret4043;4044; CHECK-GI-LABEL: fshl_v16i16_c:4045; CHECK-GI: // %bb.0: // %entry4046; CHECK-GI-NEXT: shl v0.8h, v0.8h, #34047; CHECK-GI-NEXT: shl v1.8h, v1.8h, #34048; CHECK-GI-NEXT: usra v0.8h, v2.8h, #134049; CHECK-GI-NEXT: usra v1.8h, v3.8h, #134050; CHECK-GI-NEXT: ret4051entry:4052 %d = call <16 x i16> @llvm.fshl(<16 x i16> %a, <16 x i16> %b, <16 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)4053 ret <16 x i16> %d4054}4055 4056define <16 x i16> @fshr_v16i16_c(<16 x i16> %a, <16 x i16> %b) {4057; CHECK-SD-LABEL: fshr_v16i16_c:4058; CHECK-SD: // %bb.0: // %entry4059; CHECK-SD-NEXT: shl v1.8h, v1.8h, #134060; CHECK-SD-NEXT: shl v0.8h, v0.8h, #134061; CHECK-SD-NEXT: usra v1.8h, v3.8h, #34062; CHECK-SD-NEXT: usra v0.8h, v2.8h, #34063; CHECK-SD-NEXT: ret4064;4065; CHECK-GI-LABEL: fshr_v16i16_c:4066; CHECK-GI: // %bb.0: // %entry4067; CHECK-GI-NEXT: shl v0.8h, v0.8h, #134068; CHECK-GI-NEXT: shl v1.8h, v1.8h, #134069; CHECK-GI-NEXT: usra v0.8h, v2.8h, #34070; CHECK-GI-NEXT: usra v1.8h, v3.8h, #34071; CHECK-GI-NEXT: ret4072entry:4073 %d = call <16 x i16> @llvm.fshr(<16 x i16> %a, <16 x i16> %b, <16 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)4074 ret <16 x i16> %d4075}4076 4077define <2 x i32> @fshl_v2i32_c(<2 x i32> %a, <2 x i32> %b) {4078; CHECK-LABEL: fshl_v2i32_c:4079; CHECK: // %bb.0: // %entry4080; CHECK-NEXT: shl v0.2s, v0.2s, #34081; CHECK-NEXT: usra v0.2s, v1.2s, #294082; CHECK-NEXT: ret4083entry:4084 %d = call <2 x i32> @llvm.fshl(<2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 3, i32 3>)4085 ret <2 x i32> %d4086}4087 4088define <2 x i32> @fshr_v2i32_c(<2 x i32> %a, <2 x i32> %b) {4089; CHECK-LABEL: fshr_v2i32_c:4090; CHECK: // %bb.0: // %entry4091; CHECK-NEXT: shl v0.2s, v0.2s, #294092; CHECK-NEXT: usra v0.2s, v1.2s, #34093; CHECK-NEXT: ret4094entry:4095 %d = call <2 x i32> @llvm.fshr(<2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 3, i32 3>)4096 ret <2 x i32> %d4097}4098 4099define <4 x i32> @fshl_v4i32_c(<4 x i32> %a, <4 x i32> %b) {4100; CHECK-LABEL: fshl_v4i32_c:4101; CHECK: // %bb.0: // %entry4102; CHECK-NEXT: shl v0.4s, v0.4s, #34103; CHECK-NEXT: usra v0.4s, v1.4s, #294104; CHECK-NEXT: ret4105entry:4106 %d = call <4 x i32> @llvm.fshl(<4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)4107 ret <4 x i32> %d4108}4109 4110define <4 x i32> @fshr_v4i32_c(<4 x i32> %a, <4 x i32> %b) {4111; CHECK-LABEL: fshr_v4i32_c:4112; CHECK: // %bb.0: // %entry4113; CHECK-NEXT: shl v0.4s, v0.4s, #294114; CHECK-NEXT: usra v0.4s, v1.4s, #34115; CHECK-NEXT: ret4116entry:4117 %d = call <4 x i32> @llvm.fshr(<4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)4118 ret <4 x i32> %d4119}4120 4121define <7 x i32> @fshl_v7i32_c(<7 x i32> %a, <7 x i32> %b) {4122; CHECK-SD-LABEL: fshl_v7i32_c:4123; CHECK-SD: // %bb.0: // %entry4124; CHECK-SD-NEXT: fmov s0, w04125; CHECK-SD-NEXT: fmov s1, w44126; CHECK-SD-NEXT: mov x8, sp4127; CHECK-SD-NEXT: fmov s2, w74128; CHECK-SD-NEXT: ldr s3, [sp, #24]4129; CHECK-SD-NEXT: add x9, sp, #324130; CHECK-SD-NEXT: mov v0.s[1], w14131; CHECK-SD-NEXT: mov v1.s[1], w54132; CHECK-SD-NEXT: ld1 { v3.s }[1], [x9]4133; CHECK-SD-NEXT: ld1 { v2.s }[1], [x8]4134; CHECK-SD-NEXT: add x8, sp, #84135; CHECK-SD-NEXT: add x9, sp, #404136; CHECK-SD-NEXT: ld1 { v3.s }[2], [x9]4137; CHECK-SD-NEXT: mov v0.s[2], w24138; CHECK-SD-NEXT: mov v1.s[2], w64139; CHECK-SD-NEXT: ld1 { v2.s }[2], [x8]4140; CHECK-SD-NEXT: add x8, sp, #164141; CHECK-SD-NEXT: ld1 { v2.s }[3], [x8]4142; CHECK-SD-NEXT: mov v0.s[3], w34143; CHECK-SD-NEXT: shl v1.4s, v1.4s, #34144; CHECK-SD-NEXT: usra v1.4s, v3.4s, #294145; CHECK-SD-NEXT: shl v0.4s, v0.4s, #34146; CHECK-SD-NEXT: mov w5, v1.s[1]4147; CHECK-SD-NEXT: mov w6, v1.s[2]4148; CHECK-SD-NEXT: fmov w4, s14149; CHECK-SD-NEXT: usra v0.4s, v2.4s, #294150; CHECK-SD-NEXT: mov w1, v0.s[1]4151; CHECK-SD-NEXT: mov w2, v0.s[2]4152; CHECK-SD-NEXT: mov w3, v0.s[3]4153; CHECK-SD-NEXT: fmov w0, s04154; CHECK-SD-NEXT: ret4155;4156; CHECK-GI-LABEL: fshl_v7i32_c:4157; CHECK-GI: // %bb.0: // %entry4158; CHECK-GI-NEXT: fmov s0, w04159; CHECK-GI-NEXT: mov w8, #29 // =0x1d4160; CHECK-GI-NEXT: fmov s5, w74161; CHECK-GI-NEXT: fmov s3, w84162; CHECK-GI-NEXT: ldr s1, [sp]4163; CHECK-GI-NEXT: mov w9, #3 // =0x34164; CHECK-GI-NEXT: fmov s7, w94165; CHECK-GI-NEXT: ldr s4, [sp, #24]4166; CHECK-GI-NEXT: ldr s6, [sp, #32]4167; CHECK-GI-NEXT: mov v0.s[1], w14168; CHECK-GI-NEXT: mov v5.s[1], v1.s[0]4169; CHECK-GI-NEXT: fmov s1, w44170; CHECK-GI-NEXT: mov v3.s[1], w84171; CHECK-GI-NEXT: mov v4.s[1], v6.s[0]4172; CHECK-GI-NEXT: ldr s2, [sp, #8]4173; CHECK-GI-NEXT: mov v7.s[1], w94174; CHECK-GI-NEXT: ldr s6, [sp, #40]4175; CHECK-GI-NEXT: mov v1.s[1], w54176; CHECK-GI-NEXT: mov v0.s[2], w24177; CHECK-GI-NEXT: mov v5.s[2], v2.s[0]4178; CHECK-GI-NEXT: ldr s2, [sp, #16]4179; CHECK-GI-NEXT: mov v3.s[2], w84180; CHECK-GI-NEXT: mov v4.s[2], v6.s[0]4181; CHECK-GI-NEXT: mov v7.s[2], w94182; CHECK-GI-NEXT: mov v1.s[2], w64183; CHECK-GI-NEXT: mov v0.s[3], w34184; CHECK-GI-NEXT: mov v5.s[3], v2.s[0]4185; CHECK-GI-NEXT: neg v3.4s, v3.4s4186; CHECK-GI-NEXT: ushl v1.4s, v1.4s, v7.4s4187; CHECK-GI-NEXT: shl v0.4s, v0.4s, #34188; CHECK-GI-NEXT: ushl v2.4s, v4.4s, v3.4s4189; CHECK-GI-NEXT: usra v0.4s, v5.4s, #294190; CHECK-GI-NEXT: orr v1.16b, v1.16b, v2.16b4191; CHECK-GI-NEXT: mov s2, v0.s[1]4192; CHECK-GI-NEXT: mov s3, v0.s[2]4193; CHECK-GI-NEXT: mov s4, v0.s[3]4194; CHECK-GI-NEXT: mov s5, v1.s[1]4195; CHECK-GI-NEXT: mov s6, v1.s[2]4196; CHECK-GI-NEXT: fmov w0, s04197; CHECK-GI-NEXT: fmov w4, s14198; CHECK-GI-NEXT: fmov w1, s24199; CHECK-GI-NEXT: fmov w2, s34200; CHECK-GI-NEXT: fmov w3, s44201; CHECK-GI-NEXT: fmov w5, s54202; CHECK-GI-NEXT: fmov w6, s64203; CHECK-GI-NEXT: ret4204entry:4205 %d = call <7 x i32> @llvm.fshl(<7 x i32> %a, <7 x i32> %b, <7 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>)4206 ret <7 x i32> %d4207}4208 4209define <7 x i32> @fshr_v7i32_c(<7 x i32> %a, <7 x i32> %b) {4210; CHECK-SD-LABEL: fshr_v7i32_c:4211; CHECK-SD: // %bb.0: // %entry4212; CHECK-SD-NEXT: fmov s0, w04213; CHECK-SD-NEXT: fmov s1, w44214; CHECK-SD-NEXT: mov x8, sp4215; CHECK-SD-NEXT: fmov s2, w74216; CHECK-SD-NEXT: ldr s3, [sp, #24]4217; CHECK-SD-NEXT: add x9, sp, #324218; CHECK-SD-NEXT: mov v0.s[1], w14219; CHECK-SD-NEXT: mov v1.s[1], w54220; CHECK-SD-NEXT: ld1 { v3.s }[1], [x9]4221; CHECK-SD-NEXT: ld1 { v2.s }[1], [x8]4222; CHECK-SD-NEXT: add x8, sp, #84223; CHECK-SD-NEXT: add x9, sp, #404224; CHECK-SD-NEXT: ld1 { v3.s }[2], [x9]4225; CHECK-SD-NEXT: mov v0.s[2], w24226; CHECK-SD-NEXT: mov v1.s[2], w64227; CHECK-SD-NEXT: ld1 { v2.s }[2], [x8]4228; CHECK-SD-NEXT: add x8, sp, #164229; CHECK-SD-NEXT: ld1 { v2.s }[3], [x8]4230; CHECK-SD-NEXT: mov v0.s[3], w34231; CHECK-SD-NEXT: shl v1.4s, v1.4s, #294232; CHECK-SD-NEXT: usra v1.4s, v3.4s, #34233; CHECK-SD-NEXT: shl v0.4s, v0.4s, #294234; CHECK-SD-NEXT: mov w5, v1.s[1]4235; CHECK-SD-NEXT: mov w6, v1.s[2]4236; CHECK-SD-NEXT: fmov w4, s14237; CHECK-SD-NEXT: usra v0.4s, v2.4s, #34238; CHECK-SD-NEXT: mov w1, v0.s[1]4239; CHECK-SD-NEXT: mov w2, v0.s[2]4240; CHECK-SD-NEXT: mov w3, v0.s[3]4241; CHECK-SD-NEXT: fmov w0, s04242; CHECK-SD-NEXT: ret4243;4244; CHECK-GI-LABEL: fshr_v7i32_c:4245; CHECK-GI: // %bb.0: // %entry4246; CHECK-GI-NEXT: fmov s0, w04247; CHECK-GI-NEXT: mov w8, #3 // =0x34248; CHECK-GI-NEXT: fmov s5, w74249; CHECK-GI-NEXT: fmov s3, w84250; CHECK-GI-NEXT: ldr s1, [sp]4251; CHECK-GI-NEXT: mov w9, #29 // =0x1d4252; CHECK-GI-NEXT: fmov s7, w94253; CHECK-GI-NEXT: ldr s4, [sp, #24]4254; CHECK-GI-NEXT: ldr s6, [sp, #32]4255; CHECK-GI-NEXT: mov v0.s[1], w14256; CHECK-GI-NEXT: mov v5.s[1], v1.s[0]4257; CHECK-GI-NEXT: fmov s1, w44258; CHECK-GI-NEXT: mov v3.s[1], w84259; CHECK-GI-NEXT: mov v4.s[1], v6.s[0]4260; CHECK-GI-NEXT: ldr s2, [sp, #8]4261; CHECK-GI-NEXT: mov v7.s[1], w94262; CHECK-GI-NEXT: ldr s6, [sp, #40]4263; CHECK-GI-NEXT: mov v1.s[1], w54264; CHECK-GI-NEXT: mov v0.s[2], w24265; CHECK-GI-NEXT: mov v5.s[2], v2.s[0]4266; CHECK-GI-NEXT: ldr s2, [sp, #16]4267; CHECK-GI-NEXT: mov v3.s[2], w84268; CHECK-GI-NEXT: mov v4.s[2], v6.s[0]4269; CHECK-GI-NEXT: mov v7.s[2], w94270; CHECK-GI-NEXT: mov v1.s[2], w64271; CHECK-GI-NEXT: mov v0.s[3], w34272; CHECK-GI-NEXT: mov v5.s[3], v2.s[0]4273; CHECK-GI-NEXT: neg v3.4s, v3.4s4274; CHECK-GI-NEXT: ushl v1.4s, v1.4s, v7.4s4275; CHECK-GI-NEXT: shl v0.4s, v0.4s, #294276; CHECK-GI-NEXT: ushl v2.4s, v4.4s, v3.4s4277; CHECK-GI-NEXT: usra v0.4s, v5.4s, #34278; CHECK-GI-NEXT: orr v1.16b, v1.16b, v2.16b4279; CHECK-GI-NEXT: mov s2, v0.s[1]4280; CHECK-GI-NEXT: mov s3, v0.s[2]4281; CHECK-GI-NEXT: mov s4, v0.s[3]4282; CHECK-GI-NEXT: mov s5, v1.s[1]4283; CHECK-GI-NEXT: mov s6, v1.s[2]4284; CHECK-GI-NEXT: fmov w0, s04285; CHECK-GI-NEXT: fmov w4, s14286; CHECK-GI-NEXT: fmov w1, s24287; CHECK-GI-NEXT: fmov w2, s34288; CHECK-GI-NEXT: fmov w3, s44289; CHECK-GI-NEXT: fmov w5, s54290; CHECK-GI-NEXT: fmov w6, s64291; CHECK-GI-NEXT: ret4292entry:4293 %d = call <7 x i32> @llvm.fshr(<7 x i32> %a, <7 x i32> %b, <7 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>)4294 ret <7 x i32> %d4295}4296 4297define <8 x i32> @fshl_v8i32_c(<8 x i32> %a, <8 x i32> %b) {4298; CHECK-SD-LABEL: fshl_v8i32_c:4299; CHECK-SD: // %bb.0: // %entry4300; CHECK-SD-NEXT: shl v1.4s, v1.4s, #34301; CHECK-SD-NEXT: shl v0.4s, v0.4s, #34302; CHECK-SD-NEXT: usra v1.4s, v3.4s, #294303; CHECK-SD-NEXT: usra v0.4s, v2.4s, #294304; CHECK-SD-NEXT: ret4305;4306; CHECK-GI-LABEL: fshl_v8i32_c:4307; CHECK-GI: // %bb.0: // %entry4308; CHECK-GI-NEXT: shl v0.4s, v0.4s, #34309; CHECK-GI-NEXT: shl v1.4s, v1.4s, #34310; CHECK-GI-NEXT: usra v0.4s, v2.4s, #294311; CHECK-GI-NEXT: usra v1.4s, v3.4s, #294312; CHECK-GI-NEXT: ret4313entry:4314 %d = call <8 x i32> @llvm.fshl(<8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>)4315 ret <8 x i32> %d4316}4317 4318define <8 x i32> @fshr_v8i32_c(<8 x i32> %a, <8 x i32> %b) {4319; CHECK-SD-LABEL: fshr_v8i32_c:4320; CHECK-SD: // %bb.0: // %entry4321; CHECK-SD-NEXT: shl v1.4s, v1.4s, #294322; CHECK-SD-NEXT: shl v0.4s, v0.4s, #294323; CHECK-SD-NEXT: usra v1.4s, v3.4s, #34324; CHECK-SD-NEXT: usra v0.4s, v2.4s, #34325; CHECK-SD-NEXT: ret4326;4327; CHECK-GI-LABEL: fshr_v8i32_c:4328; CHECK-GI: // %bb.0: // %entry4329; CHECK-GI-NEXT: shl v0.4s, v0.4s, #294330; CHECK-GI-NEXT: shl v1.4s, v1.4s, #294331; CHECK-GI-NEXT: usra v0.4s, v2.4s, #34332; CHECK-GI-NEXT: usra v1.4s, v3.4s, #34333; CHECK-GI-NEXT: ret4334entry:4335 %d = call <8 x i32> @llvm.fshr(<8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>)4336 ret <8 x i32> %d4337}4338 4339define <2 x i64> @fshl_v2i64_c(<2 x i64> %a, <2 x i64> %b) {4340; CHECK-LABEL: fshl_v2i64_c:4341; CHECK: // %bb.0: // %entry4342; CHECK-NEXT: shl v0.2d, v0.2d, #34343; CHECK-NEXT: usra v0.2d, v1.2d, #614344; CHECK-NEXT: ret4345entry:4346 %d = call <2 x i64> @llvm.fshl(<2 x i64> %a, <2 x i64> %b, <2 x i64> <i64 3, i64 3>)4347 ret <2 x i64> %d4348}4349 4350define <2 x i64> @fshr_v2i64_c(<2 x i64> %a, <2 x i64> %b) {4351; CHECK-LABEL: fshr_v2i64_c:4352; CHECK: // %bb.0: // %entry4353; CHECK-NEXT: shl v0.2d, v0.2d, #614354; CHECK-NEXT: usra v0.2d, v1.2d, #34355; CHECK-NEXT: ret4356entry:4357 %d = call <2 x i64> @llvm.fshr(<2 x i64> %a, <2 x i64> %b, <2 x i64> <i64 3, i64 3>)4358 ret <2 x i64> %d4359}4360 4361define <4 x i64> @fshl_v4i64_c(<4 x i64> %a, <4 x i64> %b) {4362; CHECK-SD-LABEL: fshl_v4i64_c:4363; CHECK-SD: // %bb.0: // %entry4364; CHECK-SD-NEXT: shl v1.2d, v1.2d, #34365; CHECK-SD-NEXT: shl v0.2d, v0.2d, #34366; CHECK-SD-NEXT: usra v1.2d, v3.2d, #614367; CHECK-SD-NEXT: usra v0.2d, v2.2d, #614368; CHECK-SD-NEXT: ret4369;4370; CHECK-GI-LABEL: fshl_v4i64_c:4371; CHECK-GI: // %bb.0: // %entry4372; CHECK-GI-NEXT: shl v0.2d, v0.2d, #34373; CHECK-GI-NEXT: shl v1.2d, v1.2d, #34374; CHECK-GI-NEXT: usra v0.2d, v2.2d, #614375; CHECK-GI-NEXT: usra v1.2d, v3.2d, #614376; CHECK-GI-NEXT: ret4377entry:4378 %d = call <4 x i64> @llvm.fshl(<4 x i64> %a, <4 x i64> %b, <4 x i64> <i64 3, i64 3, i64 3, i64 3>)4379 ret <4 x i64> %d4380}4381 4382define <4 x i64> @fshr_v4i64_c(<4 x i64> %a, <4 x i64> %b) {4383; CHECK-SD-LABEL: fshr_v4i64_c:4384; CHECK-SD: // %bb.0: // %entry4385; CHECK-SD-NEXT: shl v1.2d, v1.2d, #614386; CHECK-SD-NEXT: shl v0.2d, v0.2d, #614387; CHECK-SD-NEXT: usra v1.2d, v3.2d, #34388; CHECK-SD-NEXT: usra v0.2d, v2.2d, #34389; CHECK-SD-NEXT: ret4390;4391; CHECK-GI-LABEL: fshr_v4i64_c:4392; CHECK-GI: // %bb.0: // %entry4393; CHECK-GI-NEXT: shl v0.2d, v0.2d, #614394; CHECK-GI-NEXT: shl v1.2d, v1.2d, #614395; CHECK-GI-NEXT: usra v0.2d, v2.2d, #34396; CHECK-GI-NEXT: usra v1.2d, v3.2d, #34397; CHECK-GI-NEXT: ret4398entry:4399 %d = call <4 x i64> @llvm.fshr(<4 x i64> %a, <4 x i64> %b, <4 x i64> <i64 3, i64 3, i64 3, i64 3>)4400 ret <4 x i64> %d4401}4402 4403define <2 x i128> @fshl_v2i128_c(<2 x i128> %a, <2 x i128> %b) {4404; CHECK-SD-LABEL: fshl_v2i128_c:4405; CHECK-SD: // %bb.0: // %entry4406; CHECK-SD-NEXT: extr x8, x0, x5, #614407; CHECK-SD-NEXT: extr x9, x2, x7, #614408; CHECK-SD-NEXT: extr x1, x1, x0, #614409; CHECK-SD-NEXT: extr x3, x3, x2, #614410; CHECK-SD-NEXT: mov x0, x84411; CHECK-SD-NEXT: mov x2, x94412; CHECK-SD-NEXT: ret4413;4414; CHECK-GI-LABEL: fshl_v2i128_c:4415; CHECK-GI: // %bb.0: // %entry4416; CHECK-GI-NEXT: extr x8, x0, x5, #614417; CHECK-GI-NEXT: extr x1, x1, x0, #614418; CHECK-GI-NEXT: extr x3, x3, x2, #614419; CHECK-GI-NEXT: extr x2, x2, x7, #614420; CHECK-GI-NEXT: mov x0, x84421; CHECK-GI-NEXT: ret4422entry:4423 %d = call <2 x i128> @llvm.fshl(<2 x i128> %a, <2 x i128> %b, <2 x i128> <i128 3, i128 3>)4424 ret <2 x i128> %d4425}4426 4427define <2 x i128> @fshr_v2i128_c(<2 x i128> %a, <2 x i128> %b) {4428; CHECK-LABEL: fshr_v2i128_c:4429; CHECK: // %bb.0: // %entry4430; CHECK-NEXT: extr x8, x5, x4, #34431; CHECK-NEXT: extr x9, x7, x6, #34432; CHECK-NEXT: extr x1, x0, x5, #34433; CHECK-NEXT: extr x3, x2, x7, #34434; CHECK-NEXT: mov x0, x84435; CHECK-NEXT: mov x2, x94436; CHECK-NEXT: ret4437entry:4438 %d = call <2 x i128> @llvm.fshr(<2 x i128> %a, <2 x i128> %b, <2 x i128> <i128 3, i128 3>)4439 ret <2 x i128> %d4440}4441 4442 4443 4444define <2 x i64> @fshl_to_rev2i64(<2 x i64> %r) {4445; CHECK-SD-LABEL: fshl_to_rev2i64:4446; CHECK-SD: // %bb.0:4447; CHECK-SD-NEXT: rev64 v0.4s, v0.4s4448; CHECK-SD-NEXT: ret4449;4450; CHECK-GI-LABEL: fshl_to_rev2i64:4451; CHECK-GI: // %bb.0:4452; CHECK-GI-NEXT: shl v1.2d, v0.2d, #324453; CHECK-GI-NEXT: ushr v0.2d, v0.2d, #324454; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b4455; CHECK-GI-NEXT: ret4456 %or = tail call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %r, <2 x i64> %r, <2 x i64> splat (i64 32))4457 ret <2 x i64> %or4458}4459 4460define <4 x i32> @fshl_to_rev4i32(<4 x i32> %r) {4461; CHECK-SD-LABEL: fshl_to_rev4i32:4462; CHECK-SD: // %bb.0:4463; CHECK-SD-NEXT: rev32 v0.8h, v0.8h4464; CHECK-SD-NEXT: ret4465;4466; CHECK-GI-LABEL: fshl_to_rev4i32:4467; CHECK-GI: // %bb.0:4468; CHECK-GI-NEXT: shl v1.4s, v0.4s, #164469; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #164470; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b4471; CHECK-GI-NEXT: ret4472 %or = tail call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %r, <4 x i32> %r, <4 x i32> splat (i32 16))4473 ret <4 x i32> %or4474}4475 4476define <2 x i32> @fshl_to_rev2i32(<2 x i32> %r) {4477; CHECK-SD-LABEL: fshl_to_rev2i32:4478; CHECK-SD: // %bb.0:4479; CHECK-SD-NEXT: rev32 v0.4h, v0.4h4480; CHECK-SD-NEXT: ret4481;4482; CHECK-GI-LABEL: fshl_to_rev2i32:4483; CHECK-GI: // %bb.0:4484; CHECK-GI-NEXT: shl v1.2s, v0.2s, #164485; CHECK-GI-NEXT: ushr v0.2s, v0.2s, #164486; CHECK-GI-NEXT: orr v0.8b, v1.8b, v0.8b4487; CHECK-GI-NEXT: ret4488 %or = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %r, <2 x i32> %r, <2 x i32> splat (i32 16))4489 ret <2 x i32> %or4490}4491