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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5declare i8 @llvm.fshl.i8(i8, i8, i8)6declare i16 @llvm.fshl.i16(i16, i16, i16)7declare i32 @llvm.fshl.i32(i32, i32, i32)8declare i64 @llvm.fshl.i64(i64, i64, i64)9declare i128 @llvm.fshl.i128(i128, i128, i128)10declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)11 12declare i8 @llvm.fshr.i8(i8, i8, i8)13declare i16 @llvm.fshr.i16(i16, i16, i16)14declare i32 @llvm.fshr.i32(i32, i32, i32)15declare i64 @llvm.fshr.i64(i64, i64, i64)16declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)17 18; General case - all operands can be variables.19 20define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {21; CHECK-SD-LABEL: fshl_i32:22; CHECK-SD: // %bb.0:23; CHECK-SD-NEXT: lsr w8, w1, #124; CHECK-SD-NEXT: mvn w9, w225; CHECK-SD-NEXT: lsl w10, w0, w226; CHECK-SD-NEXT: lsr w8, w8, w927; CHECK-SD-NEXT: orr w0, w10, w828; CHECK-SD-NEXT: ret29;30; CHECK-GI-LABEL: fshl_i32:31; CHECK-GI: // %bb.0:32; CHECK-GI-NEXT: mov w8, #31 // =0x1f33; CHECK-GI-NEXT: lsr w9, w1, #134; CHECK-GI-NEXT: and w10, w2, #0x1f35; CHECK-GI-NEXT: bic w8, w8, w236; CHECK-GI-NEXT: lsl w10, w0, w1037; CHECK-GI-NEXT: lsr w8, w9, w838; CHECK-GI-NEXT: orr w0, w10, w839; CHECK-GI-NEXT: ret40 %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)41 ret i32 %f42}43 44define i64 @fshl_i64(i64 %x, i64 %y, i64 %z) {45; CHECK-SD-LABEL: fshl_i64:46; CHECK-SD: // %bb.0:47; CHECK-SD-NEXT: lsr x8, x1, #148; CHECK-SD-NEXT: mvn w9, w249; CHECK-SD-NEXT: lsl x10, x0, x250; CHECK-SD-NEXT: lsr x8, x8, x951; CHECK-SD-NEXT: orr x0, x10, x852; CHECK-SD-NEXT: ret53;54; CHECK-GI-LABEL: fshl_i64:55; CHECK-GI: // %bb.0:56; CHECK-GI-NEXT: mov w8, #63 // =0x3f57; CHECK-GI-NEXT: lsr x9, x1, #158; CHECK-GI-NEXT: and x10, x2, #0x3f59; CHECK-GI-NEXT: bic x8, x8, x260; CHECK-GI-NEXT: lsl x10, x0, x1061; CHECK-GI-NEXT: lsr x8, x9, x862; CHECK-GI-NEXT: orr x0, x10, x863; CHECK-GI-NEXT: ret64 %f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 %z)65 ret i64 %f66}67 68define i128 @fshl_i128(i128 %x, i128 %y, i128 %z) nounwind {69; CHECK-SD-LABEL: fshl_i128:70; CHECK-SD: // %bb.0:71; CHECK-SD-NEXT: tst x4, #0x4072; CHECK-SD-NEXT: mvn w11, w473; CHECK-SD-NEXT: csel x8, x3, x0, ne74; CHECK-SD-NEXT: csel x9, x2, x3, ne75; CHECK-SD-NEXT: csel x12, x0, x1, ne76; CHECK-SD-NEXT: lsr x9, x9, #177; CHECK-SD-NEXT: lsr x10, x8, #178; CHECK-SD-NEXT: lsl x8, x8, x479; CHECK-SD-NEXT: lsl x12, x12, x480; CHECK-SD-NEXT: lsr x9, x9, x1181; CHECK-SD-NEXT: lsr x10, x10, x1182; CHECK-SD-NEXT: orr x0, x8, x983; CHECK-SD-NEXT: orr x1, x12, x1084; CHECK-SD-NEXT: ret85;86; CHECK-GI-LABEL: fshl_i128:87; CHECK-GI: // %bb.0:88; CHECK-GI-NEXT: mov w8, #64 // =0x4089; CHECK-GI-NEXT: and x9, x4, #0x7f90; CHECK-GI-NEXT: mov w10, #127 // =0x7f91; CHECK-GI-NEXT: sub x12, x8, x992; CHECK-GI-NEXT: lsl x13, x1, x993; CHECK-GI-NEXT: bic x10, x10, x494; CHECK-GI-NEXT: lsr x12, x0, x1295; CHECK-GI-NEXT: sub x14, x9, #6496; CHECK-GI-NEXT: lsl x15, x0, x997; CHECK-GI-NEXT: extr x16, x3, x2, #198; CHECK-GI-NEXT: cmp x9, #6499; CHECK-GI-NEXT: sub x8, x8, x10100; CHECK-GI-NEXT: orr x9, x12, x13101; CHECK-GI-NEXT: lsr x12, x3, #1102; CHECK-GI-NEXT: lsl x13, x0, x14103; CHECK-GI-NEXT: csel x14, x15, xzr, lo104; CHECK-GI-NEXT: sub x15, x10, #64105; CHECK-GI-NEXT: lsr x17, x16, x10106; CHECK-GI-NEXT: lsl x8, x12, x8107; CHECK-GI-NEXT: csel x9, x9, x13, lo108; CHECK-GI-NEXT: tst x4, #0x7f109; CHECK-GI-NEXT: lsr x13, x12, x15110; CHECK-GI-NEXT: mvn x11, x4111; CHECK-GI-NEXT: csel x9, x1, x9, eq112; CHECK-GI-NEXT: orr x8, x17, x8113; CHECK-GI-NEXT: cmp x10, #64114; CHECK-GI-NEXT: lsr x12, x12, x10115; CHECK-GI-NEXT: csel x8, x8, x13, lo116; CHECK-GI-NEXT: tst x11, #0x7f117; CHECK-GI-NEXT: csel x8, x16, x8, eq118; CHECK-GI-NEXT: cmp x10, #64119; CHECK-GI-NEXT: csel x10, x12, xzr, lo120; CHECK-GI-NEXT: orr x0, x14, x8121; CHECK-GI-NEXT: orr x1, x9, x10122; CHECK-GI-NEXT: ret123 %f = call i128 @llvm.fshl.i128(i128 %x, i128 %y, i128 %z)124 ret i128 %f125}126 127; Verify that weird types are minimally supported.128declare i37 @llvm.fshl.i37(i37, i37, i37)129define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {130; CHECK-SD-LABEL: fshl_i37:131; CHECK-SD: // %bb.0:132; CHECK-SD-NEXT: mov x9, #46053 // =0xb3e5133; CHECK-SD-NEXT: and x8, x2, #0x1fffffffff134; CHECK-SD-NEXT: movk x9, #12398, lsl #16135; CHECK-SD-NEXT: movk x9, #15941, lsl #32136; CHECK-SD-NEXT: movk x9, #1771, lsl #48137; CHECK-SD-NEXT: umulh x8, x8, x9138; CHECK-SD-NEXT: mov w9, #37 // =0x25139; CHECK-SD-NEXT: msub w8, w8, w9, w2140; CHECK-SD-NEXT: ubfiz x9, x1, #26, #37141; CHECK-SD-NEXT: mvn w10, w8142; CHECK-SD-NEXT: lsl x8, x0, x8143; CHECK-SD-NEXT: lsr x9, x9, x10144; CHECK-SD-NEXT: orr x0, x8, x9145; CHECK-SD-NEXT: ret146;147; CHECK-GI-LABEL: fshl_i37:148; CHECK-GI: // %bb.0:149; CHECK-GI-NEXT: mov w8, #37 // =0x25150; CHECK-GI-NEXT: and x9, x2, #0x1fffffffff151; CHECK-GI-NEXT: udiv x10, x9, x8152; CHECK-GI-NEXT: msub x8, x10, x8, x9153; CHECK-GI-NEXT: mov w9, #36 // =0x24154; CHECK-GI-NEXT: ubfx x10, x1, #1, #36155; CHECK-GI-NEXT: sub x9, x9, x8156; CHECK-GI-NEXT: and x8, x8, #0x1fffffffff157; CHECK-GI-NEXT: and x9, x9, #0x1fffffffff158; CHECK-GI-NEXT: lsl x8, x0, x8159; CHECK-GI-NEXT: lsr x9, x10, x9160; CHECK-GI-NEXT: orr x0, x8, x9161; CHECK-GI-NEXT: ret162 %f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)163 ret i37 %f164}165 166; extract(concat(0b1110000, 0b1111111) << 2) = 0b1000011167 168declare i7 @llvm.fshl.i7(i7, i7, i7)169define i7 @fshl_i7_const_fold() {170; CHECK-LABEL: fshl_i7_const_fold:171; CHECK: // %bb.0:172; CHECK-NEXT: mov w0, #67 // =0x43173; CHECK-NEXT: ret174 %f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2)175 ret i7 %f176}177 178define i8 @fshl_i8_const_fold_overshift_1() {179; CHECK-SD-LABEL: fshl_i8_const_fold_overshift_1:180; CHECK-SD: // %bb.0:181; CHECK-SD-NEXT: mov w0, #128 // =0x80182; CHECK-SD-NEXT: ret183;184; CHECK-GI-LABEL: fshl_i8_const_fold_overshift_1:185; CHECK-GI: // %bb.0:186; CHECK-GI-NEXT: mov w0, #-128 // =0xffffff80187; CHECK-GI-NEXT: ret188 %f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 15)189 ret i8 %f190}191 192define i8 @fshl_i8_const_fold_overshift_2() {193; CHECK-LABEL: fshl_i8_const_fold_overshift_2:194; CHECK: // %bb.0:195; CHECK-NEXT: mov w0, #120 // =0x78196; CHECK-NEXT: ret197 %f = call i8 @llvm.fshl.i8(i8 15, i8 15, i8 11)198 ret i8 %f199}200 201define i8 @fshl_i8_const_fold_overshift_3() {202; CHECK-LABEL: fshl_i8_const_fold_overshift_3:203; CHECK: // %bb.0:204; CHECK-NEXT: mov w0, wzr205; CHECK-NEXT: ret206 %f = call i8 @llvm.fshl.i8(i8 0, i8 225, i8 8)207 ret i8 %f208}209 210; With constant shift amount, this is 'extr'.211 212define i32 @fshl_i32_const_shift(i32 %x, i32 %y) {213; CHECK-LABEL: fshl_i32_const_shift:214; CHECK: // %bb.0:215; CHECK-NEXT: extr w0, w0, w1, #23216; CHECK-NEXT: ret217 %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 9)218 ret i32 %f219}220 221; Check modulo math on shift amount.222 223define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) {224; CHECK-LABEL: fshl_i32_const_overshift:225; CHECK: // %bb.0:226; CHECK-NEXT: extr w0, w0, w1, #23227; CHECK-NEXT: ret228 %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 41)229 ret i32 %f230}231 232; 64-bit should also work.233 234define i64 @fshl_i64_const_overshift(i64 %x, i64 %y) {235; CHECK-LABEL: fshl_i64_const_overshift:236; CHECK: // %bb.0:237; CHECK-NEXT: extr x0, x0, x1, #23238; CHECK-NEXT: ret239 %f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 105)240 ret i64 %f241}242 243; This should work without any node-specific logic.244 245define i8 @fshl_i8_const_fold() {246; CHECK-SD-LABEL: fshl_i8_const_fold:247; CHECK-SD: // %bb.0:248; CHECK-SD-NEXT: mov w0, #128 // =0x80249; CHECK-SD-NEXT: ret250;251; CHECK-GI-LABEL: fshl_i8_const_fold:252; CHECK-GI: // %bb.0:253; CHECK-GI-NEXT: mov w0, #-128 // =0xffffff80254; CHECK-GI-NEXT: ret255 %f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 7)256 ret i8 %f257}258 259; Repeat everything for funnel shift right.260 261; General case - all operands can be variables.262 263define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {264; CHECK-SD-LABEL: fshr_i32:265; CHECK-SD: // %bb.0:266; CHECK-SD-NEXT: lsl w8, w0, #1267; CHECK-SD-NEXT: mvn w9, w2268; CHECK-SD-NEXT: lsr w10, w1, w2269; CHECK-SD-NEXT: lsl w8, w8, w9270; CHECK-SD-NEXT: orr w0, w8, w10271; CHECK-SD-NEXT: ret272;273; CHECK-GI-LABEL: fshr_i32:274; CHECK-GI: // %bb.0:275; CHECK-GI-NEXT: mov w8, #31 // =0x1f276; CHECK-GI-NEXT: lsl w9, w0, #1277; CHECK-GI-NEXT: and w10, w2, #0x1f278; CHECK-GI-NEXT: bic w8, w8, w2279; CHECK-GI-NEXT: lsl w8, w9, w8280; CHECK-GI-NEXT: lsr w9, w1, w10281; CHECK-GI-NEXT: orr w0, w8, w9282; CHECK-GI-NEXT: ret283 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)284 ret i32 %f285}286 287define i64 @fshr_i64(i64 %x, i64 %y, i64 %z) {288; CHECK-SD-LABEL: fshr_i64:289; CHECK-SD: // %bb.0:290; CHECK-SD-NEXT: lsl x8, x0, #1291; CHECK-SD-NEXT: mvn w9, w2292; CHECK-SD-NEXT: lsr x10, x1, x2293; CHECK-SD-NEXT: lsl x8, x8, x9294; CHECK-SD-NEXT: orr x0, x8, x10295; CHECK-SD-NEXT: ret296;297; CHECK-GI-LABEL: fshr_i64:298; CHECK-GI: // %bb.0:299; CHECK-GI-NEXT: mov w8, #63 // =0x3f300; CHECK-GI-NEXT: lsl x9, x0, #1301; CHECK-GI-NEXT: and x10, x2, #0x3f302; CHECK-GI-NEXT: bic x8, x8, x2303; CHECK-GI-NEXT: lsl x8, x9, x8304; CHECK-GI-NEXT: lsr x9, x1, x10305; CHECK-GI-NEXT: orr x0, x8, x9306; CHECK-GI-NEXT: ret307 %f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 %z)308 ret i64 %f309}310 311; Verify that weird types are minimally supported.312declare i37 @llvm.fshr.i37(i37, i37, i37)313define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {314; CHECK-SD-LABEL: fshr_i37:315; CHECK-SD: // %bb.0:316; CHECK-SD-NEXT: mov x9, #46053 // =0xb3e5317; CHECK-SD-NEXT: and x8, x2, #0x1fffffffff318; CHECK-SD-NEXT: lsl x10, x0, #1319; CHECK-SD-NEXT: movk x9, #12398, lsl #16320; CHECK-SD-NEXT: movk x9, #15941, lsl #32321; CHECK-SD-NEXT: movk x9, #1771, lsl #48322; CHECK-SD-NEXT: umulh x8, x8, x9323; CHECK-SD-NEXT: mov w9, #37 // =0x25324; CHECK-SD-NEXT: msub w8, w8, w9, w2325; CHECK-SD-NEXT: lsl x9, x1, #27326; CHECK-SD-NEXT: add w8, w8, #27327; CHECK-SD-NEXT: mvn w11, w8328; CHECK-SD-NEXT: lsr x8, x9, x8329; CHECK-SD-NEXT: lsl x9, x10, x11330; CHECK-SD-NEXT: orr x0, x9, x8331; CHECK-SD-NEXT: ret332;333; CHECK-GI-LABEL: fshr_i37:334; CHECK-GI: // %bb.0:335; CHECK-GI-NEXT: mov w8, #37 // =0x25336; CHECK-GI-NEXT: and x9, x2, #0x1fffffffff337; CHECK-GI-NEXT: and x11, x1, #0x1fffffffff338; CHECK-GI-NEXT: udiv x10, x9, x8339; CHECK-GI-NEXT: msub x8, x10, x8, x9340; CHECK-GI-NEXT: mov w9, #36 // =0x24341; CHECK-GI-NEXT: lsl x10, x0, #1342; CHECK-GI-NEXT: sub x9, x9, x8343; CHECK-GI-NEXT: and x8, x8, #0x1fffffffff344; CHECK-GI-NEXT: and x9, x9, #0x1fffffffff345; CHECK-GI-NEXT: lsr x8, x11, x8346; CHECK-GI-NEXT: lsl x9, x10, x9347; CHECK-GI-NEXT: orr x0, x9, x8348; CHECK-GI-NEXT: ret349 %f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)350 ret i37 %f351}352 353; extract(concat(0b1110000, 0b1111111) >> 2) = 0b0011111354 355declare i7 @llvm.fshr.i7(i7, i7, i7)356define i7 @fshr_i7_const_fold() {357; CHECK-LABEL: fshr_i7_const_fold:358; CHECK: // %bb.0:359; CHECK-NEXT: mov w0, #31 // =0x1f360; CHECK-NEXT: ret361 %f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 2)362 ret i7 %f363}364 365define i8 @fshr_i8_const_fold_overshift_1() {366; CHECK-SD-LABEL: fshr_i8_const_fold_overshift_1:367; CHECK-SD: // %bb.0:368; CHECK-SD-NEXT: mov w0, #254 // =0xfe369; CHECK-SD-NEXT: ret370;371; CHECK-GI-LABEL: fshr_i8_const_fold_overshift_1:372; CHECK-GI: // %bb.0:373; CHECK-GI-NEXT: mov w0, #-2 // =0xfffffffe374; CHECK-GI-NEXT: ret375 %f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 15)376 ret i8 %f377}378 379define i8 @fshr_i8_const_fold_overshift_2() {380; CHECK-SD-LABEL: fshr_i8_const_fold_overshift_2:381; CHECK-SD: // %bb.0:382; CHECK-SD-NEXT: mov w0, #225 // =0xe1383; CHECK-SD-NEXT: ret384;385; CHECK-GI-LABEL: fshr_i8_const_fold_overshift_2:386; CHECK-GI: // %bb.0:387; CHECK-GI-NEXT: mov w0, #481 // =0x1e1388; CHECK-GI-NEXT: ret389 %f = call i8 @llvm.fshr.i8(i8 15, i8 15, i8 11)390 ret i8 %f391}392 393define i8 @fshr_i8_const_fold_overshift_3() {394; CHECK-LABEL: fshr_i8_const_fold_overshift_3:395; CHECK: // %bb.0:396; CHECK-NEXT: mov w0, #255 // =0xff397; CHECK-NEXT: ret398 %f = call i8 @llvm.fshr.i8(i8 0, i8 255, i8 8)399 ret i8 %f400}401 402; With constant shift amount, this is 'extr'.403 404define i32 @fshr_i32_const_shift(i32 %x, i32 %y) {405; CHECK-LABEL: fshr_i32_const_shift:406; CHECK: // %bb.0:407; CHECK-NEXT: extr w0, w0, w1, #9408; CHECK-NEXT: ret409 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 9)410 ret i32 %f411}412 413; Check modulo math on shift amount. 41-32=9.414 415define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) {416; CHECK-LABEL: fshr_i32_const_overshift:417; CHECK: // %bb.0:418; CHECK-NEXT: extr w0, w0, w1, #9419; CHECK-NEXT: ret420 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 41)421 ret i32 %f422}423 424; 64-bit should also work. 105-64 = 41.425 426define i64 @fshr_i64_const_overshift(i64 %x, i64 %y) {427; CHECK-LABEL: fshr_i64_const_overshift:428; CHECK: // %bb.0:429; CHECK-NEXT: extr x0, x0, x1, #41430; CHECK-NEXT: ret431 %f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 105)432 ret i64 %f433}434 435; This should work without any node-specific logic.436 437define i8 @fshr_i8_const_fold() {438; CHECK-SD-LABEL: fshr_i8_const_fold:439; CHECK-SD: // %bb.0:440; CHECK-SD-NEXT: mov w0, #254 // =0xfe441; CHECK-SD-NEXT: ret442;443; CHECK-GI-LABEL: fshr_i8_const_fold:444; CHECK-GI: // %bb.0:445; CHECK-GI-NEXT: mov w0, #-2 // =0xfffffffe446; CHECK-GI-NEXT: ret447 %f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 7)448 ret i8 %f449}450 451define i32 @fshl_i32_shift_by_bitwidth(i32 %x, i32 %y) {452; CHECK-LABEL: fshl_i32_shift_by_bitwidth:453; CHECK: // %bb.0:454; CHECK-NEXT: ret455 %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 32)456 ret i32 %f457}458 459define i32 @fshr_i32_shift_by_bitwidth(i32 %x, i32 %y) {460; CHECK-LABEL: fshr_i32_shift_by_bitwidth:461; CHECK: // %bb.0:462; CHECK-NEXT: mov w0, w1463; CHECK-NEXT: ret464 %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 32)465 ret i32 %f466}467 468define <4 x i32> @fshl_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {469; CHECK-LABEL: fshl_v4i32_shift_by_bitwidth:470; CHECK: // %bb.0:471; CHECK-NEXT: ret472 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)473 ret <4 x i32> %f474}475 476define <4 x i32> @fshr_v4i32_shift_by_bitwidth(<4 x i32> %x, <4 x i32> %y) {477; CHECK-LABEL: fshr_v4i32_shift_by_bitwidth:478; CHECK: // %bb.0:479; CHECK-NEXT: mov v0.16b, v1.16b480; CHECK-NEXT: ret481 %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)482 ret <4 x i32> %f483}484 485define i32 @or_shl_fshl(i32 %x, i32 %y, i32 %s) {486; CHECK-SD-LABEL: or_shl_fshl:487; CHECK-SD: // %bb.0:488; CHECK-SD-NEXT: mov w8, w2489; CHECK-SD-NEXT: lsr w9, w1, #1490; CHECK-SD-NEXT: lsl w10, w1, w2491; CHECK-SD-NEXT: mvn w11, w2492; CHECK-SD-NEXT: lsl w8, w0, w8493; CHECK-SD-NEXT: lsr w9, w9, w11494; CHECK-SD-NEXT: orr w8, w8, w10495; CHECK-SD-NEXT: orr w0, w8, w9496; CHECK-SD-NEXT: ret497;498; CHECK-GI-LABEL: or_shl_fshl:499; CHECK-GI: // %bb.0:500; CHECK-GI-NEXT: mov w8, #31 // =0x1f501; CHECK-GI-NEXT: and w9, w2, #0x1f502; CHECK-GI-NEXT: lsr w10, w1, #1503; CHECK-GI-NEXT: lsl w11, w1, w2504; CHECK-GI-NEXT: bic w8, w8, w2505; CHECK-GI-NEXT: lsl w9, w0, w9506; CHECK-GI-NEXT: lsr w8, w10, w8507; CHECK-GI-NEXT: orr w9, w9, w11508; CHECK-GI-NEXT: orr w0, w9, w8509; CHECK-GI-NEXT: ret510 %shy = shl i32 %y, %s511 %fun = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %s)512 %or = or i32 %fun, %shy513 ret i32 %or514}515 516define i32 @or_shl_rotl(i32 %x, i32 %y, i32 %s) {517; CHECK-LABEL: or_shl_rotl:518; CHECK: // %bb.0:519; CHECK-NEXT: neg w8, w2520; CHECK-NEXT: lsl w9, w0, w2521; CHECK-NEXT: ror w8, w1, w8522; CHECK-NEXT: orr w0, w8, w9523; CHECK-NEXT: ret524 %shx = shl i32 %x, %s525 %rot = call i32 @llvm.fshl.i32(i32 %y, i32 %y, i32 %s)526 %or = or i32 %rot, %shx527 ret i32 %or528}529 530define i32 @or_shl_fshl_commute(i32 %x, i32 %y, i32 %s) {531; CHECK-SD-LABEL: or_shl_fshl_commute:532; CHECK-SD: // %bb.0:533; CHECK-SD-NEXT: mov w8, w2534; CHECK-SD-NEXT: lsr w9, w1, #1535; CHECK-SD-NEXT: lsl w10, w1, w2536; CHECK-SD-NEXT: mvn w11, w2537; CHECK-SD-NEXT: lsl w8, w0, w8538; CHECK-SD-NEXT: lsr w9, w9, w11539; CHECK-SD-NEXT: orr w8, w10, w8540; CHECK-SD-NEXT: orr w0, w8, w9541; CHECK-SD-NEXT: ret542;543; CHECK-GI-LABEL: or_shl_fshl_commute:544; CHECK-GI: // %bb.0:545; CHECK-GI-NEXT: mov w8, #31 // =0x1f546; CHECK-GI-NEXT: and w9, w2, #0x1f547; CHECK-GI-NEXT: lsr w10, w1, #1548; CHECK-GI-NEXT: lsl w11, w1, w2549; CHECK-GI-NEXT: bic w8, w8, w2550; CHECK-GI-NEXT: lsl w9, w0, w9551; CHECK-GI-NEXT: lsr w8, w10, w8552; CHECK-GI-NEXT: orr w9, w11, w9553; CHECK-GI-NEXT: orr w0, w9, w8554; CHECK-GI-NEXT: ret555 %shy = shl i32 %y, %s556 %fun = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %s)557 %or = or i32 %shy, %fun558 ret i32 %or559}560 561define i32 @or_shl_rotl_commute(i32 %x, i32 %y, i32 %s) {562; CHECK-LABEL: or_shl_rotl_commute:563; CHECK: // %bb.0:564; CHECK-NEXT: neg w8, w2565; CHECK-NEXT: lsl w9, w0, w2566; CHECK-NEXT: ror w8, w1, w8567; CHECK-NEXT: orr w0, w9, w8568; CHECK-NEXT: ret569 %shx = shl i32 %x, %s570 %rot = call i32 @llvm.fshl.i32(i32 %y, i32 %y, i32 %s)571 %or = or i32 %shx, %rot572 ret i32 %or573}574 575define i32 @or_lshr_fshr(i32 %x, i32 %y, i32 %s) {576; CHECK-SD-LABEL: or_lshr_fshr:577; CHECK-SD: // %bb.0:578; CHECK-SD-NEXT: mov w8, w2579; CHECK-SD-NEXT: lsl w9, w1, #1580; CHECK-SD-NEXT: lsr w10, w1, w2581; CHECK-SD-NEXT: lsr w8, w0, w8582; CHECK-SD-NEXT: mvn w11, w2583; CHECK-SD-NEXT: lsl w9, w9, w11584; CHECK-SD-NEXT: orr w8, w8, w10585; CHECK-SD-NEXT: orr w0, w9, w8586; CHECK-SD-NEXT: ret587;588; CHECK-GI-LABEL: or_lshr_fshr:589; CHECK-GI: // %bb.0:590; CHECK-GI-NEXT: mov w8, #31 // =0x1f591; CHECK-GI-NEXT: and w9, w2, #0x1f592; CHECK-GI-NEXT: lsl w10, w1, #1593; CHECK-GI-NEXT: lsr w11, w1, w2594; CHECK-GI-NEXT: bic w8, w8, w2595; CHECK-GI-NEXT: lsr w9, w0, w9596; CHECK-GI-NEXT: lsl w8, w10, w8597; CHECK-GI-NEXT: orr w9, w9, w11598; CHECK-GI-NEXT: orr w0, w8, w9599; CHECK-GI-NEXT: ret600 %shy = lshr i32 %y, %s601 %fun = call i32 @llvm.fshr.i32(i32 %y, i32 %x, i32 %s)602 %or = or i32 %fun, %shy603 ret i32 %or604}605 606define i32 @or_lshr_rotr(i32 %x, i32 %y, i32 %s) {607; CHECK-LABEL: or_lshr_rotr:608; CHECK: // %bb.0:609; CHECK-NEXT: lsr w8, w0, w2610; CHECK-NEXT: ror w9, w1, w2611; CHECK-NEXT: orr w0, w9, w8612; CHECK-NEXT: ret613 %shx = lshr i32 %x, %s614 %rot = call i32 @llvm.fshr.i32(i32 %y, i32 %y, i32 %s)615 %or = or i32 %rot, %shx616 ret i32 %or617}618 619define i32 @or_lshr_fshr_commute(i32 %x, i32 %y, i32 %s) {620; CHECK-SD-LABEL: or_lshr_fshr_commute:621; CHECK-SD: // %bb.0:622; CHECK-SD-NEXT: mov w8, w2623; CHECK-SD-NEXT: lsl w9, w1, #1624; CHECK-SD-NEXT: lsr w10, w1, w2625; CHECK-SD-NEXT: lsr w8, w0, w8626; CHECK-SD-NEXT: mvn w11, w2627; CHECK-SD-NEXT: lsl w9, w9, w11628; CHECK-SD-NEXT: orr w8, w10, w8629; CHECK-SD-NEXT: orr w0, w8, w9630; CHECK-SD-NEXT: ret631;632; CHECK-GI-LABEL: or_lshr_fshr_commute:633; CHECK-GI: // %bb.0:634; CHECK-GI-NEXT: mov w8, #31 // =0x1f635; CHECK-GI-NEXT: and w9, w2, #0x1f636; CHECK-GI-NEXT: lsl w10, w1, #1637; CHECK-GI-NEXT: lsr w11, w1, w2638; CHECK-GI-NEXT: bic w8, w8, w2639; CHECK-GI-NEXT: lsr w9, w0, w9640; CHECK-GI-NEXT: lsl w8, w10, w8641; CHECK-GI-NEXT: orr w9, w11, w9642; CHECK-GI-NEXT: orr w0, w9, w8643; CHECK-GI-NEXT: ret644 %shy = lshr i32 %y, %s645 %fun = call i32 @llvm.fshr.i32(i32 %y, i32 %x, i32 %s)646 %or = or i32 %shy, %fun647 ret i32 %or648}649 650define i32 @or_lshr_rotr_commute(i32 %x, i32 %y, i32 %s) {651; CHECK-LABEL: or_lshr_rotr_commute:652; CHECK: // %bb.0:653; CHECK-NEXT: lsr w8, w0, w2654; CHECK-NEXT: ror w9, w1, w2655; CHECK-NEXT: orr w0, w8, w9656; CHECK-NEXT: ret657 %shx = lshr i32 %x, %s658 %rot = call i32 @llvm.fshr.i32(i32 %y, i32 %y, i32 %s)659 %or = or i32 %shx, %rot660 ret i32 %or661}662 663define i32 @or_shl_fshl_simplify(i32 %x, i32 %y, i32 %s) {664; CHECK-SD-LABEL: or_shl_fshl_simplify:665; CHECK-SD: // %bb.0:666; CHECK-SD-NEXT: lsr w8, w0, #1667; CHECK-SD-NEXT: mvn w9, w2668; CHECK-SD-NEXT: lsl w10, w1, w2669; CHECK-SD-NEXT: lsr w8, w8, w9670; CHECK-SD-NEXT: orr w0, w10, w8671; CHECK-SD-NEXT: ret672;673; CHECK-GI-LABEL: or_shl_fshl_simplify:674; CHECK-GI: // %bb.0:675; CHECK-GI-NEXT: mov w8, #31 // =0x1f676; CHECK-GI-NEXT: lsr w9, w0, #1677; CHECK-GI-NEXT: and w10, w2, #0x1f678; CHECK-GI-NEXT: bic w8, w8, w2679; CHECK-GI-NEXT: lsl w10, w1, w10680; CHECK-GI-NEXT: lsr w8, w9, w8681; CHECK-GI-NEXT: orr w0, w10, w8682; CHECK-GI-NEXT: ret683 %shy = shl i32 %y, %s684 %fun = call i32 @llvm.fshl.i32(i32 %y, i32 %x, i32 %s)685 %or = or i32 %fun, %shy686 ret i32 %or687}688 689define i32 @or_lshr_fshr_simplify(i32 %x, i32 %y, i32 %s) {690; CHECK-SD-LABEL: or_lshr_fshr_simplify:691; CHECK-SD: // %bb.0:692; CHECK-SD-NEXT: lsl w8, w0, #1693; CHECK-SD-NEXT: mvn w9, w2694; CHECK-SD-NEXT: lsr w10, w1, w2695; CHECK-SD-NEXT: lsl w8, w8, w9696; CHECK-SD-NEXT: orr w0, w8, w10697; CHECK-SD-NEXT: ret698;699; CHECK-GI-LABEL: or_lshr_fshr_simplify:700; CHECK-GI: // %bb.0:701; CHECK-GI-NEXT: mov w8, #31 // =0x1f702; CHECK-GI-NEXT: lsl w9, w0, #1703; CHECK-GI-NEXT: and w10, w2, #0x1f704; CHECK-GI-NEXT: bic w8, w8, w2705; CHECK-GI-NEXT: lsl w8, w9, w8706; CHECK-GI-NEXT: lsr w9, w1, w10707; CHECK-GI-NEXT: orr w0, w8, w9708; CHECK-GI-NEXT: ret709 %shy = lshr i32 %y, %s710 %fun = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %s)711 %or = or i32 %shy, %fun712 ret i32 %or713}714