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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-unknown-unknown -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; We are looking for the following pattern here:6; (X & (C l>> Y)) ==/!= 07; It may be optimal to hoist the constant:8; ((X << Y) & C) ==/!= 09 10;------------------------------------------------------------------------------;11; A few scalar test12;------------------------------------------------------------------------------;13 14; i8 scalar15 16define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {17; CHECK-SD-LABEL: scalar_i8_signbit_eq:18; CHECK-SD: // %bb.0:19; CHECK-SD-NEXT: lsl w8, w0, w120; CHECK-SD-NEXT: tst w8, #0x8021; CHECK-SD-NEXT: cset w0, eq22; CHECK-SD-NEXT: ret23;24; CHECK-GI-LABEL: scalar_i8_signbit_eq:25; CHECK-GI: // %bb.0:26; CHECK-GI-NEXT: mov w8, #128 // =0x8027; CHECK-GI-NEXT: and w9, w1, #0xff28; CHECK-GI-NEXT: lsr w8, w8, w929; CHECK-GI-NEXT: tst w8, w030; CHECK-GI-NEXT: cset w0, eq31; CHECK-GI-NEXT: ret32 %t0 = lshr i8 128, %y33 %t1 = and i8 %t0, %x34 %res = icmp eq i8 %t1, 035 ret i1 %res36}37 38define i1 @scalar_i8_lowestbit_eq(i8 %x, i8 %y) nounwind {39; CHECK-SD-LABEL: scalar_i8_lowestbit_eq:40; CHECK-SD: // %bb.0:41; CHECK-SD-NEXT: lsl w8, w0, w142; CHECK-SD-NEXT: tst w8, #0x143; CHECK-SD-NEXT: cset w0, eq44; CHECK-SD-NEXT: ret45;46; CHECK-GI-LABEL: scalar_i8_lowestbit_eq:47; CHECK-GI: // %bb.0:48; CHECK-GI-NEXT: mov w8, #1 // =0x149; CHECK-GI-NEXT: and w9, w1, #0xff50; CHECK-GI-NEXT: lsr w8, w8, w951; CHECK-GI-NEXT: tst w8, w052; CHECK-GI-NEXT: cset w0, eq53; CHECK-GI-NEXT: ret54 %t0 = lshr i8 1, %y55 %t1 = and i8 %t0, %x56 %res = icmp eq i8 %t1, 057 ret i1 %res58}59 60define i1 @scalar_i8_bitsinmiddle_eq(i8 %x, i8 %y) nounwind {61; CHECK-SD-LABEL: scalar_i8_bitsinmiddle_eq:62; CHECK-SD: // %bb.0:63; CHECK-SD-NEXT: lsl w8, w0, w164; CHECK-SD-NEXT: tst w8, #0x1865; CHECK-SD-NEXT: cset w0, eq66; CHECK-SD-NEXT: ret67;68; CHECK-GI-LABEL: scalar_i8_bitsinmiddle_eq:69; CHECK-GI: // %bb.0:70; CHECK-GI-NEXT: mov w8, #24 // =0x1871; CHECK-GI-NEXT: and w9, w1, #0xff72; CHECK-GI-NEXT: lsr w8, w8, w973; CHECK-GI-NEXT: tst w8, w074; CHECK-GI-NEXT: cset w0, eq75; CHECK-GI-NEXT: ret76 %t0 = lshr i8 24, %y77 %t1 = and i8 %t0, %x78 %res = icmp eq i8 %t1, 079 ret i1 %res80}81 82; i16 scalar83 84define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {85; CHECK-SD-LABEL: scalar_i16_signbit_eq:86; CHECK-SD: // %bb.0:87; CHECK-SD-NEXT: lsl w8, w0, w188; CHECK-SD-NEXT: tst w8, #0x800089; CHECK-SD-NEXT: cset w0, eq90; CHECK-SD-NEXT: ret91;92; CHECK-GI-LABEL: scalar_i16_signbit_eq:93; CHECK-GI: // %bb.0:94; CHECK-GI-NEXT: mov w8, #32768 // =0x800095; CHECK-GI-NEXT: and w9, w1, #0xffff96; CHECK-GI-NEXT: lsr w8, w8, w997; CHECK-GI-NEXT: tst w8, w098; CHECK-GI-NEXT: cset w0, eq99; CHECK-GI-NEXT: ret100 %t0 = lshr i16 32768, %y101 %t1 = and i16 %t0, %x102 %res = icmp eq i16 %t1, 0103 ret i1 %res104}105 106define i1 @scalar_i16_lowestbit_eq(i16 %x, i16 %y) nounwind {107; CHECK-SD-LABEL: scalar_i16_lowestbit_eq:108; CHECK-SD: // %bb.0:109; CHECK-SD-NEXT: lsl w8, w0, w1110; CHECK-SD-NEXT: tst w8, #0x1111; CHECK-SD-NEXT: cset w0, eq112; CHECK-SD-NEXT: ret113;114; CHECK-GI-LABEL: scalar_i16_lowestbit_eq:115; CHECK-GI: // %bb.0:116; CHECK-GI-NEXT: mov w8, #1 // =0x1117; CHECK-GI-NEXT: and w9, w1, #0xffff118; CHECK-GI-NEXT: lsr w8, w8, w9119; CHECK-GI-NEXT: tst w8, w0120; CHECK-GI-NEXT: cset w0, eq121; CHECK-GI-NEXT: ret122 %t0 = lshr i16 1, %y123 %t1 = and i16 %t0, %x124 %res = icmp eq i16 %t1, 0125 ret i1 %res126}127 128define i1 @scalar_i16_bitsinmiddle_eq(i16 %x, i16 %y) nounwind {129; CHECK-SD-LABEL: scalar_i16_bitsinmiddle_eq:130; CHECK-SD: // %bb.0:131; CHECK-SD-NEXT: lsl w8, w0, w1132; CHECK-SD-NEXT: tst w8, #0xff0133; CHECK-SD-NEXT: cset w0, eq134; CHECK-SD-NEXT: ret135;136; CHECK-GI-LABEL: scalar_i16_bitsinmiddle_eq:137; CHECK-GI: // %bb.0:138; CHECK-GI-NEXT: mov w8, #4080 // =0xff0139; CHECK-GI-NEXT: and w9, w1, #0xffff140; CHECK-GI-NEXT: lsr w8, w8, w9141; CHECK-GI-NEXT: tst w8, w0142; CHECK-GI-NEXT: cset w0, eq143; CHECK-GI-NEXT: ret144 %t0 = lshr i16 4080, %y145 %t1 = and i16 %t0, %x146 %res = icmp eq i16 %t1, 0147 ret i1 %res148}149 150; i32 scalar151 152define i1 @scalar_i32_signbit_eq(i32 %x, i32 %y) nounwind {153; CHECK-SD-LABEL: scalar_i32_signbit_eq:154; CHECK-SD: // %bb.0:155; CHECK-SD-NEXT: lsl w8, w0, w1156; CHECK-SD-NEXT: tst w8, #0x80000000157; CHECK-SD-NEXT: cset w0, eq158; CHECK-SD-NEXT: ret159;160; CHECK-GI-LABEL: scalar_i32_signbit_eq:161; CHECK-GI: // %bb.0:162; CHECK-GI-NEXT: mov w8, #-2147483648 // =0x80000000163; CHECK-GI-NEXT: lsr w8, w8, w1164; CHECK-GI-NEXT: tst w8, w0165; CHECK-GI-NEXT: cset w0, eq166; CHECK-GI-NEXT: ret167 %t0 = lshr i32 2147483648, %y168 %t1 = and i32 %t0, %x169 %res = icmp eq i32 %t1, 0170 ret i1 %res171}172 173define i1 @scalar_i32_lowestbit_eq(i32 %x, i32 %y) nounwind {174; CHECK-SD-LABEL: scalar_i32_lowestbit_eq:175; CHECK-SD: // %bb.0:176; CHECK-SD-NEXT: lsl w8, w0, w1177; CHECK-SD-NEXT: tst w8, #0x1178; CHECK-SD-NEXT: cset w0, eq179; CHECK-SD-NEXT: ret180;181; CHECK-GI-LABEL: scalar_i32_lowestbit_eq:182; CHECK-GI: // %bb.0:183; CHECK-GI-NEXT: mov w8, #1 // =0x1184; CHECK-GI-NEXT: lsr w8, w8, w1185; CHECK-GI-NEXT: tst w8, w0186; CHECK-GI-NEXT: cset w0, eq187; CHECK-GI-NEXT: ret188 %t0 = lshr i32 1, %y189 %t1 = and i32 %t0, %x190 %res = icmp eq i32 %t1, 0191 ret i1 %res192}193 194define i1 @scalar_i32_bitsinmiddle_eq(i32 %x, i32 %y) nounwind {195; CHECK-SD-LABEL: scalar_i32_bitsinmiddle_eq:196; CHECK-SD: // %bb.0:197; CHECK-SD-NEXT: lsl w8, w0, w1198; CHECK-SD-NEXT: tst w8, #0xffff00199; CHECK-SD-NEXT: cset w0, eq200; CHECK-SD-NEXT: ret201;202; CHECK-GI-LABEL: scalar_i32_bitsinmiddle_eq:203; CHECK-GI: // %bb.0:204; CHECK-GI-NEXT: mov w8, #16776960 // =0xffff00205; CHECK-GI-NEXT: lsr w8, w8, w1206; CHECK-GI-NEXT: tst w8, w0207; CHECK-GI-NEXT: cset w0, eq208; CHECK-GI-NEXT: ret209 %t0 = lshr i32 16776960, %y210 %t1 = and i32 %t0, %x211 %res = icmp eq i32 %t1, 0212 ret i1 %res213}214 215; i64 scalar216 217define i1 @scalar_i64_signbit_eq(i64 %x, i64 %y) nounwind {218; CHECK-SD-LABEL: scalar_i64_signbit_eq:219; CHECK-SD: // %bb.0:220; CHECK-SD-NEXT: lsl x8, x0, x1221; CHECK-SD-NEXT: tst x8, #0x8000000000000000222; CHECK-SD-NEXT: cset w0, eq223; CHECK-SD-NEXT: ret224;225; CHECK-GI-LABEL: scalar_i64_signbit_eq:226; CHECK-GI: // %bb.0:227; CHECK-GI-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000228; CHECK-GI-NEXT: lsr x8, x8, x1229; CHECK-GI-NEXT: tst x8, x0230; CHECK-GI-NEXT: cset w0, eq231; CHECK-GI-NEXT: ret232 %t0 = lshr i64 9223372036854775808, %y233 %t1 = and i64 %t0, %x234 %res = icmp eq i64 %t1, 0235 ret i1 %res236}237 238define i1 @scalar_i64_lowestbit_eq(i64 %x, i64 %y) nounwind {239; CHECK-SD-LABEL: scalar_i64_lowestbit_eq:240; CHECK-SD: // %bb.0:241; CHECK-SD-NEXT: lsl x8, x0, x1242; CHECK-SD-NEXT: tst x8, #0x1243; CHECK-SD-NEXT: cset w0, eq244; CHECK-SD-NEXT: ret245;246; CHECK-GI-LABEL: scalar_i64_lowestbit_eq:247; CHECK-GI: // %bb.0:248; CHECK-GI-NEXT: mov w8, #1 // =0x1249; CHECK-GI-NEXT: lsr x8, x8, x1250; CHECK-GI-NEXT: tst x8, x0251; CHECK-GI-NEXT: cset w0, eq252; CHECK-GI-NEXT: ret253 %t0 = lshr i64 1, %y254 %t1 = and i64 %t0, %x255 %res = icmp eq i64 %t1, 0256 ret i1 %res257}258 259define i1 @scalar_i64_bitsinmiddle_eq(i64 %x, i64 %y) nounwind {260; CHECK-SD-LABEL: scalar_i64_bitsinmiddle_eq:261; CHECK-SD: // %bb.0:262; CHECK-SD-NEXT: lsl x8, x0, x1263; CHECK-SD-NEXT: tst x8, #0xffffffff0000264; CHECK-SD-NEXT: cset w0, eq265; CHECK-SD-NEXT: ret266;267; CHECK-GI-LABEL: scalar_i64_bitsinmiddle_eq:268; CHECK-GI: // %bb.0:269; CHECK-GI-NEXT: mov x8, #281474976645120 // =0xffffffff0000270; CHECK-GI-NEXT: lsr x8, x8, x1271; CHECK-GI-NEXT: tst x8, x0272; CHECK-GI-NEXT: cset w0, eq273; CHECK-GI-NEXT: ret274 %t0 = lshr i64 281474976645120, %y275 %t1 = and i64 %t0, %x276 %res = icmp eq i64 %t1, 0277 ret i1 %res278}279 280;------------------------------------------------------------------------------;281; A few trivial vector tests282;------------------------------------------------------------------------------;283 284define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {285; CHECK-SD-LABEL: vec_4xi32_splat_eq:286; CHECK-SD: // %bb.0:287; CHECK-SD-NEXT: movi v2.4s, #1288; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v1.4s289; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b290; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0291; CHECK-SD-NEXT: xtn v0.4h, v0.4s292; CHECK-SD-NEXT: ret293;294; CHECK-GI-LABEL: vec_4xi32_splat_eq:295; CHECK-GI: // %bb.0:296; CHECK-GI-NEXT: movi v2.4s, #1297; CHECK-GI-NEXT: neg v1.4s, v1.4s298; CHECK-GI-NEXT: ushl v1.4s, v2.4s, v1.4s299; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b300; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, #0301; CHECK-GI-NEXT: xtn v0.4h, v0.4s302; CHECK-GI-NEXT: ret303 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y304 %t1 = and <4 x i32> %t0, %x305 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>306 ret <4 x i1> %res307}308 309define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {310; CHECK-LABEL: vec_4xi32_nonsplat_eq:311; CHECK: // %bb.0:312; CHECK-NEXT: adrp x8, .LCPI13_0313; CHECK-NEXT: neg v1.4s, v1.4s314; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]315; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s316; CHECK-NEXT: and v0.16b, v1.16b, v0.16b317; CHECK-NEXT: cmeq v0.4s, v0.4s, #0318; CHECK-NEXT: xtn v0.4h, v0.4s319; CHECK-NEXT: ret320 %t0 = lshr <4 x i32> <i32 0, i32 1, i32 16776960, i32 2147483648>, %y321 %t1 = and <4 x i32> %t0, %x322 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>323 ret <4 x i1> %res324}325 326define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {327; CHECK-SD-LABEL: vec_4xi32_nonsplat_undef0_eq:328; CHECK-SD: // %bb.0:329; CHECK-SD-NEXT: movi v2.4s, #1330; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v1.4s331; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b332; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0333; CHECK-SD-NEXT: xtn v0.4h, v0.4s334; CHECK-SD-NEXT: ret335;336; CHECK-GI-LABEL: vec_4xi32_nonsplat_undef0_eq:337; CHECK-GI: // %bb.0:338; CHECK-GI-NEXT: mov w8, #1 // =0x1339; CHECK-GI-NEXT: neg v1.4s, v1.4s340; CHECK-GI-NEXT: fmov s2, w8341; CHECK-GI-NEXT: mov v2.s[1], w8342; CHECK-GI-NEXT: mov v2.s[3], w8343; CHECK-GI-NEXT: ushl v1.4s, v2.4s, v1.4s344; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b345; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, #0346; CHECK-GI-NEXT: xtn v0.4h, v0.4s347; CHECK-GI-NEXT: ret348 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y349 %t1 = and <4 x i32> %t0, %x350 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>351 ret <4 x i1> %res352}353define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind {354; CHECK-SD-LABEL: vec_4xi32_nonsplat_undef1_eq:355; CHECK-SD: // %bb.0:356; CHECK-SD-NEXT: movi v2.4s, #1357; CHECK-SD-NEXT: neg v1.4s, v1.4s358; CHECK-SD-NEXT: ushl v1.4s, v2.4s, v1.4s359; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b360; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0361; CHECK-SD-NEXT: xtn v0.4h, v0.4s362; CHECK-SD-NEXT: ret363;364; CHECK-GI-LABEL: vec_4xi32_nonsplat_undef1_eq:365; CHECK-GI: // %bb.0:366; CHECK-GI-NEXT: movi d2, #0000000000000000367; CHECK-GI-NEXT: movi v3.4s, #1368; CHECK-GI-NEXT: neg v1.4s, v1.4s369; CHECK-GI-NEXT: mov v2.s[1], wzr370; CHECK-GI-NEXT: ushl v1.4s, v3.4s, v1.4s371; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b372; CHECK-GI-NEXT: mov v2.s[3], wzr373; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v2.4s374; CHECK-GI-NEXT: xtn v0.4h, v0.4s375; CHECK-GI-NEXT: ret376 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y377 %t1 = and <4 x i32> %t0, %x378 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>379 ret <4 x i1> %res380}381define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind {382; CHECK-SD-LABEL: vec_4xi32_nonsplat_undef2_eq:383; CHECK-SD: // %bb.0:384; CHECK-SD-NEXT: movi v2.4s, #1385; CHECK-SD-NEXT: neg v1.4s, v1.4s386; CHECK-SD-NEXT: ushl v1.4s, v2.4s, v1.4s387; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b388; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0389; CHECK-SD-NEXT: xtn v0.4h, v0.4s390; CHECK-SD-NEXT: ret391;392; CHECK-GI-LABEL: vec_4xi32_nonsplat_undef2_eq:393; CHECK-GI: // %bb.0:394; CHECK-GI-NEXT: mov w8, #1 // =0x1395; CHECK-GI-NEXT: movi d2, #0000000000000000396; CHECK-GI-NEXT: neg v1.4s, v1.4s397; CHECK-GI-NEXT: fmov s3, w8398; CHECK-GI-NEXT: mov v3.s[1], w8399; CHECK-GI-NEXT: mov v2.s[1], wzr400; CHECK-GI-NEXT: mov v3.s[3], w8401; CHECK-GI-NEXT: mov v2.s[3], wzr402; CHECK-GI-NEXT: ushl v1.4s, v3.4s, v1.4s403; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b404; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v2.4s405; CHECK-GI-NEXT: xtn v0.4h, v0.4s406; CHECK-GI-NEXT: ret407 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y408 %t1 = and <4 x i32> %t0, %x409 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>410 ret <4 x i1> %res411}412 413;------------------------------------------------------------------------------;414; A special tests415;------------------------------------------------------------------------------;416 417define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {418; CHECK-SD-LABEL: scalar_i8_signbit_ne:419; CHECK-SD: // %bb.0:420; CHECK-SD-NEXT: lsl w8, w0, w1421; CHECK-SD-NEXT: ubfx w0, w8, #7, #1422; CHECK-SD-NEXT: ret423;424; CHECK-GI-LABEL: scalar_i8_signbit_ne:425; CHECK-GI: // %bb.0:426; CHECK-GI-NEXT: mov w8, #128 // =0x80427; CHECK-GI-NEXT: and w9, w1, #0xff428; CHECK-GI-NEXT: lsr w8, w8, w9429; CHECK-GI-NEXT: tst w8, w0430; CHECK-GI-NEXT: cset w0, ne431; CHECK-GI-NEXT: ret432 %t0 = lshr i8 128, %y433 %t1 = and i8 %t0, %x434 %res = icmp ne i8 %t1, 0 ; we are perfectly happy with 'ne' predicate435 ret i1 %res436}437 438;------------------------------------------------------------------------------;439; What if X is a constant too?440;------------------------------------------------------------------------------;441 442define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {443; CHECK-LABEL: scalar_i32_x_is_const_eq:444; CHECK: // %bb.0:445; CHECK-NEXT: mov w8, #43605 // =0xaa55446; CHECK-NEXT: movk w8, #43605, lsl #16447; CHECK-NEXT: lsr w8, w8, w0448; CHECK-NEXT: tst w8, #0x1449; CHECK-NEXT: cset w0, eq450; CHECK-NEXT: ret451 %t0 = lshr i32 2857740885, %y452 %t1 = and i32 %t0, 1453 %res = icmp eq i32 %t1, 0454 ret i1 %res455}456define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {457; CHECK-LABEL: scalar_i32_x_is_const2_eq:458; CHECK: // %bb.0:459; CHECK-NEXT: mov w8, #1 // =0x1460; CHECK-NEXT: lsr w8, w8, w0461; CHECK-NEXT: cmp w8, #0462; CHECK-NEXT: cset w0, eq463; CHECK-NEXT: ret464 %t0 = lshr i32 1, %y465 %t1 = and i32 %t0, 2857740885466 %res = icmp eq i32 %t1, 0467 ret i1 %res468}469 470define i1 @scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {471; CHECK-LABEL: scalar_i8_bitsinmiddle_slt:472; CHECK: // %bb.0:473; CHECK-NEXT: mov w0, wzr474; CHECK-NEXT: ret475 %t0 = lshr i8 24, %y476 %t1 = and i8 %t0, %x477 %res = icmp slt i8 %t1, 0478 ret i1 %res479}480 481define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {482; CHECK-SD-LABEL: scalar_i8_signbit_eq_with_nonzero:483; CHECK-SD: // %bb.0:484; CHECK-SD-NEXT: mov w8, #128 // =0x80485; CHECK-SD-NEXT: lsr w8, w8, w1486; CHECK-SD-NEXT: and w8, w8, w0487; CHECK-SD-NEXT: cmp w8, #1488; CHECK-SD-NEXT: cset w0, eq489; CHECK-SD-NEXT: ret490;491; CHECK-GI-LABEL: scalar_i8_signbit_eq_with_nonzero:492; CHECK-GI: // %bb.0:493; CHECK-GI-NEXT: mov w8, #128 // =0x80494; CHECK-GI-NEXT: and w9, w1, #0xff495; CHECK-GI-NEXT: lsr w8, w8, w9496; CHECK-GI-NEXT: and w8, w8, w0497; CHECK-GI-NEXT: cmp w8, #1498; CHECK-GI-NEXT: cset w0, eq499; CHECK-GI-NEXT: ret500 %t0 = lshr i8 128, %y501 %t1 = and i8 %t0, %x502 %res = icmp eq i8 %t1, 1 ; should be comparing with 0503 ret i1 %res504}505