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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-unknown-unknown -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; We are looking for the following pattern here:6; (X & (C << Y)) ==/!= 07; It may be optimal to hoist the constant:8; ((X l>> Y) & C) ==/!= 09 10;------------------------------------------------------------------------------;11; A few scalar test12;------------------------------------------------------------------------------;13 14; i8 scalar15 16define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {17; CHECK-SD-LABEL: scalar_i8_signbit_eq:18; CHECK-SD: // %bb.0:19; CHECK-SD-NEXT: and w8, w0, #0xff20; CHECK-SD-NEXT: lsr w8, w8, w121; CHECK-SD-NEXT: tst w8, #0x8022; CHECK-SD-NEXT: cset w0, eq23; CHECK-SD-NEXT: ret24;25; CHECK-GI-LABEL: scalar_i8_signbit_eq:26; CHECK-GI: // %bb.0:27; CHECK-GI-NEXT: mov w8, #-128 // =0xffffff8028; CHECK-GI-NEXT: and w9, w1, #0xff29; CHECK-GI-NEXT: lsl w8, w8, w930; CHECK-GI-NEXT: and w8, w8, w031; CHECK-GI-NEXT: tst w8, #0xff32; CHECK-GI-NEXT: cset w0, eq33; CHECK-GI-NEXT: ret34 %t0 = shl i8 128, %y35 %t1 = and i8 %t0, %x36 %res = icmp eq i8 %t1, 037 ret i1 %res38}39 40define i1 @scalar_i8_lowestbit_eq(i8 %x, i8 %y) nounwind {41; CHECK-SD-LABEL: scalar_i8_lowestbit_eq:42; CHECK-SD: // %bb.0:43; CHECK-SD-NEXT: and w8, w0, #0xff44; CHECK-SD-NEXT: lsr w8, w8, w145; CHECK-SD-NEXT: tst w8, #0x146; CHECK-SD-NEXT: cset w0, eq47; CHECK-SD-NEXT: ret48;49; CHECK-GI-LABEL: scalar_i8_lowestbit_eq:50; CHECK-GI: // %bb.0:51; CHECK-GI-NEXT: mov w8, #1 // =0x152; CHECK-GI-NEXT: and w9, w1, #0xff53; CHECK-GI-NEXT: lsl w8, w8, w954; CHECK-GI-NEXT: and w8, w8, w055; CHECK-GI-NEXT: tst w8, #0xff56; CHECK-GI-NEXT: cset w0, eq57; CHECK-GI-NEXT: ret58 %t0 = shl i8 1, %y59 %t1 = and i8 %t0, %x60 %res = icmp eq i8 %t1, 061 ret i1 %res62}63 64define i1 @scalar_i8_bitsinmiddle_eq(i8 %x, i8 %y) nounwind {65; CHECK-SD-LABEL: scalar_i8_bitsinmiddle_eq:66; CHECK-SD: // %bb.0:67; CHECK-SD-NEXT: and w8, w0, #0xff68; CHECK-SD-NEXT: lsr w8, w8, w169; CHECK-SD-NEXT: tst w8, #0x1870; CHECK-SD-NEXT: cset w0, eq71; CHECK-SD-NEXT: ret72;73; CHECK-GI-LABEL: scalar_i8_bitsinmiddle_eq:74; CHECK-GI: // %bb.0:75; CHECK-GI-NEXT: mov w8, #24 // =0x1876; CHECK-GI-NEXT: and w9, w1, #0xff77; CHECK-GI-NEXT: lsl w8, w8, w978; CHECK-GI-NEXT: and w8, w8, w079; CHECK-GI-NEXT: tst w8, #0xff80; CHECK-GI-NEXT: cset w0, eq81; CHECK-GI-NEXT: ret82 %t0 = shl i8 24, %y83 %t1 = and i8 %t0, %x84 %res = icmp eq i8 %t1, 085 ret i1 %res86}87 88; i16 scalar89 90define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {91; CHECK-SD-LABEL: scalar_i16_signbit_eq:92; CHECK-SD: // %bb.0:93; CHECK-SD-NEXT: and w8, w0, #0xffff94; CHECK-SD-NEXT: lsr w8, w8, w195; CHECK-SD-NEXT: tst w8, #0x800096; CHECK-SD-NEXT: cset w0, eq97; CHECK-SD-NEXT: ret98;99; CHECK-GI-LABEL: scalar_i16_signbit_eq:100; CHECK-GI: // %bb.0:101; CHECK-GI-NEXT: mov w8, #-32768 // =0xffff8000102; CHECK-GI-NEXT: and w9, w1, #0xffff103; CHECK-GI-NEXT: lsl w8, w8, w9104; CHECK-GI-NEXT: and w8, w8, w0105; CHECK-GI-NEXT: tst w8, #0xffff106; CHECK-GI-NEXT: cset w0, eq107; CHECK-GI-NEXT: ret108 %t0 = shl i16 32768, %y109 %t1 = and i16 %t0, %x110 %res = icmp eq i16 %t1, 0111 ret i1 %res112}113 114define i1 @scalar_i16_lowestbit_eq(i16 %x, i16 %y) nounwind {115; CHECK-SD-LABEL: scalar_i16_lowestbit_eq:116; CHECK-SD: // %bb.0:117; CHECK-SD-NEXT: and w8, w0, #0xffff118; CHECK-SD-NEXT: lsr w8, w8, w1119; CHECK-SD-NEXT: tst w8, #0x1120; CHECK-SD-NEXT: cset w0, eq121; CHECK-SD-NEXT: ret122;123; CHECK-GI-LABEL: scalar_i16_lowestbit_eq:124; CHECK-GI: // %bb.0:125; CHECK-GI-NEXT: mov w8, #1 // =0x1126; CHECK-GI-NEXT: and w9, w1, #0xffff127; CHECK-GI-NEXT: lsl w8, w8, w9128; CHECK-GI-NEXT: and w8, w8, w0129; CHECK-GI-NEXT: tst w8, #0xffff130; CHECK-GI-NEXT: cset w0, eq131; CHECK-GI-NEXT: ret132 %t0 = shl i16 1, %y133 %t1 = and i16 %t0, %x134 %res = icmp eq i16 %t1, 0135 ret i1 %res136}137 138define i1 @scalar_i16_bitsinmiddle_eq(i16 %x, i16 %y) nounwind {139; CHECK-SD-LABEL: scalar_i16_bitsinmiddle_eq:140; CHECK-SD: // %bb.0:141; CHECK-SD-NEXT: and w8, w0, #0xffff142; CHECK-SD-NEXT: lsr w8, w8, w1143; CHECK-SD-NEXT: tst w8, #0xff0144; CHECK-SD-NEXT: cset w0, eq145; CHECK-SD-NEXT: ret146;147; CHECK-GI-LABEL: scalar_i16_bitsinmiddle_eq:148; CHECK-GI: // %bb.0:149; CHECK-GI-NEXT: mov w8, #4080 // =0xff0150; CHECK-GI-NEXT: and w9, w1, #0xffff151; CHECK-GI-NEXT: lsl w8, w8, w9152; CHECK-GI-NEXT: and w8, w8, w0153; CHECK-GI-NEXT: tst w8, #0xffff154; CHECK-GI-NEXT: cset w0, eq155; CHECK-GI-NEXT: ret156 %t0 = shl i16 4080, %y157 %t1 = and i16 %t0, %x158 %res = icmp eq i16 %t1, 0159 ret i1 %res160}161 162; i32 scalar163 164define i1 @scalar_i32_signbit_eq(i32 %x, i32 %y) nounwind {165; CHECK-SD-LABEL: scalar_i32_signbit_eq:166; CHECK-SD: // %bb.0:167; CHECK-SD-NEXT: lsr w8, w0, w1168; CHECK-SD-NEXT: tst w8, #0x80000000169; CHECK-SD-NEXT: cset w0, eq170; CHECK-SD-NEXT: ret171;172; CHECK-GI-LABEL: scalar_i32_signbit_eq:173; CHECK-GI: // %bb.0:174; CHECK-GI-NEXT: mov w8, #-2147483648 // =0x80000000175; CHECK-GI-NEXT: lsl w8, w8, w1176; CHECK-GI-NEXT: tst w8, w0177; CHECK-GI-NEXT: cset w0, eq178; CHECK-GI-NEXT: ret179 %t0 = shl i32 2147483648, %y180 %t1 = and i32 %t0, %x181 %res = icmp eq i32 %t1, 0182 ret i1 %res183}184 185define i1 @scalar_i32_lowestbit_eq(i32 %x, i32 %y) nounwind {186; CHECK-SD-LABEL: scalar_i32_lowestbit_eq:187; CHECK-SD: // %bb.0:188; CHECK-SD-NEXT: lsr w8, w0, w1189; CHECK-SD-NEXT: tst w8, #0x1190; CHECK-SD-NEXT: cset w0, eq191; CHECK-SD-NEXT: ret192;193; CHECK-GI-LABEL: scalar_i32_lowestbit_eq:194; CHECK-GI: // %bb.0:195; CHECK-GI-NEXT: mov w8, #1 // =0x1196; CHECK-GI-NEXT: lsl w8, w8, w1197; CHECK-GI-NEXT: tst w8, w0198; CHECK-GI-NEXT: cset w0, eq199; CHECK-GI-NEXT: ret200 %t0 = shl i32 1, %y201 %t1 = and i32 %t0, %x202 %res = icmp eq i32 %t1, 0203 ret i1 %res204}205 206define i1 @scalar_i32_bitsinmiddle_eq(i32 %x, i32 %y) nounwind {207; CHECK-SD-LABEL: scalar_i32_bitsinmiddle_eq:208; CHECK-SD: // %bb.0:209; CHECK-SD-NEXT: lsr w8, w0, w1210; CHECK-SD-NEXT: tst w8, #0xffff00211; CHECK-SD-NEXT: cset w0, eq212; CHECK-SD-NEXT: ret213;214; CHECK-GI-LABEL: scalar_i32_bitsinmiddle_eq:215; CHECK-GI: // %bb.0:216; CHECK-GI-NEXT: mov w8, #16776960 // =0xffff00217; CHECK-GI-NEXT: lsl w8, w8, w1218; CHECK-GI-NEXT: tst w8, w0219; CHECK-GI-NEXT: cset w0, eq220; CHECK-GI-NEXT: ret221 %t0 = shl i32 16776960, %y222 %t1 = and i32 %t0, %x223 %res = icmp eq i32 %t1, 0224 ret i1 %res225}226 227; i64 scalar228 229define i1 @scalar_i64_signbit_eq(i64 %x, i64 %y) nounwind {230; CHECK-SD-LABEL: scalar_i64_signbit_eq:231; CHECK-SD: // %bb.0:232; CHECK-SD-NEXT: lsr x8, x0, x1233; CHECK-SD-NEXT: tst x8, #0x8000000000000000234; CHECK-SD-NEXT: cset w0, eq235; CHECK-SD-NEXT: ret236;237; CHECK-GI-LABEL: scalar_i64_signbit_eq:238; CHECK-GI: // %bb.0:239; CHECK-GI-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000240; CHECK-GI-NEXT: lsl x8, x8, x1241; CHECK-GI-NEXT: tst x8, x0242; CHECK-GI-NEXT: cset w0, eq243; CHECK-GI-NEXT: ret244 %t0 = shl i64 9223372036854775808, %y245 %t1 = and i64 %t0, %x246 %res = icmp eq i64 %t1, 0247 ret i1 %res248}249 250define i1 @scalar_i64_lowestbit_eq(i64 %x, i64 %y) nounwind {251; CHECK-SD-LABEL: scalar_i64_lowestbit_eq:252; CHECK-SD: // %bb.0:253; CHECK-SD-NEXT: lsr x8, x0, x1254; CHECK-SD-NEXT: tst x8, #0x1255; CHECK-SD-NEXT: cset w0, eq256; CHECK-SD-NEXT: ret257;258; CHECK-GI-LABEL: scalar_i64_lowestbit_eq:259; CHECK-GI: // %bb.0:260; CHECK-GI-NEXT: mov w8, #1 // =0x1261; CHECK-GI-NEXT: lsl x8, x8, x1262; CHECK-GI-NEXT: tst x8, x0263; CHECK-GI-NEXT: cset w0, eq264; CHECK-GI-NEXT: ret265 %t0 = shl i64 1, %y266 %t1 = and i64 %t0, %x267 %res = icmp eq i64 %t1, 0268 ret i1 %res269}270 271define i1 @scalar_i64_bitsinmiddle_eq(i64 %x, i64 %y) nounwind {272; CHECK-SD-LABEL: scalar_i64_bitsinmiddle_eq:273; CHECK-SD: // %bb.0:274; CHECK-SD-NEXT: lsr x8, x0, x1275; CHECK-SD-NEXT: tst x8, #0xffffffff0000276; CHECK-SD-NEXT: cset w0, eq277; CHECK-SD-NEXT: ret278;279; CHECK-GI-LABEL: scalar_i64_bitsinmiddle_eq:280; CHECK-GI: // %bb.0:281; CHECK-GI-NEXT: mov x8, #281474976645120 // =0xffffffff0000282; CHECK-GI-NEXT: lsl x8, x8, x1283; CHECK-GI-NEXT: tst x8, x0284; CHECK-GI-NEXT: cset w0, eq285; CHECK-GI-NEXT: ret286 %t0 = shl i64 281474976645120, %y287 %t1 = and i64 %t0, %x288 %res = icmp eq i64 %t1, 0289 ret i1 %res290}291 292;------------------------------------------------------------------------------;293; A few trivial vector tests294;------------------------------------------------------------------------------;295 296define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {297; CHECK-LABEL: vec_4xi32_splat_eq:298; CHECK: // %bb.0:299; CHECK-NEXT: movi v2.4s, #1300; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s301; CHECK-NEXT: and v0.16b, v1.16b, v0.16b302; CHECK-NEXT: cmeq v0.4s, v0.4s, #0303; CHECK-NEXT: xtn v0.4h, v0.4s304; CHECK-NEXT: ret305 %t0 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y306 %t1 = and <4 x i32> %t0, %x307 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>308 ret <4 x i1> %res309}310 311define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {312; CHECK-LABEL: vec_4xi32_nonsplat_eq:313; CHECK: // %bb.0:314; CHECK-NEXT: adrp x8, .LCPI13_0315; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]316; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s317; CHECK-NEXT: and v0.16b, v1.16b, v0.16b318; CHECK-NEXT: cmeq v0.4s, v0.4s, #0319; CHECK-NEXT: xtn v0.4h, v0.4s320; CHECK-NEXT: ret321 %t0 = shl <4 x i32> <i32 0, i32 1, i32 16776960, i32 2147483648>, %y322 %t1 = and <4 x i32> %t0, %x323 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>324 ret <4 x i1> %res325}326 327define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {328; CHECK-SD-LABEL: vec_4xi32_nonsplat_undef0_eq:329; CHECK-SD: // %bb.0:330; CHECK-SD-NEXT: movi v2.4s, #1331; CHECK-SD-NEXT: ushl v1.4s, v2.4s, v1.4s332; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b333; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0334; CHECK-SD-NEXT: xtn v0.4h, v0.4s335; CHECK-SD-NEXT: ret336;337; CHECK-GI-LABEL: vec_4xi32_nonsplat_undef0_eq:338; CHECK-GI: // %bb.0:339; CHECK-GI-NEXT: mov w8, #1 // =0x1340; CHECK-GI-NEXT: fmov s2, w8341; CHECK-GI-NEXT: mov v2.s[1], w8342; CHECK-GI-NEXT: mov v2.s[3], w8343; CHECK-GI-NEXT: ushl v1.4s, v2.4s, v1.4s344; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b345; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, #0346; CHECK-GI-NEXT: xtn v0.4h, v0.4s347; CHECK-GI-NEXT: ret348 %t0 = shl <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y349 %t1 = and <4 x i32> %t0, %x350 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>351 ret <4 x i1> %res352}353define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind {354; CHECK-SD-LABEL: vec_4xi32_nonsplat_undef1_eq:355; CHECK-SD: // %bb.0:356; CHECK-SD-NEXT: movi v2.4s, #1357; CHECK-SD-NEXT: ushl v1.4s, v2.4s, v1.4s358; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b359; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0360; CHECK-SD-NEXT: xtn v0.4h, v0.4s361; CHECK-SD-NEXT: ret362;363; CHECK-GI-LABEL: vec_4xi32_nonsplat_undef1_eq:364; CHECK-GI: // %bb.0:365; CHECK-GI-NEXT: movi d3, #0000000000000000366; CHECK-GI-NEXT: movi v2.4s, #1367; CHECK-GI-NEXT: mov v3.s[1], wzr368; CHECK-GI-NEXT: ushl v1.4s, v2.4s, v1.4s369; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b370; CHECK-GI-NEXT: mov v3.s[3], wzr371; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v3.4s372; CHECK-GI-NEXT: xtn v0.4h, v0.4s373; CHECK-GI-NEXT: ret374 %t0 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y375 %t1 = and <4 x i32> %t0, %x376 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>377 ret <4 x i1> %res378}379define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind {380; CHECK-SD-LABEL: vec_4xi32_nonsplat_undef2_eq:381; CHECK-SD: // %bb.0:382; CHECK-SD-NEXT: movi v2.4s, #1383; CHECK-SD-NEXT: ushl v1.4s, v2.4s, v1.4s384; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b385; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0386; CHECK-SD-NEXT: xtn v0.4h, v0.4s387; CHECK-SD-NEXT: ret388;389; CHECK-GI-LABEL: vec_4xi32_nonsplat_undef2_eq:390; CHECK-GI: // %bb.0:391; CHECK-GI-NEXT: mov w8, #1 // =0x1392; CHECK-GI-NEXT: movi d3, #0000000000000000393; CHECK-GI-NEXT: fmov s2, w8394; CHECK-GI-NEXT: mov v2.s[1], w8395; CHECK-GI-NEXT: mov v3.s[1], wzr396; CHECK-GI-NEXT: mov v2.s[3], w8397; CHECK-GI-NEXT: mov v3.s[3], wzr398; CHECK-GI-NEXT: ushl v1.4s, v2.4s, v1.4s399; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b400; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v3.4s401; CHECK-GI-NEXT: xtn v0.4h, v0.4s402; CHECK-GI-NEXT: ret403 %t0 = shl <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y404 %t1 = and <4 x i32> %t0, %x405 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>406 ret <4 x i1> %res407}408 409;------------------------------------------------------------------------------;410; A special tests411;------------------------------------------------------------------------------;412 413define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {414; CHECK-SD-LABEL: scalar_i8_signbit_ne:415; CHECK-SD: // %bb.0:416; CHECK-SD-NEXT: and w8, w0, #0xff417; CHECK-SD-NEXT: lsr w8, w8, w1418; CHECK-SD-NEXT: lsr w0, w8, #7419; CHECK-SD-NEXT: ret420;421; CHECK-GI-LABEL: scalar_i8_signbit_ne:422; CHECK-GI: // %bb.0:423; CHECK-GI-NEXT: mov w8, #-128 // =0xffffff80424; CHECK-GI-NEXT: and w9, w1, #0xff425; CHECK-GI-NEXT: lsl w8, w8, w9426; CHECK-GI-NEXT: and w8, w8, w0427; CHECK-GI-NEXT: tst w8, #0xff428; CHECK-GI-NEXT: cset w0, ne429; CHECK-GI-NEXT: ret430 %t0 = shl i8 128, %y431 %t1 = and i8 %t0, %x432 %res = icmp ne i8 %t1, 0 ; we are perfectly happy with 'ne' predicate433 ret i1 %res434}435 436;------------------------------------------------------------------------------;437; What if X is a constant too?438;------------------------------------------------------------------------------;439 440define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {441; CHECK-LABEL: scalar_i32_x_is_const_eq:442; CHECK: // %bb.0:443; CHECK-NEXT: mov w8, #43605 // =0xaa55444; CHECK-NEXT: movk w8, #43605, lsl #16445; CHECK-NEXT: lsl w8, w8, w0446; CHECK-NEXT: tst w8, #0x1447; CHECK-NEXT: cset w0, eq448; CHECK-NEXT: ret449 %t0 = shl i32 2857740885, %y450 %t1 = and i32 %t0, 1451 %res = icmp eq i32 %t1, 0452 ret i1 %res453}454define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {455; CHECK-LABEL: scalar_i32_x_is_const2_eq:456; CHECK: // %bb.0:457; CHECK-NEXT: mov w8, #1 // =0x1458; CHECK-NEXT: mov w9, #43605 // =0xaa55459; CHECK-NEXT: lsl w8, w8, w0460; CHECK-NEXT: movk w9, #43605, lsl #16461; CHECK-NEXT: tst w8, w9462; CHECK-NEXT: cset w0, eq463; CHECK-NEXT: ret464 %t0 = shl i32 1, %y465 %t1 = and i32 %t0, 2857740885466 %res = icmp eq i32 %t1, 0467 ret i1 %res468}469 470define i1 @scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {471; CHECK-SD-LABEL: scalar_i8_bitsinmiddle_slt:472; CHECK-SD: // %bb.0:473; CHECK-SD-NEXT: mov w8, #24 // =0x18474; CHECK-SD-NEXT: lsl w8, w8, w1475; CHECK-SD-NEXT: and w8, w8, w0476; CHECK-SD-NEXT: ubfx w0, w8, #7, #1477; CHECK-SD-NEXT: ret478;479; CHECK-GI-LABEL: scalar_i8_bitsinmiddle_slt:480; CHECK-GI: // %bb.0:481; CHECK-GI-NEXT: mov w8, #24 // =0x18482; CHECK-GI-NEXT: and w9, w1, #0xff483; CHECK-GI-NEXT: lsl w8, w8, w9484; CHECK-GI-NEXT: and w8, w8, w0485; CHECK-GI-NEXT: sxtb w8, w8486; CHECK-GI-NEXT: cmp w8, #0487; CHECK-GI-NEXT: cset w0, mi488; CHECK-GI-NEXT: ret489 %t0 = shl i8 24, %y490 %t1 = and i8 %t0, %x491 %res = icmp slt i8 %t1, 0492 ret i1 %res493}494 495define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {496; CHECK-SD-LABEL: scalar_i8_signbit_eq_with_nonzero:497; CHECK-SD: // %bb.0:498; CHECK-SD-NEXT: mov w8, #-128 // =0xffffff80499; CHECK-SD-NEXT: lsl w8, w8, w1500; CHECK-SD-NEXT: and w8, w8, w0501; CHECK-SD-NEXT: and w8, w8, #0x80502; CHECK-SD-NEXT: cmp w8, #1503; CHECK-SD-NEXT: cset w0, eq504; CHECK-SD-NEXT: ret505;506; CHECK-GI-LABEL: scalar_i8_signbit_eq_with_nonzero:507; CHECK-GI: // %bb.0:508; CHECK-GI-NEXT: mov w0, wzr509; CHECK-GI-NEXT: ret510 %t0 = shl i8 128, %y511 %t1 = and i8 %t0, %x512 %res = icmp eq i8 %t1, 1 ; should be comparing with 0513 ret i1 %res514}515