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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s3 4; Optimize expanded SRL/SHL used as an input of5; SETCC comparing it with zero by removing rotation.6;7; See https://bugs.llvm.org/show_bug.cgi?id=501978define i128 @opt_setcc_lt_power_of_2(i128 %a) nounwind {9; CHECK-LABEL: opt_setcc_lt_power_of_2:10; CHECK: // %bb.0:11; CHECK-NEXT: .LBB0_1: // %loop12; CHECK-NEXT: // =>This Inner Loop Header: Depth=113; CHECK-NEXT: adds x0, x0, #114; CHECK-NEXT: cinc x1, x1, hs15; CHECK-NEXT: orr x8, x1, x0, lsr #6016; CHECK-NEXT: cbnz x8, .LBB0_117; CHECK-NEXT: // %bb.2: // %exit18; CHECK-NEXT: ret19 br label %loop20 21loop:22 %phi.a = phi i128 [ %a, %0 ], [ %inc, %loop ]23 %inc = add i128 %phi.a, 124 %cmp = icmp ult i128 %inc, 115292150460684697625 br i1 %cmp, label %exit, label %loop26 27exit:28 ret i128 %inc29}30 31define i1 @opt_setcc_srl_eq_zero(i128 %a) nounwind {32; CHECK-LABEL: opt_setcc_srl_eq_zero:33; CHECK: // %bb.0:34; CHECK-NEXT: orr x8, x1, x0, lsr #1735; CHECK-NEXT: cmp x8, #036; CHECK-NEXT: cset w0, eq37; CHECK-NEXT: ret38 %srl = lshr i128 %a, 1739 %cmp = icmp eq i128 %srl, 040 ret i1 %cmp41}42 43define i1 @opt_setcc_srl_ne_zero(i128 %a) nounwind {44; CHECK-LABEL: opt_setcc_srl_ne_zero:45; CHECK: // %bb.0:46; CHECK-NEXT: orr x8, x1, x0, lsr #1747; CHECK-NEXT: cmp x8, #048; CHECK-NEXT: cset w0, ne49; CHECK-NEXT: ret50 %srl = lshr i128 %a, 1751 %cmp = icmp ne i128 %srl, 052 ret i1 %cmp53}54 55define i1 @opt_setcc_shl_eq_zero(i128 %a) nounwind {56; CHECK-LABEL: opt_setcc_shl_eq_zero:57; CHECK: // %bb.0:58; CHECK-NEXT: orr x8, x0, x1, lsl #1759; CHECK-NEXT: cmp x8, #060; CHECK-NEXT: cset w0, eq61; CHECK-NEXT: ret62 %shl = shl i128 %a, 1763 %cmp = icmp eq i128 %shl, 064 ret i1 %cmp65}66 67define i1 @opt_setcc_shl_ne_zero(i128 %a) nounwind {68; CHECK-LABEL: opt_setcc_shl_ne_zero:69; CHECK: // %bb.0:70; CHECK-NEXT: orr x8, x0, x1, lsl #1771; CHECK-NEXT: cmp x8, #072; CHECK-NEXT: cset w0, ne73; CHECK-NEXT: ret74 %shl = shl i128 %a, 1775 %cmp = icmp ne i128 %shl, 076 ret i1 %cmp77}78 79; Negative test: optimization should not be applied if shift has multiple users.80define i1 @opt_setcc_shl_eq_zero_multiple_shl_users(i128 %a) nounwind {81; CHECK-LABEL: opt_setcc_shl_eq_zero_multiple_shl_users:82; CHECK: // %bb.0:83; CHECK-NEXT: stp x30, x19, [sp, #-16]! // 16-byte Folded Spill84; CHECK-NEXT: extr x1, x1, x0, #4785; CHECK-NEXT: lsl x0, x0, #1786; CHECK-NEXT: orr x8, x0, x187; CHECK-NEXT: cmp x8, #088; CHECK-NEXT: cset w19, eq89; CHECK-NEXT: bl use90; CHECK-NEXT: mov w0, w1991; CHECK-NEXT: ldp x30, x19, [sp], #16 // 16-byte Folded Reload92; CHECK-NEXT: ret93 %shl = shl i128 %a, 1794 %cmp = icmp eq i128 %shl, 095 call void @use(i128 %shl)96 ret i1 %cmp97}98 99; Check that optimization is applied to DAG having appropriate shape100; even if there were no actual shift's expansion.101define i1 @opt_setcc_expanded_shl_correct_shifts(i64 %a, i64 %b) nounwind {102; CHECK-LABEL: opt_setcc_expanded_shl_correct_shifts:103; CHECK: // %bb.0:104; CHECK-NEXT: orr x8, x1, x0, lsl #17105; CHECK-NEXT: cmp x8, #0106; CHECK-NEXT: cset w0, eq107; CHECK-NEXT: ret108 %shl.a = shl i64 %a, 17109 %srl.b = lshr i64 %b, 47110 %or.0 = or i64 %shl.a, %srl.b111 %shl.b = shl i64 %b, 17112 %or.1 = or i64 %or.0, %shl.b113 %cmp = icmp eq i64 %or.1, 0114 ret i1 %cmp115}116 117; Negative test: optimization should not be applied as118; constants used in shifts do not match.119define i1 @opt_setcc_expanded_shl_wrong_shifts(i64 %a, i64 %b) nounwind {120; CHECK-LABEL: opt_setcc_expanded_shl_wrong_shifts:121; CHECK: // %bb.0:122; CHECK-NEXT: extr x8, x0, x1, #47123; CHECK-NEXT: orr x8, x8, x1, lsl #18124; CHECK-NEXT: cmp x8, #0125; CHECK-NEXT: cset w0, eq126; CHECK-NEXT: ret127 %shl.a = shl i64 %a, 17128 %srl.b = lshr i64 %b, 47129 %or.0 = or i64 %shl.a, %srl.b130 %shl.b = shl i64 %b, 18131 %or.1 = or i64 %or.0, %shl.b132 %cmp = icmp eq i64 %or.1, 0133 ret i1 %cmp134}135 136define i1 @opt_setcc_shl_ne_zero_i256(i256 %a) nounwind {137; CHECK-LABEL: opt_setcc_shl_ne_zero_i256:138; CHECK: // %bb.0:139; CHECK-NEXT: orr x8, x2, x0140; CHECK-NEXT: orr x8, x1, x8141; CHECK-NEXT: orr x8, x8, x3, lsl #17142; CHECK-NEXT: cmp x8, #0143; CHECK-NEXT: cset w0, ne144; CHECK-NEXT: ret145 %shl = shl i256 %a, 17146 %cmp = icmp ne i256 %shl, 0147 ret i1 %cmp148}149 150declare void @use(i128 %a)151