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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define i64 @i64_i64(i64 %a, i64 %b, i64 %d, i64 %e) {6; CHECK-LABEL: i64_i64:7; CHECK: // %bb.0: // %entry8; CHECK-NEXT: cmp x0, x19; CHECK-NEXT: csel x0, x2, x3, lt10; CHECK-NEXT: ret11entry:12 %c = icmp slt i64 %a, %b13 %s = select i1 %c, i64 %d, i64 %e14 ret i64 %s15}16 17define i32 @i32_i32(i32 %a, i32 %b, i32 %d, i32 %e) {18; CHECK-LABEL: i32_i32:19; CHECK: // %bb.0: // %entry20; CHECK-NEXT: cmp w0, w121; CHECK-NEXT: csel w0, w2, w3, lt22; CHECK-NEXT: ret23entry:24 %c = icmp slt i32 %a, %b25 %s = select i1 %c, i32 %d, i32 %e26 ret i32 %s27}28 29define i16 @i16_i16(i16 %a, i16 %b, i16 %d, i16 %e) {30; CHECK-LABEL: i16_i16:31; CHECK: // %bb.0: // %entry32; CHECK-NEXT: sxth w8, w033; CHECK-NEXT: cmp w8, w1, sxth34; CHECK-NEXT: csel w0, w2, w3, lt35; CHECK-NEXT: ret36entry:37 %c = icmp slt i16 %a, %b38 %s = select i1 %c, i16 %d, i16 %e39 ret i16 %s40}41 42define i8 @i8_i8(i8 %a, i8 %b, i8 %d, i8 %e) {43; CHECK-LABEL: i8_i8:44; CHECK: // %bb.0: // %entry45; CHECK-NEXT: sxtb w8, w046; CHECK-NEXT: cmp w8, w1, sxtb47; CHECK-NEXT: csel w0, w2, w3, lt48; CHECK-NEXT: ret49entry:50 %c = icmp slt i8 %a, %b51 %s = select i1 %c, i8 %d, i8 %e52 ret i8 %s53}54 55define <2 x i1> @test_v2i64_eq(<2 x i64> %v1, <2 x i64> %v2) {56; CHECK-LABEL: test_v2i64_eq:57; CHECK: // %bb.0:58; CHECK-NEXT: cmeq v0.2d, v0.2d, v1.2d59; CHECK-NEXT: xtn v0.2s, v0.2d60; CHECK-NEXT: ret61 %cmp = icmp eq <2 x i64> %v1, %v262 ret <2 x i1> %cmp63}64 65define <4 x i1> @test_v4i64_eq(<4 x i64> %v1, <4 x i64> %v2) {66; CHECK-SD-LABEL: test_v4i64_eq:67; CHECK-SD: // %bb.0: // %entry68; CHECK-SD-NEXT: cmeq v1.2d, v1.2d, v3.2d69; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, v2.2d70; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s71; CHECK-SD-NEXT: xtn v0.4h, v0.4s72; CHECK-SD-NEXT: ret73;74; CHECK-GI-LABEL: test_v4i64_eq:75; CHECK-GI: // %bb.0: // %entry76; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v2.2d77; CHECK-GI-NEXT: cmeq v1.2d, v1.2d, v3.2d78; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s79; CHECK-GI-NEXT: xtn v0.4h, v0.4s80; CHECK-GI-NEXT: ret81entry:82 %cmp = icmp eq <4 x i64> %v1, %v283 ret <4 x i1> %cmp84}85 86define <4 x i1> @test_v4i32_eq(<4 x i32> %v1, <4 x i32> %v2) {87; CHECK-LABEL: test_v4i32_eq:88; CHECK: // %bb.0:89; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s90; CHECK-NEXT: xtn v0.4h, v0.4s91; CHECK-NEXT: ret92 %cmp = icmp eq <4 x i32> %v1, %v293 ret <4 x i1> %cmp94}95 96define <2 x i1> @test_v2i32_eq(<2 x i32> %v1, <2 x i32> %v2) {97; CHECK-LABEL: test_v2i32_eq:98; CHECK: // %bb.0:99; CHECK-NEXT: cmeq v0.2s, v0.2s, v1.2s100; CHECK-NEXT: ret101 %cmp = icmp eq <2 x i32> %v1, %v2102 ret <2 x i1> %cmp103}104 105define <2 x i1> @test_v2i16_eq(<2 x i16> %v1, <2 x i16> %v2) {106; CHECK-SD-LABEL: test_v2i16_eq:107; CHECK-SD: // %bb.0:108; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff109; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b110; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b111; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, v1.2s112; CHECK-SD-NEXT: ret113;114; CHECK-GI-LABEL: test_v2i16_eq:115; CHECK-GI: // %bb.0:116; CHECK-GI-NEXT: movi d2, #0x00ffff0000ffff117; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b118; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b119; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s120; CHECK-GI-NEXT: ret121 %cmp = icmp eq <2 x i16> %v1, %v2122 ret <2 x i1> %cmp123}124 125define <8 x i1> @test_v8i16_eq(<8 x i16> %v1, <8 x i16> %v2) {126; CHECK-LABEL: test_v8i16_eq:127; CHECK: // %bb.0:128; CHECK-NEXT: cmeq v0.8h, v0.8h, v1.8h129; CHECK-NEXT: xtn v0.8b, v0.8h130; CHECK-NEXT: ret131 %cmp = icmp eq <8 x i16> %v1, %v2132 ret <8 x i1> %cmp133}134 135define <4 x i1> @test_v4i16_eq(<4 x i16> %v1, <4 x i16> %v2) {136; CHECK-LABEL: test_v4i16_eq:137; CHECK: // %bb.0:138; CHECK-NEXT: cmeq v0.4h, v0.4h, v1.4h139; CHECK-NEXT: ret140 %cmp = icmp eq <4 x i16> %v1, %v2141 ret <4 x i1> %cmp142}143 144define <16 x i1> @test_v16i8_eq(<16 x i8> %v1, <16 x i8> %v2) {145; CHECK-LABEL: test_v16i8_eq:146; CHECK: // %bb.0:147; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b148; CHECK-NEXT: ret149 %cmp = icmp eq <16 x i8> %v1, %v2150 ret <16 x i1> %cmp151}152 153define <8 x i1> @test_v8i8_eq(<8 x i8> %v1, <8 x i8> %v2) {154; CHECK-LABEL: test_v8i8_eq:155; CHECK: // %bb.0:156; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b157; CHECK-NEXT: ret158 %cmp = icmp eq <8 x i8> %v1, %v2159 ret <8 x i1> %cmp160}161 162define <2 x i1> @test_v2i64_ne(<2 x i64> %v1, <2 x i64> %v2) {163; CHECK-LABEL: test_v2i64_ne:164; CHECK: // %bb.0:165; CHECK-NEXT: cmeq v0.2d, v0.2d, v1.2d166; CHECK-NEXT: mvn v0.16b, v0.16b167; CHECK-NEXT: xtn v0.2s, v0.2d168; CHECK-NEXT: ret169 %cmp = icmp ne <2 x i64> %v1, %v2170 ret <2 x i1> %cmp171}172 173define <4 x i1> @test_v4i64_ne(<4 x i64> %v1, <4 x i64> %v2) {174; CHECK-SD-LABEL: test_v4i64_ne:175; CHECK-SD: // %bb.0: // %entry176; CHECK-SD-NEXT: cmeq v1.2d, v1.2d, v3.2d177; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, v2.2d178; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s179; CHECK-SD-NEXT: mvn v0.16b, v0.16b180; CHECK-SD-NEXT: xtn v0.4h, v0.4s181; CHECK-SD-NEXT: ret182;183; CHECK-GI-LABEL: test_v4i64_ne:184; CHECK-GI: // %bb.0: // %entry185; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v2.2d186; CHECK-GI-NEXT: cmeq v1.2d, v1.2d, v3.2d187; CHECK-GI-NEXT: mvn v0.16b, v0.16b188; CHECK-GI-NEXT: mvn v1.16b, v1.16b189; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s190; CHECK-GI-NEXT: xtn v0.4h, v0.4s191; CHECK-GI-NEXT: ret192entry:193 %cmp = icmp ne <4 x i64> %v1, %v2194 ret <4 x i1> %cmp195}196 197define <4 x i1> @test_v4i32_ne(<4 x i32> %v1, <4 x i32> %v2) {198; CHECK-LABEL: test_v4i32_ne:199; CHECK: // %bb.0:200; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s201; CHECK-NEXT: mvn v0.16b, v0.16b202; CHECK-NEXT: xtn v0.4h, v0.4s203; CHECK-NEXT: ret204 %cmp = icmp ne <4 x i32> %v1, %v2205 ret <4 x i1> %cmp206}207 208define <2 x i1> @test_v2i32_ne(<2 x i32> %v1, <2 x i32> %v2) {209; CHECK-LABEL: test_v2i32_ne:210; CHECK: // %bb.0:211; CHECK-NEXT: cmeq v0.2s, v0.2s, v1.2s212; CHECK-NEXT: mvn v0.8b, v0.8b213; CHECK-NEXT: ret214 %cmp = icmp ne <2 x i32> %v1, %v2215 ret <2 x i1> %cmp216}217 218define <2 x i1> @test_v2i16_ne(<2 x i16> %v1, <2 x i16> %v2) {219; CHECK-SD-LABEL: test_v2i16_ne:220; CHECK-SD: // %bb.0:221; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff222; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b223; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b224; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, v1.2s225; CHECK-SD-NEXT: mvn v0.8b, v0.8b226; CHECK-SD-NEXT: ret227;228; CHECK-GI-LABEL: test_v2i16_ne:229; CHECK-GI: // %bb.0:230; CHECK-GI-NEXT: movi d2, #0x00ffff0000ffff231; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b232; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b233; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s234; CHECK-GI-NEXT: mvn v0.8b, v0.8b235; CHECK-GI-NEXT: ret236 %cmp = icmp ne <2 x i16> %v1, %v2237 ret <2 x i1> %cmp238}239 240define <8 x i1> @test_v8i16_ne(<8 x i16> %v1, <8 x i16> %v2) {241; CHECK-LABEL: test_v8i16_ne:242; CHECK: // %bb.0:243; CHECK-NEXT: cmeq v0.8h, v0.8h, v1.8h244; CHECK-NEXT: mvn v0.16b, v0.16b245; CHECK-NEXT: xtn v0.8b, v0.8h246; CHECK-NEXT: ret247 %cmp = icmp ne <8 x i16> %v1, %v2248 ret <8 x i1> %cmp249}250 251define <4 x i1> @test_v4i16_ne(<4 x i16> %v1, <4 x i16> %v2) {252; CHECK-LABEL: test_v4i16_ne:253; CHECK: // %bb.0:254; CHECK-NEXT: cmeq v0.4h, v0.4h, v1.4h255; CHECK-NEXT: mvn v0.8b, v0.8b256; CHECK-NEXT: ret257 %cmp = icmp ne <4 x i16> %v1, %v2258 ret <4 x i1> %cmp259}260 261define <16 x i1> @test_v16i8_ne(<16 x i8> %v1, <16 x i8> %v2) {262; CHECK-LABEL: test_v16i8_ne:263; CHECK: // %bb.0:264; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b265; CHECK-NEXT: mvn v0.16b, v0.16b266; CHECK-NEXT: ret267 %cmp = icmp ne <16 x i8> %v1, %v2268 ret <16 x i1> %cmp269}270 271define <8 x i1> @test_v8i8_ne(<8 x i8> %v1, <8 x i8> %v2) {272; CHECK-LABEL: test_v8i8_ne:273; CHECK: // %bb.0:274; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b275; CHECK-NEXT: mvn v0.8b, v0.8b276; CHECK-NEXT: ret277 %cmp = icmp ne <8 x i8> %v1, %v2278 ret <8 x i1> %cmp279}280 281define <2 x i1> @test_v2i64_ugt(<2 x i64> %v1, <2 x i64> %v2) {282; CHECK-LABEL: test_v2i64_ugt:283; CHECK: // %bb.0:284; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d285; CHECK-NEXT: xtn v0.2s, v0.2d286; CHECK-NEXT: ret287 %cmp = icmp ugt <2 x i64> %v1, %v2288 ret <2 x i1> %cmp289}290 291define <4 x i1> @test_v4i64_ugt(<4 x i64> %v1, <4 x i64> %v2) {292; CHECK-SD-LABEL: test_v4i64_ugt:293; CHECK-SD: // %bb.0: // %entry294; CHECK-SD-NEXT: cmhi v1.2d, v1.2d, v3.2d295; CHECK-SD-NEXT: cmhi v0.2d, v0.2d, v2.2d296; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s297; CHECK-SD-NEXT: xtn v0.4h, v0.4s298; CHECK-SD-NEXT: ret299;300; CHECK-GI-LABEL: test_v4i64_ugt:301; CHECK-GI: // %bb.0: // %entry302; CHECK-GI-NEXT: cmhi v0.2d, v0.2d, v2.2d303; CHECK-GI-NEXT: cmhi v1.2d, v1.2d, v3.2d304; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s305; CHECK-GI-NEXT: xtn v0.4h, v0.4s306; CHECK-GI-NEXT: ret307entry:308 %cmp = icmp ugt <4 x i64> %v1, %v2309 ret <4 x i1> %cmp310}311 312define <4 x i1> @test_v4i32_ugt(<4 x i32> %v1, <4 x i32> %v2) {313; CHECK-LABEL: test_v4i32_ugt:314; CHECK: // %bb.0:315; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s316; CHECK-NEXT: xtn v0.4h, v0.4s317; CHECK-NEXT: ret318 %cmp = icmp ugt <4 x i32> %v1, %v2319 ret <4 x i1> %cmp320}321 322define <2 x i1> @test_v2i32_ugt(<2 x i32> %v1, <2 x i32> %v2) {323; CHECK-LABEL: test_v2i32_ugt:324; CHECK: // %bb.0:325; CHECK-NEXT: cmhi v0.2s, v0.2s, v1.2s326; CHECK-NEXT: ret327 %cmp = icmp ugt <2 x i32> %v1, %v2328 ret <2 x i1> %cmp329}330 331define <2 x i1> @test_v2i16_ugt(<2 x i16> %v1, <2 x i16> %v2) {332; CHECK-SD-LABEL: test_v2i16_ugt:333; CHECK-SD: // %bb.0:334; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff335; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b336; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b337; CHECK-SD-NEXT: cmhi v0.2s, v0.2s, v1.2s338; CHECK-SD-NEXT: ret339;340; CHECK-GI-LABEL: test_v2i16_ugt:341; CHECK-GI: // %bb.0:342; CHECK-GI-NEXT: movi d2, #0x00ffff0000ffff343; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b344; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b345; CHECK-GI-NEXT: cmhi v0.2s, v0.2s, v1.2s346; CHECK-GI-NEXT: ret347 %cmp = icmp ugt <2 x i16> %v1, %v2348 ret <2 x i1> %cmp349}350 351define <8 x i1> @test_v8i16_ugt(<8 x i16> %v1, <8 x i16> %v2) {352; CHECK-LABEL: test_v8i16_ugt:353; CHECK: // %bb.0:354; CHECK-NEXT: cmhi v0.8h, v0.8h, v1.8h355; CHECK-NEXT: xtn v0.8b, v0.8h356; CHECK-NEXT: ret357 %cmp = icmp ugt <8 x i16> %v1, %v2358 ret <8 x i1> %cmp359}360 361define <4 x i1> @test_v4i16_ugt(<4 x i16> %v1, <4 x i16> %v2) {362; CHECK-LABEL: test_v4i16_ugt:363; CHECK: // %bb.0:364; CHECK-NEXT: cmhi v0.4h, v0.4h, v1.4h365; CHECK-NEXT: ret366 %cmp = icmp ugt <4 x i16> %v1, %v2367 ret <4 x i1> %cmp368}369 370define <16 x i1> @test_v16i8_ugt(<16 x i8> %v1, <16 x i8> %v2) {371; CHECK-LABEL: test_v16i8_ugt:372; CHECK: // %bb.0:373; CHECK-NEXT: cmhi v0.16b, v0.16b, v1.16b374; CHECK-NEXT: ret375 %cmp = icmp ugt <16 x i8> %v1, %v2376 ret <16 x i1> %cmp377}378 379define <8 x i1> @test_v8i8_ugt(<8 x i8> %v1, <8 x i8> %v2) {380; CHECK-LABEL: test_v8i8_ugt:381; CHECK: // %bb.0:382; CHECK-NEXT: cmhi v0.8b, v0.8b, v1.8b383; CHECK-NEXT: ret384 %cmp = icmp ugt <8 x i8> %v1, %v2385 ret <8 x i1> %cmp386}387 388define <2 x i1> @test_v2i64_uge(<2 x i64> %v1, <2 x i64> %v2) {389; CHECK-LABEL: test_v2i64_uge:390; CHECK: // %bb.0:391; CHECK-NEXT: cmhs v0.2d, v0.2d, v1.2d392; CHECK-NEXT: xtn v0.2s, v0.2d393; CHECK-NEXT: ret394 %cmp = icmp uge <2 x i64> %v1, %v2395 ret <2 x i1> %cmp396}397 398define <4 x i1> @test_v4i64_uge(<4 x i64> %v1, <4 x i64> %v2) {399; CHECK-SD-LABEL: test_v4i64_uge:400; CHECK-SD: // %bb.0: // %entry401; CHECK-SD-NEXT: cmhs v1.2d, v1.2d, v3.2d402; CHECK-SD-NEXT: cmhs v0.2d, v0.2d, v2.2d403; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s404; CHECK-SD-NEXT: xtn v0.4h, v0.4s405; CHECK-SD-NEXT: ret406;407; CHECK-GI-LABEL: test_v4i64_uge:408; CHECK-GI: // %bb.0: // %entry409; CHECK-GI-NEXT: cmhs v0.2d, v0.2d, v2.2d410; CHECK-GI-NEXT: cmhs v1.2d, v1.2d, v3.2d411; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s412; CHECK-GI-NEXT: xtn v0.4h, v0.4s413; CHECK-GI-NEXT: ret414entry:415 %cmp = icmp uge <4 x i64> %v1, %v2416 ret <4 x i1> %cmp417}418 419define <4 x i1> @test_v4i32_uge(<4 x i32> %v1, <4 x i32> %v2) {420; CHECK-LABEL: test_v4i32_uge:421; CHECK: // %bb.0:422; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s423; CHECK-NEXT: xtn v0.4h, v0.4s424; CHECK-NEXT: ret425 %cmp = icmp uge <4 x i32> %v1, %v2426 ret <4 x i1> %cmp427}428 429define <2 x i1> @test_v2i32_uge(<2 x i32> %v1, <2 x i32> %v2) {430; CHECK-LABEL: test_v2i32_uge:431; CHECK: // %bb.0:432; CHECK-NEXT: cmhs v0.2s, v0.2s, v1.2s433; CHECK-NEXT: ret434 %cmp = icmp uge <2 x i32> %v1, %v2435 ret <2 x i1> %cmp436}437 438define <2 x i1> @test_v2i16_uge(<2 x i16> %v1, <2 x i16> %v2) {439; CHECK-SD-LABEL: test_v2i16_uge:440; CHECK-SD: // %bb.0:441; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff442; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b443; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b444; CHECK-SD-NEXT: cmhs v0.2s, v0.2s, v1.2s445; CHECK-SD-NEXT: ret446;447; CHECK-GI-LABEL: test_v2i16_uge:448; CHECK-GI: // %bb.0:449; CHECK-GI-NEXT: movi d2, #0x00ffff0000ffff450; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b451; CHECK-GI-NEXT: and v1.8b, v1.8b, v2.8b452; CHECK-GI-NEXT: cmhs v0.2s, v0.2s, v1.2s453; CHECK-GI-NEXT: ret454 %cmp = icmp uge <2 x i16> %v1, %v2455 ret <2 x i1> %cmp456}457 458define <8 x i1> @test_v8i16_uge(<8 x i16> %v1, <8 x i16> %v2) {459; CHECK-LABEL: test_v8i16_uge:460; CHECK: // %bb.0:461; CHECK-NEXT: cmhs v0.8h, v0.8h, v1.8h462; CHECK-NEXT: xtn v0.8b, v0.8h463; CHECK-NEXT: ret464 %cmp = icmp uge <8 x i16> %v1, %v2465 ret <8 x i1> %cmp466}467 468define <4 x i1> @test_v4i16_uge(<4 x i16> %v1, <4 x i16> %v2) {469; CHECK-LABEL: test_v4i16_uge:470; CHECK: // %bb.0:471; CHECK-NEXT: cmhs v0.4h, v0.4h, v1.4h472; CHECK-NEXT: ret473 %cmp = icmp uge <4 x i16> %v1, %v2474 ret <4 x i1> %cmp475}476 477define <16 x i1> @test_v16i8_uge(<16 x i8> %v1, <16 x i8> %v2) {478; CHECK-LABEL: test_v16i8_uge:479; CHECK: // %bb.0:480; CHECK-NEXT: cmhs v0.16b, v0.16b, v1.16b481; CHECK-NEXT: ret482 %cmp = icmp uge <16 x i8> %v1, %v2483 ret <16 x i1> %cmp484}485 486define <8 x i1> @test_v8i8_uge(<8 x i8> %v1, <8 x i8> %v2) {487; CHECK-LABEL: test_v8i8_uge:488; CHECK: // %bb.0:489; CHECK-NEXT: cmhs v0.8b, v0.8b, v1.8b490; CHECK-NEXT: ret491 %cmp = icmp uge <8 x i8> %v1, %v2492 ret <8 x i1> %cmp493}494 495define <2 x i1> @test_v2i64_ult(<2 x i64> %v1, <2 x i64> %v2) {496; CHECK-LABEL: test_v2i64_ult:497; CHECK: // %bb.0:498; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d499; CHECK-NEXT: xtn v0.2s, v0.2d500; CHECK-NEXT: ret501 %cmp = icmp ult <2 x i64> %v1, %v2502 ret <2 x i1> %cmp503}504 505define <4 x i1> @test_v4i64_ult(<4 x i64> %v1, <4 x i64> %v2) {506; CHECK-SD-LABEL: test_v4i64_ult:507; CHECK-SD: // %bb.0: // %entry508; CHECK-SD-NEXT: cmhi v1.2d, v3.2d, v1.2d509; CHECK-SD-NEXT: cmhi v0.2d, v2.2d, v0.2d510; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s511; CHECK-SD-NEXT: xtn v0.4h, v0.4s512; CHECK-SD-NEXT: ret513;514; CHECK-GI-LABEL: test_v4i64_ult:515; CHECK-GI: // %bb.0: // %entry516; CHECK-GI-NEXT: cmhi v0.2d, v2.2d, v0.2d517; CHECK-GI-NEXT: cmhi v1.2d, v3.2d, v1.2d518; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s519; CHECK-GI-NEXT: xtn v0.4h, v0.4s520; CHECK-GI-NEXT: ret521entry:522 %cmp = icmp ult <4 x i64> %v1, %v2523 ret <4 x i1> %cmp524}525 526define <4 x i1> @test_v4i32_ult(<4 x i32> %v1, <4 x i32> %v2) {527; CHECK-LABEL: test_v4i32_ult:528; CHECK: // %bb.0:529; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s530; CHECK-NEXT: xtn v0.4h, v0.4s531; CHECK-NEXT: ret532 %cmp = icmp ult <4 x i32> %v1, %v2533 ret <4 x i1> %cmp534}535 536define <2 x i1> @test_v2i32_ult(<2 x i32> %v1, <2 x i32> %v2) {537; CHECK-LABEL: test_v2i32_ult:538; CHECK: // %bb.0:539; CHECK-NEXT: cmhi v0.2s, v1.2s, v0.2s540; CHECK-NEXT: ret541 %cmp = icmp ult <2 x i32> %v1, %v2542 ret <2 x i1> %cmp543}544 545define <2 x i1> @test_v2i16_ult(<2 x i16> %v1, <2 x i16> %v2) {546; CHECK-LABEL: test_v2i16_ult:547; CHECK: // %bb.0:548; CHECK-NEXT: movi d2, #0x00ffff0000ffff549; CHECK-NEXT: and v0.8b, v0.8b, v2.8b550; CHECK-NEXT: and v1.8b, v1.8b, v2.8b551; CHECK-NEXT: cmhi v0.2s, v1.2s, v0.2s552; CHECK-NEXT: ret553 %cmp = icmp ult <2 x i16> %v1, %v2554 ret <2 x i1> %cmp555}556 557define <8 x i1> @test_v8i16_ult(<8 x i16> %v1, <8 x i16> %v2) {558; CHECK-LABEL: test_v8i16_ult:559; CHECK: // %bb.0:560; CHECK-NEXT: cmhi v0.8h, v1.8h, v0.8h561; CHECK-NEXT: xtn v0.8b, v0.8h562; CHECK-NEXT: ret563 %cmp = icmp ult <8 x i16> %v1, %v2564 ret <8 x i1> %cmp565}566 567define <4 x i1> @test_v4i16_ult(<4 x i16> %v1, <4 x i16> %v2) {568; CHECK-LABEL: test_v4i16_ult:569; CHECK: // %bb.0:570; CHECK-NEXT: cmhi v0.4h, v1.4h, v0.4h571; CHECK-NEXT: ret572 %cmp = icmp ult <4 x i16> %v1, %v2573 ret <4 x i1> %cmp574}575 576define <16 x i1> @test_v16i8_ult(<16 x i8> %v1, <16 x i8> %v2) {577; CHECK-LABEL: test_v16i8_ult:578; CHECK: // %bb.0:579; CHECK-NEXT: cmhi v0.16b, v1.16b, v0.16b580; CHECK-NEXT: ret581 %cmp = icmp ult <16 x i8> %v1, %v2582 ret <16 x i1> %cmp583}584 585define <8 x i1> @test_v8i8_ult(<8 x i8> %v1, <8 x i8> %v2) {586; CHECK-LABEL: test_v8i8_ult:587; CHECK: // %bb.0:588; CHECK-NEXT: cmhi v0.8b, v1.8b, v0.8b589; CHECK-NEXT: ret590 %cmp = icmp ult <8 x i8> %v1, %v2591 ret <8 x i1> %cmp592}593 594define <2 x i1> @test_v2i64_ule(<2 x i64> %v1, <2 x i64> %v2) {595; CHECK-LABEL: test_v2i64_ule:596; CHECK: // %bb.0:597; CHECK-NEXT: cmhs v0.2d, v1.2d, v0.2d598; CHECK-NEXT: xtn v0.2s, v0.2d599; CHECK-NEXT: ret600 %cmp = icmp ule <2 x i64> %v1, %v2601 ret <2 x i1> %cmp602}603 604define <4 x i1> @test_v4i64_ule(<4 x i64> %v1, <4 x i64> %v2) {605; CHECK-SD-LABEL: test_v4i64_ule:606; CHECK-SD: // %bb.0: // %entry607; CHECK-SD-NEXT: cmhs v1.2d, v3.2d, v1.2d608; CHECK-SD-NEXT: cmhs v0.2d, v2.2d, v0.2d609; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s610; CHECK-SD-NEXT: xtn v0.4h, v0.4s611; CHECK-SD-NEXT: ret612;613; CHECK-GI-LABEL: test_v4i64_ule:614; CHECK-GI: // %bb.0: // %entry615; CHECK-GI-NEXT: cmhs v0.2d, v2.2d, v0.2d616; CHECK-GI-NEXT: cmhs v1.2d, v3.2d, v1.2d617; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s618; CHECK-GI-NEXT: xtn v0.4h, v0.4s619; CHECK-GI-NEXT: ret620entry:621 %cmp = icmp ule <4 x i64> %v1, %v2622 ret <4 x i1> %cmp623}624 625define <4 x i1> @test_v4i32_ule(<4 x i32> %v1, <4 x i32> %v2) {626; CHECK-LABEL: test_v4i32_ule:627; CHECK: // %bb.0:628; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s629; CHECK-NEXT: xtn v0.4h, v0.4s630; CHECK-NEXT: ret631 %cmp = icmp ule <4 x i32> %v1, %v2632 ret <4 x i1> %cmp633}634 635define <2 x i1> @test_v2i32_ule(<2 x i32> %v1, <2 x i32> %v2) {636; CHECK-LABEL: test_v2i32_ule:637; CHECK: // %bb.0:638; CHECK-NEXT: cmhs v0.2s, v1.2s, v0.2s639; CHECK-NEXT: ret640 %cmp = icmp ule <2 x i32> %v1, %v2641 ret <2 x i1> %cmp642}643 644define <2 x i1> @test_v2i16_ule(<2 x i16> %v1, <2 x i16> %v2) {645; CHECK-LABEL: test_v2i16_ule:646; CHECK: // %bb.0:647; CHECK-NEXT: movi d2, #0x00ffff0000ffff648; CHECK-NEXT: and v0.8b, v0.8b, v2.8b649; CHECK-NEXT: and v1.8b, v1.8b, v2.8b650; CHECK-NEXT: cmhs v0.2s, v1.2s, v0.2s651; CHECK-NEXT: ret652 %cmp = icmp ule <2 x i16> %v1, %v2653 ret <2 x i1> %cmp654}655 656define <8 x i1> @test_v8i16_ule(<8 x i16> %v1, <8 x i16> %v2) {657; CHECK-LABEL: test_v8i16_ule:658; CHECK: // %bb.0:659; CHECK-NEXT: cmhs v0.8h, v1.8h, v0.8h660; CHECK-NEXT: xtn v0.8b, v0.8h661; CHECK-NEXT: ret662 %cmp = icmp ule <8 x i16> %v1, %v2663 ret <8 x i1> %cmp664}665 666define <4 x i1> @test_v4i16_ule(<4 x i16> %v1, <4 x i16> %v2) {667; CHECK-LABEL: test_v4i16_ule:668; CHECK: // %bb.0:669; CHECK-NEXT: cmhs v0.4h, v1.4h, v0.4h670; CHECK-NEXT: ret671 %cmp = icmp ule <4 x i16> %v1, %v2672 ret <4 x i1> %cmp673}674 675define <16 x i1> @test_v16i8_ule(<16 x i8> %v1, <16 x i8> %v2) {676; CHECK-LABEL: test_v16i8_ule:677; CHECK: // %bb.0:678; CHECK-NEXT: cmhs v0.16b, v1.16b, v0.16b679; CHECK-NEXT: ret680 %cmp = icmp ule <16 x i8> %v1, %v2681 ret <16 x i1> %cmp682}683 684define <8 x i1> @test_v8i8_ule(<8 x i8> %v1, <8 x i8> %v2) {685; CHECK-LABEL: test_v8i8_ule:686; CHECK: // %bb.0:687; CHECK-NEXT: cmhs v0.8b, v1.8b, v0.8b688; CHECK-NEXT: ret689 %cmp = icmp ule <8 x i8> %v1, %v2690 ret <8 x i1> %cmp691}692 693define <2 x i1> @test_v2i64_sgt(<2 x i64> %v1, <2 x i64> %v2) {694; CHECK-LABEL: test_v2i64_sgt:695; CHECK: // %bb.0:696; CHECK-NEXT: cmgt v0.2d, v0.2d, v1.2d697; CHECK-NEXT: xtn v0.2s, v0.2d698; CHECK-NEXT: ret699 %cmp = icmp sgt <2 x i64> %v1, %v2700 ret <2 x i1> %cmp701}702 703define <4 x i1> @test_v4i64_sgt(<4 x i64> %v1, <4 x i64> %v2) {704; CHECK-SD-LABEL: test_v4i64_sgt:705; CHECK-SD: // %bb.0: // %entry706; CHECK-SD-NEXT: cmgt v1.2d, v1.2d, v3.2d707; CHECK-SD-NEXT: cmgt v0.2d, v0.2d, v2.2d708; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s709; CHECK-SD-NEXT: xtn v0.4h, v0.4s710; CHECK-SD-NEXT: ret711;712; CHECK-GI-LABEL: test_v4i64_sgt:713; CHECK-GI: // %bb.0: // %entry714; CHECK-GI-NEXT: cmgt v0.2d, v0.2d, v2.2d715; CHECK-GI-NEXT: cmgt v1.2d, v1.2d, v3.2d716; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s717; CHECK-GI-NEXT: xtn v0.4h, v0.4s718; CHECK-GI-NEXT: ret719entry:720 %cmp = icmp sgt <4 x i64> %v1, %v2721 ret <4 x i1> %cmp722}723 724define <4 x i1> @test_v4i32_sgt(<4 x i32> %v1, <4 x i32> %v2) {725; CHECK-LABEL: test_v4i32_sgt:726; CHECK: // %bb.0:727; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s728; CHECK-NEXT: xtn v0.4h, v0.4s729; CHECK-NEXT: ret730 %cmp = icmp sgt <4 x i32> %v1, %v2731 ret <4 x i1> %cmp732}733 734define <2 x i1> @test_v2i32_sgt(<2 x i32> %v1, <2 x i32> %v2) {735; CHECK-LABEL: test_v2i32_sgt:736; CHECK: // %bb.0:737; CHECK-NEXT: cmgt v0.2s, v0.2s, v1.2s738; CHECK-NEXT: ret739 %cmp = icmp sgt <2 x i32> %v1, %v2740 ret <2 x i1> %cmp741}742 743define <2 x i1> @test_v2i16_sgt(<2 x i16> %v1, <2 x i16> %v2) {744; CHECK-SD-LABEL: test_v2i16_sgt:745; CHECK-SD: // %bb.0:746; CHECK-SD-NEXT: shl v1.2s, v1.2s, #16747; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16748; CHECK-SD-NEXT: sshr v1.2s, v1.2s, #16749; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #16750; CHECK-SD-NEXT: cmgt v0.2s, v0.2s, v1.2s751; CHECK-SD-NEXT: ret752;753; CHECK-GI-LABEL: test_v2i16_sgt:754; CHECK-GI: // %bb.0:755; CHECK-GI-NEXT: shl v0.2s, v0.2s, #16756; CHECK-GI-NEXT: shl v1.2s, v1.2s, #16757; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #16758; CHECK-GI-NEXT: sshr v1.2s, v1.2s, #16759; CHECK-GI-NEXT: cmgt v0.2s, v0.2s, v1.2s760; CHECK-GI-NEXT: ret761 %cmp = icmp sgt <2 x i16> %v1, %v2762 ret <2 x i1> %cmp763}764 765define <8 x i1> @test_v8i16_sgt(<8 x i16> %v1, <8 x i16> %v2) {766; CHECK-LABEL: test_v8i16_sgt:767; CHECK: // %bb.0:768; CHECK-NEXT: cmgt v0.8h, v0.8h, v1.8h769; CHECK-NEXT: xtn v0.8b, v0.8h770; CHECK-NEXT: ret771 %cmp = icmp sgt <8 x i16> %v1, %v2772 ret <8 x i1> %cmp773}774 775define <4 x i1> @test_v4i16_sgt(<4 x i16> %v1, <4 x i16> %v2) {776; CHECK-LABEL: test_v4i16_sgt:777; CHECK: // %bb.0:778; CHECK-NEXT: cmgt v0.4h, v0.4h, v1.4h779; CHECK-NEXT: ret780 %cmp = icmp sgt <4 x i16> %v1, %v2781 ret <4 x i1> %cmp782}783 784define <16 x i1> @test_v16i8_sgt(<16 x i8> %v1, <16 x i8> %v2) {785; CHECK-LABEL: test_v16i8_sgt:786; CHECK: // %bb.0:787; CHECK-NEXT: cmgt v0.16b, v0.16b, v1.16b788; CHECK-NEXT: ret789 %cmp = icmp sgt <16 x i8> %v1, %v2790 ret <16 x i1> %cmp791}792 793define <8 x i1> @test_v8i8_sgt(<8 x i8> %v1, <8 x i8> %v2) {794; CHECK-LABEL: test_v8i8_sgt:795; CHECK: // %bb.0:796; CHECK-NEXT: cmgt v0.8b, v0.8b, v1.8b797; CHECK-NEXT: ret798 %cmp = icmp sgt <8 x i8> %v1, %v2799 ret <8 x i1> %cmp800}801 802define <2 x i1> @test_v2i64_sge(<2 x i64> %v1, <2 x i64> %v2) {803; CHECK-LABEL: test_v2i64_sge:804; CHECK: // %bb.0:805; CHECK-NEXT: cmge v0.2d, v0.2d, v1.2d806; CHECK-NEXT: xtn v0.2s, v0.2d807; CHECK-NEXT: ret808 %cmp = icmp sge <2 x i64> %v1, %v2809 ret <2 x i1> %cmp810}811 812define <4 x i1> @test_v4i64_sge(<4 x i64> %v1, <4 x i64> %v2) {813; CHECK-SD-LABEL: test_v4i64_sge:814; CHECK-SD: // %bb.0: // %entry815; CHECK-SD-NEXT: cmge v1.2d, v1.2d, v3.2d816; CHECK-SD-NEXT: cmge v0.2d, v0.2d, v2.2d817; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s818; CHECK-SD-NEXT: xtn v0.4h, v0.4s819; CHECK-SD-NEXT: ret820;821; CHECK-GI-LABEL: test_v4i64_sge:822; CHECK-GI: // %bb.0: // %entry823; CHECK-GI-NEXT: cmge v0.2d, v0.2d, v2.2d824; CHECK-GI-NEXT: cmge v1.2d, v1.2d, v3.2d825; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s826; CHECK-GI-NEXT: xtn v0.4h, v0.4s827; CHECK-GI-NEXT: ret828entry:829 %cmp = icmp sge <4 x i64> %v1, %v2830 ret <4 x i1> %cmp831}832 833define <4 x i1> @test_v4i32_sge(<4 x i32> %v1, <4 x i32> %v2) {834; CHECK-LABEL: test_v4i32_sge:835; CHECK: // %bb.0:836; CHECK-NEXT: cmge v0.4s, v0.4s, v1.4s837; CHECK-NEXT: xtn v0.4h, v0.4s838; CHECK-NEXT: ret839 %cmp = icmp sge <4 x i32> %v1, %v2840 ret <4 x i1> %cmp841}842 843define <2 x i1> @test_v2i32_sge(<2 x i32> %v1, <2 x i32> %v2) {844; CHECK-LABEL: test_v2i32_sge:845; CHECK: // %bb.0:846; CHECK-NEXT: cmge v0.2s, v0.2s, v1.2s847; CHECK-NEXT: ret848 %cmp = icmp sge <2 x i32> %v1, %v2849 ret <2 x i1> %cmp850}851 852define <2 x i1> @test_v2i16_sge(<2 x i16> %v1, <2 x i16> %v2) {853; CHECK-SD-LABEL: test_v2i16_sge:854; CHECK-SD: // %bb.0:855; CHECK-SD-NEXT: shl v1.2s, v1.2s, #16856; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16857; CHECK-SD-NEXT: sshr v1.2s, v1.2s, #16858; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #16859; CHECK-SD-NEXT: cmge v0.2s, v0.2s, v1.2s860; CHECK-SD-NEXT: ret861;862; CHECK-GI-LABEL: test_v2i16_sge:863; CHECK-GI: // %bb.0:864; CHECK-GI-NEXT: shl v0.2s, v0.2s, #16865; CHECK-GI-NEXT: shl v1.2s, v1.2s, #16866; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #16867; CHECK-GI-NEXT: sshr v1.2s, v1.2s, #16868; CHECK-GI-NEXT: cmge v0.2s, v0.2s, v1.2s869; CHECK-GI-NEXT: ret870 %cmp = icmp sge <2 x i16> %v1, %v2871 ret <2 x i1> %cmp872}873 874define <8 x i1> @test_v8i16_sge(<8 x i16> %v1, <8 x i16> %v2) {875; CHECK-LABEL: test_v8i16_sge:876; CHECK: // %bb.0:877; CHECK-NEXT: cmge v0.8h, v0.8h, v1.8h878; CHECK-NEXT: xtn v0.8b, v0.8h879; CHECK-NEXT: ret880 %cmp = icmp sge <8 x i16> %v1, %v2881 ret <8 x i1> %cmp882}883 884define <4 x i1> @test_v4i16_sge(<4 x i16> %v1, <4 x i16> %v2) {885; CHECK-LABEL: test_v4i16_sge:886; CHECK: // %bb.0:887; CHECK-NEXT: cmge v0.4h, v0.4h, v1.4h888; CHECK-NEXT: ret889 %cmp = icmp sge <4 x i16> %v1, %v2890 ret <4 x i1> %cmp891}892 893define <16 x i1> @test_v16i8_sge(<16 x i8> %v1, <16 x i8> %v2) {894; CHECK-LABEL: test_v16i8_sge:895; CHECK: // %bb.0:896; CHECK-NEXT: cmge v0.16b, v0.16b, v1.16b897; CHECK-NEXT: ret898 %cmp = icmp sge <16 x i8> %v1, %v2899 ret <16 x i1> %cmp900}901 902define <8 x i1> @test_v8i8_sge(<8 x i8> %v1, <8 x i8> %v2) {903; CHECK-LABEL: test_v8i8_sge:904; CHECK: // %bb.0:905; CHECK-NEXT: cmge v0.8b, v0.8b, v1.8b906; CHECK-NEXT: ret907 %cmp = icmp sge <8 x i8> %v1, %v2908 ret <8 x i1> %cmp909}910 911define <2 x i1> @test_v2i64_slt(<2 x i64> %v1, <2 x i64> %v2) {912; CHECK-LABEL: test_v2i64_slt:913; CHECK: // %bb.0:914; CHECK-NEXT: cmgt v0.2d, v1.2d, v0.2d915; CHECK-NEXT: xtn v0.2s, v0.2d916; CHECK-NEXT: ret917 %cmp = icmp slt <2 x i64> %v1, %v2918 ret <2 x i1> %cmp919}920 921define <4 x i1> @test_v4i64_slt(<4 x i64> %v1, <4 x i64> %v2) {922; CHECK-SD-LABEL: test_v4i64_slt:923; CHECK-SD: // %bb.0: // %entry924; CHECK-SD-NEXT: cmgt v1.2d, v3.2d, v1.2d925; CHECK-SD-NEXT: cmgt v0.2d, v2.2d, v0.2d926; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s927; CHECK-SD-NEXT: xtn v0.4h, v0.4s928; CHECK-SD-NEXT: ret929;930; CHECK-GI-LABEL: test_v4i64_slt:931; CHECK-GI: // %bb.0: // %entry932; CHECK-GI-NEXT: cmgt v0.2d, v2.2d, v0.2d933; CHECK-GI-NEXT: cmgt v1.2d, v3.2d, v1.2d934; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s935; CHECK-GI-NEXT: xtn v0.4h, v0.4s936; CHECK-GI-NEXT: ret937entry:938 %cmp = icmp slt <4 x i64> %v1, %v2939 ret <4 x i1> %cmp940}941 942define <4 x i1> @test_v4i32_slt(<4 x i32> %v1, <4 x i32> %v2) {943; CHECK-LABEL: test_v4i32_slt:944; CHECK: // %bb.0:945; CHECK-NEXT: cmgt v0.4s, v1.4s, v0.4s946; CHECK-NEXT: xtn v0.4h, v0.4s947; CHECK-NEXT: ret948 %cmp = icmp slt <4 x i32> %v1, %v2949 ret <4 x i1> %cmp950}951 952define <2 x i1> @test_v2i32_slt(<2 x i32> %v1, <2 x i32> %v2) {953; CHECK-LABEL: test_v2i32_slt:954; CHECK: // %bb.0:955; CHECK-NEXT: cmgt v0.2s, v1.2s, v0.2s956; CHECK-NEXT: ret957 %cmp = icmp slt <2 x i32> %v1, %v2958 ret <2 x i1> %cmp959}960 961define <2 x i1> @test_v2i16_slt(<2 x i16> %v1, <2 x i16> %v2) {962; CHECK-LABEL: test_v2i16_slt:963; CHECK: // %bb.0:964; CHECK-NEXT: shl v0.2s, v0.2s, #16965; CHECK-NEXT: shl v1.2s, v1.2s, #16966; CHECK-NEXT: sshr v0.2s, v0.2s, #16967; CHECK-NEXT: sshr v1.2s, v1.2s, #16968; CHECK-NEXT: cmgt v0.2s, v1.2s, v0.2s969; CHECK-NEXT: ret970 %cmp = icmp slt <2 x i16> %v1, %v2971 ret <2 x i1> %cmp972}973 974define <8 x i1> @test_v8i16_slt(<8 x i16> %v1, <8 x i16> %v2) {975; CHECK-LABEL: test_v8i16_slt:976; CHECK: // %bb.0:977; CHECK-NEXT: cmgt v0.8h, v1.8h, v0.8h978; CHECK-NEXT: xtn v0.8b, v0.8h979; CHECK-NEXT: ret980 %cmp = icmp slt <8 x i16> %v1, %v2981 ret <8 x i1> %cmp982}983 984define <4 x i1> @test_v4i16_slt(<4 x i16> %v1, <4 x i16> %v2) {985; CHECK-LABEL: test_v4i16_slt:986; CHECK: // %bb.0:987; CHECK-NEXT: cmgt v0.4h, v1.4h, v0.4h988; CHECK-NEXT: ret989 %cmp = icmp slt <4 x i16> %v1, %v2990 ret <4 x i1> %cmp991}992 993define <16 x i1> @test_v16i8_slt(<16 x i8> %v1, <16 x i8> %v2) {994; CHECK-LABEL: test_v16i8_slt:995; CHECK: // %bb.0:996; CHECK-NEXT: cmgt v0.16b, v1.16b, v0.16b997; CHECK-NEXT: ret998 %cmp = icmp slt <16 x i8> %v1, %v2999 ret <16 x i1> %cmp1000}1001 1002define <8 x i1> @test_v8i8_slt(<8 x i8> %v1, <8 x i8> %v2) {1003; CHECK-LABEL: test_v8i8_slt:1004; CHECK: // %bb.0:1005; CHECK-NEXT: cmgt v0.8b, v1.8b, v0.8b1006; CHECK-NEXT: ret1007 %cmp = icmp slt <8 x i8> %v1, %v21008 ret <8 x i1> %cmp1009}1010 1011define <2 x i1> @test_v2i64_sle(<2 x i64> %v1, <2 x i64> %v2) {1012; CHECK-LABEL: test_v2i64_sle:1013; CHECK: // %bb.0:1014; CHECK-NEXT: cmge v0.2d, v1.2d, v0.2d1015; CHECK-NEXT: xtn v0.2s, v0.2d1016; CHECK-NEXT: ret1017 %cmp = icmp sle <2 x i64> %v1, %v21018 ret <2 x i1> %cmp1019}1020 1021define <4 x i1> @test_v4i64_sle(<4 x i64> %v1, <4 x i64> %v2) {1022; CHECK-SD-LABEL: test_v4i64_sle:1023; CHECK-SD: // %bb.0: // %entry1024; CHECK-SD-NEXT: cmge v1.2d, v3.2d, v1.2d1025; CHECK-SD-NEXT: cmge v0.2d, v2.2d, v0.2d1026; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s1027; CHECK-SD-NEXT: xtn v0.4h, v0.4s1028; CHECK-SD-NEXT: ret1029;1030; CHECK-GI-LABEL: test_v4i64_sle:1031; CHECK-GI: // %bb.0: // %entry1032; CHECK-GI-NEXT: cmge v0.2d, v2.2d, v0.2d1033; CHECK-GI-NEXT: cmge v1.2d, v3.2d, v1.2d1034; CHECK-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s1035; CHECK-GI-NEXT: xtn v0.4h, v0.4s1036; CHECK-GI-NEXT: ret1037entry:1038 %cmp = icmp sle <4 x i64> %v1, %v21039 ret <4 x i1> %cmp1040}1041 1042define <4 x i1> @test_v4i32_sle(<4 x i32> %v1, <4 x i32> %v2) {1043; CHECK-LABEL: test_v4i32_sle:1044; CHECK: // %bb.0:1045; CHECK-NEXT: cmge v0.4s, v1.4s, v0.4s1046; CHECK-NEXT: xtn v0.4h, v0.4s1047; CHECK-NEXT: ret1048 %cmp = icmp sle <4 x i32> %v1, %v21049 ret <4 x i1> %cmp1050}1051 1052define <2 x i1> @test_v2i32_sle(<2 x i32> %v1, <2 x i32> %v2) {1053; CHECK-LABEL: test_v2i32_sle:1054; CHECK: // %bb.0:1055; CHECK-NEXT: cmge v0.2s, v1.2s, v0.2s1056; CHECK-NEXT: ret1057 %cmp = icmp sle <2 x i32> %v1, %v21058 ret <2 x i1> %cmp1059}1060 1061define <2 x i1> @test_v2i16_sle(<2 x i16> %v1, <2 x i16> %v2) {1062; CHECK-LABEL: test_v2i16_sle:1063; CHECK: // %bb.0:1064; CHECK-NEXT: shl v0.2s, v0.2s, #161065; CHECK-NEXT: shl v1.2s, v1.2s, #161066; CHECK-NEXT: sshr v0.2s, v0.2s, #161067; CHECK-NEXT: sshr v1.2s, v1.2s, #161068; CHECK-NEXT: cmge v0.2s, v1.2s, v0.2s1069; CHECK-NEXT: ret1070 %cmp = icmp sle <2 x i16> %v1, %v21071 ret <2 x i1> %cmp1072}1073 1074define <8 x i1> @test_v8i16_sle(<8 x i16> %v1, <8 x i16> %v2) {1075; CHECK-LABEL: test_v8i16_sle:1076; CHECK: // %bb.0:1077; CHECK-NEXT: cmge v0.8h, v1.8h, v0.8h1078; CHECK-NEXT: xtn v0.8b, v0.8h1079; CHECK-NEXT: ret1080 %cmp = icmp sle <8 x i16> %v1, %v21081 ret <8 x i1> %cmp1082}1083 1084define <4 x i1> @test_v4i16_sle(<4 x i16> %v1, <4 x i16> %v2) {1085; CHECK-LABEL: test_v4i16_sle:1086; CHECK: // %bb.0:1087; CHECK-NEXT: cmge v0.4h, v1.4h, v0.4h1088; CHECK-NEXT: ret1089 %cmp = icmp sle <4 x i16> %v1, %v21090 ret <4 x i1> %cmp1091}1092 1093define <16 x i1> @test_v16i8_sle(<16 x i8> %v1, <16 x i8> %v2) {1094; CHECK-LABEL: test_v16i8_sle:1095; CHECK: // %bb.0:1096; CHECK-NEXT: cmge v0.16b, v1.16b, v0.16b1097; CHECK-NEXT: ret1098 %cmp = icmp sle <16 x i8> %v1, %v21099 ret <16 x i1> %cmp1100}1101 1102define <8 x i1> @test_v8i8_sle(<8 x i8> %v1, <8 x i8> %v2) {1103; CHECK-LABEL: test_v8i8_sle:1104; CHECK: // %bb.0:1105; CHECK-NEXT: cmge v0.8b, v1.8b, v0.8b1106; CHECK-NEXT: ret1107 %cmp = icmp sle <8 x i8> %v1, %v21108 ret <8 x i1> %cmp1109}1110 1111define <2 x i64> @v2i64_i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %d, <2 x i64> %e) {1112; CHECK-LABEL: v2i64_i64:1113; CHECK: // %bb.0: // %entry1114; CHECK-NEXT: cmgt v0.2d, v1.2d, v0.2d1115; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b1116; CHECK-NEXT: ret1117entry:1118 %c = icmp slt <2 x i64> %a, %b1119 %s = select <2 x i1> %c, <2 x i64> %d, <2 x i64> %e1120 ret <2 x i64> %s1121}1122 1123define <3 x i64> @v3i64_i64(<3 x i64> %a, <3 x i64> %b, <3 x i64> %d, <3 x i64> %e) {1124; CHECK-SD-LABEL: v3i64_i64:1125; CHECK-SD: // %bb.0: // %entry1126; CHECK-SD-NEXT: // kill: def $d4 killed $d4 def $q41127; CHECK-SD-NEXT: // kill: def $d3 killed $d3 def $q31128; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q11129; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q01130; CHECK-SD-NEXT: // kill: def $d6 killed $d6 def $q61131; CHECK-SD-NEXT: // kill: def $d7 killed $d7 def $q71132; CHECK-SD-NEXT: // kill: def $d5 killed $d5 def $q51133; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q21134; CHECK-SD-NEXT: ldr d16, [sp, #24]1135; CHECK-SD-NEXT: ldr d17, [sp]1136; CHECK-SD-NEXT: mov v3.d[1], v4.d[0]1137; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]1138; CHECK-SD-NEXT: mov v6.d[1], v7.d[0]1139; CHECK-SD-NEXT: ldp d1, d4, [sp, #8]1140; CHECK-SD-NEXT: mov v1.d[1], v4.d[0]1141; CHECK-SD-NEXT: cmgt v0.2d, v3.2d, v0.2d1142; CHECK-SD-NEXT: bsl v0.16b, v6.16b, v1.16b1143; CHECK-SD-NEXT: cmgt v1.2d, v5.2d, v2.2d1144; CHECK-SD-NEXT: mov v2.16b, v1.16b1145; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #81146; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q01147; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q11148; CHECK-SD-NEXT: bsl v2.16b, v17.16b, v16.16b1149; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q21150; CHECK-SD-NEXT: ret1151;1152; CHECK-GI-LABEL: v3i64_i64:1153; CHECK-GI: // %bb.0: // %entry1154; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q01155; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q11156; CHECK-GI-NEXT: // kill: def $d3 killed $d3 def $q31157; CHECK-GI-NEXT: // kill: def $d4 killed $d4 def $q41158; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q21159; CHECK-GI-NEXT: // kill: def $d6 killed $d6 def $q61160; CHECK-GI-NEXT: // kill: def $d5 killed $d5 def $q51161; CHECK-GI-NEXT: // kill: def $d7 killed $d7 def $q71162; CHECK-GI-NEXT: ldr x8, [sp]1163; CHECK-GI-NEXT: ldr x10, [sp, #24]1164; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]1165; CHECK-GI-NEXT: mov v3.d[1], v4.d[0]1166; CHECK-GI-NEXT: cmgt v2.2d, v5.2d, v2.2d1167; CHECK-GI-NEXT: ldp d1, d4, [sp, #8]1168; CHECK-GI-NEXT: mov v6.d[1], v7.d[0]1169; CHECK-GI-NEXT: fmov x9, d21170; CHECK-GI-NEXT: mov v1.d[1], v4.d[0]1171; CHECK-GI-NEXT: cmgt v0.2d, v3.2d, v0.2d1172; CHECK-GI-NEXT: sbfx x9, x9, #0, #11173; CHECK-GI-NEXT: bsl v0.16b, v6.16b, v1.16b1174; CHECK-GI-NEXT: and x8, x8, x91175; CHECK-GI-NEXT: bic x9, x10, x91176; CHECK-GI-NEXT: orr x8, x8, x91177; CHECK-GI-NEXT: fmov d2, x81178; CHECK-GI-NEXT: mov d1, v0.d[1]1179; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q01180; CHECK-GI-NEXT: ret1181entry:1182 %c = icmp slt <3 x i64> %a, %b1183 %s = select <3 x i1> %c, <3 x i64> %d, <3 x i64> %e1184 ret <3 x i64> %s1185}1186 1187define <4 x i64> @v4i64_i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %d, <4 x i64> %e) {1188; CHECK-SD-LABEL: v4i64_i64:1189; CHECK-SD: // %bb.0: // %entry1190; CHECK-SD-NEXT: cmgt v1.2d, v3.2d, v1.2d1191; CHECK-SD-NEXT: cmgt v0.2d, v2.2d, v0.2d1192; CHECK-SD-NEXT: bsl v1.16b, v5.16b, v7.16b1193; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v6.16b1194; CHECK-SD-NEXT: ret1195;1196; CHECK-GI-LABEL: v4i64_i64:1197; CHECK-GI: // %bb.0: // %entry1198; CHECK-GI-NEXT: cmgt v0.2d, v2.2d, v0.2d1199; CHECK-GI-NEXT: cmgt v1.2d, v3.2d, v1.2d1200; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v6.16b1201; CHECK-GI-NEXT: bsl v1.16b, v5.16b, v7.16b1202; CHECK-GI-NEXT: ret1203entry:1204 %c = icmp slt <4 x i64> %a, %b1205 %s = select <4 x i1> %c, <4 x i64> %d, <4 x i64> %e1206 ret <4 x i64> %s1207}1208 1209define <2 x i32> @v2i32_i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %d, <2 x i32> %e) {1210; CHECK-LABEL: v2i32_i32:1211; CHECK: // %bb.0: // %entry1212; CHECK-NEXT: cmgt v0.2s, v1.2s, v0.2s1213; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b1214; CHECK-NEXT: ret1215entry:1216 %c = icmp slt <2 x i32> %a, %b1217 %s = select <2 x i1> %c, <2 x i32> %d, <2 x i32> %e1218 ret <2 x i32> %s1219}1220 1221define <3 x i32> @v3i32_i32(<3 x i32> %a, <3 x i32> %b, <3 x i32> %d, <3 x i32> %e) {1222; CHECK-SD-LABEL: v3i32_i32:1223; CHECK-SD: // %bb.0: // %entry1224; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s1225; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b1226; CHECK-SD-NEXT: ret1227;1228; CHECK-GI-LABEL: v3i32_i32:1229; CHECK-GI: // %bb.0: // %entry1230; CHECK-GI-NEXT: mov w8, #31 // =0x1f1231; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s1232; CHECK-GI-NEXT: fmov s4, w81233; CHECK-GI-NEXT: mov v4.s[1], w81234; CHECK-GI-NEXT: mov v4.s[2], w81235; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff1236; CHECK-GI-NEXT: fmov s1, w81237; CHECK-GI-NEXT: mov v1.s[1], w81238; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v4.4s1239; CHECK-GI-NEXT: neg v4.4s, v4.4s1240; CHECK-GI-NEXT: sshl v0.4s, v0.4s, v4.4s1241; CHECK-GI-NEXT: mov v1.s[2], w81242; CHECK-GI-NEXT: eor v1.16b, v0.16b, v1.16b1243; CHECK-GI-NEXT: and v0.16b, v2.16b, v0.16b1244; CHECK-GI-NEXT: and v1.16b, v3.16b, v1.16b1245; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b1246; CHECK-GI-NEXT: ret1247entry:1248 %c = icmp slt <3 x i32> %a, %b1249 %s = select <3 x i1> %c, <3 x i32> %d, <3 x i32> %e1250 ret <3 x i32> %s1251}1252 1253define <4 x i32> @v4i32_i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %d, <4 x i32> %e) {1254; CHECK-LABEL: v4i32_i32:1255; CHECK: // %bb.0: // %entry1256; CHECK-NEXT: cmgt v0.4s, v1.4s, v0.4s1257; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b1258; CHECK-NEXT: ret1259entry:1260 %c = icmp slt <4 x i32> %a, %b1261 %s = select <4 x i1> %c, <4 x i32> %d, <4 x i32> %e1262 ret <4 x i32> %s1263}1264 1265define <8 x i32> @v8i32_i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %d, <8 x i32> %e) {1266; CHECK-SD-LABEL: v8i32_i32:1267; CHECK-SD: // %bb.0: // %entry1268; CHECK-SD-NEXT: cmgt v1.4s, v3.4s, v1.4s1269; CHECK-SD-NEXT: cmgt v0.4s, v2.4s, v0.4s1270; CHECK-SD-NEXT: bsl v1.16b, v5.16b, v7.16b1271; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v6.16b1272; CHECK-SD-NEXT: ret1273;1274; CHECK-GI-LABEL: v8i32_i32:1275; CHECK-GI: // %bb.0: // %entry1276; CHECK-GI-NEXT: cmgt v0.4s, v2.4s, v0.4s1277; CHECK-GI-NEXT: cmgt v1.4s, v3.4s, v1.4s1278; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v6.16b1279; CHECK-GI-NEXT: bsl v1.16b, v5.16b, v7.16b1280; CHECK-GI-NEXT: ret1281entry:1282 %c = icmp slt <8 x i32> %a, %b1283 %s = select <8 x i1> %c, <8 x i32> %d, <8 x i32> %e1284 ret <8 x i32> %s1285}1286 1287define <4 x i16> @v4i16_i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %d, <4 x i16> %e) {1288; CHECK-LABEL: v4i16_i16:1289; CHECK: // %bb.0: // %entry1290; CHECK-NEXT: cmgt v0.4h, v1.4h, v0.4h1291; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b1292; CHECK-NEXT: ret1293entry:1294 %c = icmp slt <4 x i16> %a, %b1295 %s = select <4 x i1> %c, <4 x i16> %d, <4 x i16> %e1296 ret <4 x i16> %s1297}1298 1299define <8 x i16> @v8i16_i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %d, <8 x i16> %e) {1300; CHECK-LABEL: v8i16_i16:1301; CHECK: // %bb.0: // %entry1302; CHECK-NEXT: cmgt v0.8h, v1.8h, v0.8h1303; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b1304; CHECK-NEXT: ret1305entry:1306 %c = icmp slt <8 x i16> %a, %b1307 %s = select <8 x i1> %c, <8 x i16> %d, <8 x i16> %e1308 ret <8 x i16> %s1309}1310 1311define <16 x i16> @v16i16_i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %d, <16 x i16> %e) {1312; CHECK-SD-LABEL: v16i16_i16:1313; CHECK-SD: // %bb.0: // %entry1314; CHECK-SD-NEXT: cmgt v1.8h, v3.8h, v1.8h1315; CHECK-SD-NEXT: cmgt v0.8h, v2.8h, v0.8h1316; CHECK-SD-NEXT: bsl v1.16b, v5.16b, v7.16b1317; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v6.16b1318; CHECK-SD-NEXT: ret1319;1320; CHECK-GI-LABEL: v16i16_i16:1321; CHECK-GI: // %bb.0: // %entry1322; CHECK-GI-NEXT: cmgt v0.8h, v2.8h, v0.8h1323; CHECK-GI-NEXT: cmgt v1.8h, v3.8h, v1.8h1324; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v6.16b1325; CHECK-GI-NEXT: bsl v1.16b, v5.16b, v7.16b1326; CHECK-GI-NEXT: ret1327entry:1328 %c = icmp slt <16 x i16> %a, %b1329 %s = select <16 x i1> %c, <16 x i16> %d, <16 x i16> %e1330 ret <16 x i16> %s1331}1332 1333define <8 x i8> @v8i8_i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %d, <8 x i8> %e) {1334; CHECK-LABEL: v8i8_i8:1335; CHECK: // %bb.0: // %entry1336; CHECK-NEXT: cmgt v0.8b, v1.8b, v0.8b1337; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b1338; CHECK-NEXT: ret1339entry:1340 %c = icmp slt <8 x i8> %a, %b1341 %s = select <8 x i1> %c, <8 x i8> %d, <8 x i8> %e1342 ret <8 x i8> %s1343}1344 1345define <16 x i8> @v16i8_i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %d, <16 x i8> %e) {1346; CHECK-LABEL: v16i8_i8:1347; CHECK: // %bb.0: // %entry1348; CHECK-NEXT: cmgt v0.16b, v1.16b, v0.16b1349; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b1350; CHECK-NEXT: ret1351entry:1352 %c = icmp slt <16 x i8> %a, %b1353 %s = select <16 x i1> %c, <16 x i8> %d, <16 x i8> %e1354 ret <16 x i8> %s1355}1356 1357define <32 x i8> @v32i8_i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %d, <32 x i8> %e) {1358; CHECK-SD-LABEL: v32i8_i8:1359; CHECK-SD: // %bb.0: // %entry1360; CHECK-SD-NEXT: cmgt v1.16b, v3.16b, v1.16b1361; CHECK-SD-NEXT: cmgt v0.16b, v2.16b, v0.16b1362; CHECK-SD-NEXT: bsl v1.16b, v5.16b, v7.16b1363; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v6.16b1364; CHECK-SD-NEXT: ret1365;1366; CHECK-GI-LABEL: v32i8_i8:1367; CHECK-GI: // %bb.0: // %entry1368; CHECK-GI-NEXT: cmgt v0.16b, v2.16b, v0.16b1369; CHECK-GI-NEXT: cmgt v1.16b, v3.16b, v1.16b1370; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v6.16b1371; CHECK-GI-NEXT: bsl v1.16b, v5.16b, v7.16b1372; CHECK-GI-NEXT: ret1373entry:1374 %c = icmp slt <32 x i8> %a, %b1375 %s = select <32 x i1> %c, <32 x i8> %d, <32 x i8> %e1376 ret <32 x i8> %s1377}1378 1379define <2 x i128> @v2i128_i128(<2 x i128> %a, <2 x i128> %b, <2 x i128> %d, <2 x i128> %e) {1380; CHECK-SD-LABEL: v2i128_i128:1381; CHECK-SD: // %bb.0: // %entry1382; CHECK-SD-NEXT: add x10, sp, #321383; CHECK-SD-NEXT: mov x11, sp1384; CHECK-SD-NEXT: cmp x0, x41385; CHECK-SD-NEXT: orr x12, x10, #0x81386; CHECK-SD-NEXT: orr x13, x11, #0x81387; CHECK-SD-NEXT: sbcs xzr, x1, x51388; CHECK-SD-NEXT: add x8, sp, #481389; CHECK-SD-NEXT: add x9, sp, #161390; CHECK-SD-NEXT: csel x12, x13, x12, lt1391; CHECK-SD-NEXT: csel x10, x11, x10, lt1392; CHECK-SD-NEXT: cmp x2, x61393; CHECK-SD-NEXT: orr x11, x8, #0x81394; CHECK-SD-NEXT: orr x13, x9, #0x81395; CHECK-SD-NEXT: sbcs xzr, x3, x71396; CHECK-SD-NEXT: ldr x0, [x10]1397; CHECK-SD-NEXT: csel x8, x9, x8, lt1398; CHECK-SD-NEXT: csel x9, x13, x11, lt1399; CHECK-SD-NEXT: ldr x1, [x12]1400; CHECK-SD-NEXT: ldr x2, [x8]1401; CHECK-SD-NEXT: ldr x3, [x9]1402; CHECK-SD-NEXT: ret1403;1404; CHECK-GI-LABEL: v2i128_i128:1405; CHECK-GI: // %bb.0: // %entry1406; CHECK-GI-NEXT: cmp x0, x41407; CHECK-GI-NEXT: ldp x9, x10, [sp]1408; CHECK-GI-NEXT: cset w8, lo1409; CHECK-GI-NEXT: cmp x1, x51410; CHECK-GI-NEXT: cset w11, lt1411; CHECK-GI-NEXT: ldp x14, x15, [sp, #32]1412; CHECK-GI-NEXT: csel w8, w8, w11, eq1413; CHECK-GI-NEXT: cmp x2, x61414; CHECK-GI-NEXT: cset w11, lo1415; CHECK-GI-NEXT: cmp x3, x71416; CHECK-GI-NEXT: ldp x12, x13, [sp, #16]1417; CHECK-GI-NEXT: cset w16, lt1418; CHECK-GI-NEXT: ldp x17, x18, [sp, #48]1419; CHECK-GI-NEXT: csel w11, w11, w16, eq1420; CHECK-GI-NEXT: tst w8, #0x11421; CHECK-GI-NEXT: csel x0, x9, x14, ne1422; CHECK-GI-NEXT: csel x1, x10, x15, ne1423; CHECK-GI-NEXT: tst w11, #0x11424; CHECK-GI-NEXT: csel x2, x12, x17, ne1425; CHECK-GI-NEXT: csel x3, x13, x18, ne1426; CHECK-GI-NEXT: ret1427entry:1428 %c = icmp slt <2 x i128> %a, %b1429 %s = select <2 x i1> %c, <2 x i128> %d, <2 x i128> %e1430 ret <2 x i128> %s1431}1432 1433; ===== ICMP Zero RHS =====1434 1435define <8 x i1> @icmp_eq_v8i8_Zero_RHS(<8 x i8> %a) {1436; CHECK-LABEL: icmp_eq_v8i8_Zero_RHS:1437; CHECK: // %bb.0:1438; CHECK-NEXT: cmeq v0.8b, v0.8b, #01439; CHECK-NEXT: ret1440 %c = icmp eq <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>1441 ret <8 x i1> %c1442}1443 1444define <16 x i1> @icmp_eq_v16i8_Zero_RHS(<16 x i8> %a) {1445; CHECK-LABEL: icmp_eq_v16i8_Zero_RHS:1446; CHECK: // %bb.0:1447; CHECK-NEXT: cmeq v0.16b, v0.16b, #01448; CHECK-NEXT: ret1449 %c = icmp eq <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>1450 ret <16 x i1> %c1451}1452 1453define <4 x i1> @icmp_eq_v4i16_Zero_RHS(<4 x i16> %a) {1454; CHECK-LABEL: icmp_eq_v4i16_Zero_RHS:1455; CHECK: // %bb.0:1456; CHECK-NEXT: cmeq v0.4h, v0.4h, #01457; CHECK-NEXT: ret1458 %c = icmp eq <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>1459 ret <4 x i1> %c1460}1461 1462define <8 x i1> @icmp_eq_v8i16_Zero_RHS(<8 x i16> %a) {1463; CHECK-LABEL: icmp_eq_v8i16_Zero_RHS:1464; CHECK: // %bb.0:1465; CHECK-NEXT: cmeq v0.8h, v0.8h, #01466; CHECK-NEXT: xtn v0.8b, v0.8h1467; CHECK-NEXT: ret1468 %c = icmp eq <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>1469 ret <8 x i1> %c1470}1471 1472define <2 x i1> @icmp_eq_v2i32_Zero_RHS(<2 x i32> %a) {1473; CHECK-LABEL: icmp_eq_v2i32_Zero_RHS:1474; CHECK: // %bb.0:1475; CHECK-NEXT: cmeq v0.2s, v0.2s, #01476; CHECK-NEXT: ret1477 %c = icmp eq <2 x i32> %a, <i32 0, i32 0>1478 ret <2 x i1> %c1479}1480 1481define <4 x i1> @icmp_eq_v4i32_Zero_RHS(<4 x i32> %a) {1482; CHECK-LABEL: icmp_eq_v4i32_Zero_RHS:1483; CHECK: // %bb.0:1484; CHECK-NEXT: cmeq v0.4s, v0.4s, #01485; CHECK-NEXT: xtn v0.4h, v0.4s1486; CHECK-NEXT: ret1487 %c = icmp eq <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>1488 ret <4 x i1> %c1489}1490 1491define <2 x i1> @icmp_eq_v2i64_Zero_RHS(<2 x i64> %a) {1492; CHECK-LABEL: icmp_eq_v2i64_Zero_RHS:1493; CHECK: // %bb.0:1494; CHECK-NEXT: cmeq v0.2d, v0.2d, #01495; CHECK-NEXT: xtn v0.2s, v0.2d1496; CHECK-NEXT: ret1497 %c = icmp eq <2 x i64> %a, <i64 0, i64 0>1498 ret <2 x i1> %c1499}1500 1501define <8 x i1> @icmp_sge_v8i8_Zero_RHS(<8 x i8> %a) {1502; CHECK-LABEL: icmp_sge_v8i8_Zero_RHS:1503; CHECK: // %bb.0:1504; CHECK-NEXT: cmge v0.8b, v0.8b, #01505; CHECK-NEXT: ret1506 %c = icmp sge <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>1507 ret <8 x i1> %c1508}1509 1510define <16 x i1> @icmp_sge_v16i8_Zero_RHS(<16 x i8> %a) {1511; CHECK-LABEL: icmp_sge_v16i8_Zero_RHS:1512; CHECK: // %bb.0:1513; CHECK-NEXT: cmge v0.16b, v0.16b, #01514; CHECK-NEXT: ret1515 %c = icmp sge <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>1516 ret <16 x i1> %c1517}1518 1519define <4 x i1> @icmp_sge_v4i16_Zero_RHS(<4 x i16> %a) {1520; CHECK-LABEL: icmp_sge_v4i16_Zero_RHS:1521; CHECK: // %bb.0:1522; CHECK-NEXT: cmge v0.4h, v0.4h, #01523; CHECK-NEXT: ret1524 %c = icmp sge <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>1525 ret <4 x i1> %c1526}1527 1528define <8 x i1> @icmp_sge_v8i16_Zero_RHS(<8 x i16> %a) {1529; CHECK-LABEL: icmp_sge_v8i16_Zero_RHS:1530; CHECK: // %bb.0:1531; CHECK-NEXT: cmge v0.8h, v0.8h, #01532; CHECK-NEXT: xtn v0.8b, v0.8h1533; CHECK-NEXT: ret1534 %c = icmp sge <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>1535 ret <8 x i1> %c1536}1537 1538define <2 x i1> @icmp_sge_v2i32_Zero_RHS(<2 x i32> %a) {1539; CHECK-LABEL: icmp_sge_v2i32_Zero_RHS:1540; CHECK: // %bb.0:1541; CHECK-NEXT: cmge v0.2s, v0.2s, #01542; CHECK-NEXT: ret1543 %c = icmp sge <2 x i32> %a, <i32 0, i32 0>1544 ret <2 x i1> %c1545}1546 1547define <4 x i1> @icmp_sge_v4i32_Zero_RHS(<4 x i32> %a) {1548; CHECK-LABEL: icmp_sge_v4i32_Zero_RHS:1549; CHECK: // %bb.0:1550; CHECK-NEXT: cmge v0.4s, v0.4s, #01551; CHECK-NEXT: xtn v0.4h, v0.4s1552; CHECK-NEXT: ret1553 %c = icmp sge <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>1554 ret <4 x i1> %c1555}1556 1557define <2 x i1> @icmp_sge_v2i64_Zero_RHS(<2 x i64> %a) {1558; CHECK-LABEL: icmp_sge_v2i64_Zero_RHS:1559; CHECK: // %bb.0:1560; CHECK-NEXT: cmge v0.2d, v0.2d, #01561; CHECK-NEXT: xtn v0.2s, v0.2d1562; CHECK-NEXT: ret1563 %c = icmp sge <2 x i64> %a, <i64 0, i64 0>1564 ret <2 x i1> %c1565}1566 1567define <8 x i1> @icmp_sgt_v8i8_Zero_RHS(<8 x i8> %a) {1568; CHECK-LABEL: icmp_sgt_v8i8_Zero_RHS:1569; CHECK: // %bb.0:1570; CHECK-NEXT: cmgt v0.8b, v0.8b, #01571; CHECK-NEXT: ret1572 %c = icmp sgt <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>1573 ret <8 x i1> %c1574}1575 1576define <16 x i1> @icmp_sgt_v16i8_Zero_RHS(<16 x i8> %a) {1577; CHECK-LABEL: icmp_sgt_v16i8_Zero_RHS:1578; CHECK: // %bb.0:1579; CHECK-NEXT: cmgt v0.16b, v0.16b, #01580; CHECK-NEXT: ret1581 %c = icmp sgt <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>1582 ret <16 x i1> %c1583}1584 1585define <4 x i1> @icmp_sgt_v4i16_Zero_RHS(<4 x i16> %a) {1586; CHECK-LABEL: icmp_sgt_v4i16_Zero_RHS:1587; CHECK: // %bb.0:1588; CHECK-NEXT: cmgt v0.4h, v0.4h, #01589; CHECK-NEXT: ret1590 %c = icmp sgt <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>1591 ret <4 x i1> %c1592}1593 1594define <8 x i1> @icmp_sgt_v8i16_Zero_RHS(<8 x i16> %a) {1595; CHECK-LABEL: icmp_sgt_v8i16_Zero_RHS:1596; CHECK: // %bb.0:1597; CHECK-NEXT: cmgt v0.8h, v0.8h, #01598; CHECK-NEXT: xtn v0.8b, v0.8h1599; CHECK-NEXT: ret1600 %c = icmp sgt <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>1601 ret <8 x i1> %c1602}1603 1604define <2 x i1> @icmp_sgt_v2i32_Zero_RHS(<2 x i32> %a) {1605; CHECK-LABEL: icmp_sgt_v2i32_Zero_RHS:1606; CHECK: // %bb.0:1607; CHECK-NEXT: cmgt v0.2s, v0.2s, #01608; CHECK-NEXT: ret1609 %c = icmp sgt <2 x i32> %a, <i32 0, i32 0>1610 ret <2 x i1> %c1611}1612 1613define <4 x i1> @icmp_sgt_v4i32_Zero_RHS(<4 x i32> %a) {1614; CHECK-LABEL: icmp_sgt_v4i32_Zero_RHS:1615; CHECK: // %bb.0:1616; CHECK-NEXT: cmgt v0.4s, v0.4s, #01617; CHECK-NEXT: xtn v0.4h, v0.4s1618; CHECK-NEXT: ret1619 %c = icmp sgt <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>1620 ret <4 x i1> %c1621}1622 1623define <2 x i1> @icmp_sgt_v2i64_Zero_RHS(<2 x i64> %a) {1624; CHECK-LABEL: icmp_sgt_v2i64_Zero_RHS:1625; CHECK: // %bb.0:1626; CHECK-NEXT: cmgt v0.2d, v0.2d, #01627; CHECK-NEXT: xtn v0.2s, v0.2d1628; CHECK-NEXT: ret1629 %c = icmp sgt <2 x i64> %a, <i64 0, i64 0>1630 ret <2 x i1> %c1631}1632 1633define <8 x i1> @icmp_sle_v8i8_Zero_RHS(<8 x i8> %a) {1634; CHECK-LABEL: icmp_sle_v8i8_Zero_RHS:1635; CHECK: // %bb.0:1636; CHECK-NEXT: cmle v0.8b, v0.8b, #01637; CHECK-NEXT: ret1638 %c = icmp sle <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>1639 ret <8 x i1> %c1640}1641 1642define <16 x i1> @icmp_sle_v16i8_Zero_RHS(<16 x i8> %a) {1643; CHECK-LABEL: icmp_sle_v16i8_Zero_RHS:1644; CHECK: // %bb.0:1645; CHECK-NEXT: cmle v0.16b, v0.16b, #01646; CHECK-NEXT: ret1647 %c = icmp sle <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>1648 ret <16 x i1> %c1649}1650 1651define <4 x i1> @icmp_sle_v4i16_Zero_RHS(<4 x i16> %a) {1652; CHECK-LABEL: icmp_sle_v4i16_Zero_RHS:1653; CHECK: // %bb.0:1654; CHECK-NEXT: cmle v0.4h, v0.4h, #01655; CHECK-NEXT: ret1656 %c = icmp sle <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>1657 ret <4 x i1> %c1658}1659 1660define <8 x i1> @icmp_sle_v8i16_Zero_RHS(<8 x i16> %a) {1661; CHECK-LABEL: icmp_sle_v8i16_Zero_RHS:1662; CHECK: // %bb.0:1663; CHECK-NEXT: cmle v0.8h, v0.8h, #01664; CHECK-NEXT: xtn v0.8b, v0.8h1665; CHECK-NEXT: ret1666 %c = icmp sle <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>1667 ret <8 x i1> %c1668}1669 1670define <2 x i1> @icmp_sle_v2i32_Zero_RHS(<2 x i32> %a) {1671; CHECK-LABEL: icmp_sle_v2i32_Zero_RHS:1672; CHECK: // %bb.0:1673; CHECK-NEXT: cmle v0.2s, v0.2s, #01674; CHECK-NEXT: ret1675 %c = icmp sle <2 x i32> %a, <i32 0, i32 0>1676 ret <2 x i1> %c1677}1678 1679define <4 x i1> @icmp_sle_v4i32_Zero_RHS(<4 x i32> %a) {1680; CHECK-LABEL: icmp_sle_v4i32_Zero_RHS:1681; CHECK: // %bb.0:1682; CHECK-NEXT: cmle v0.4s, v0.4s, #01683; CHECK-NEXT: xtn v0.4h, v0.4s1684; CHECK-NEXT: ret1685 %c = icmp sle <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>1686 ret <4 x i1> %c1687}1688 1689define <2 x i1> @icmp_sle_v2i64_Zero_RHS(<2 x i64> %a) {1690; CHECK-LABEL: icmp_sle_v2i64_Zero_RHS:1691; CHECK: // %bb.0:1692; CHECK-NEXT: cmle v0.2d, v0.2d, #01693; CHECK-NEXT: xtn v0.2s, v0.2d1694; CHECK-NEXT: ret1695 %c = icmp sle <2 x i64> %a, <i64 0, i64 0>1696 ret <2 x i1> %c1697}1698 1699define <8 x i1> @icmp_slt_v8i8_Zero_RHS(<8 x i8> %a) {1700; CHECK-LABEL: icmp_slt_v8i8_Zero_RHS:1701; CHECK: // %bb.0:1702; CHECK-NEXT: cmlt v0.8b, v0.8b, #01703; CHECK-NEXT: ret1704 %c = icmp slt <8 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>1705 ret <8 x i1> %c1706}1707 1708define <16 x i1> @icmp_slt_v16i8_Zero_RHS(<16 x i8> %a) {1709; CHECK-LABEL: icmp_slt_v16i8_Zero_RHS:1710; CHECK: // %bb.0:1711; CHECK-NEXT: cmlt v0.16b, v0.16b, #01712; CHECK-NEXT: ret1713 %c = icmp slt <16 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>1714 ret <16 x i1> %c1715}1716 1717define <4 x i1> @icmp_slt_v4i16_Zero_RHS(<4 x i16> %a) {1718; CHECK-LABEL: icmp_slt_v4i16_Zero_RHS:1719; CHECK: // %bb.0:1720; CHECK-NEXT: cmlt v0.4h, v0.4h, #01721; CHECK-NEXT: ret1722 %c = icmp slt <4 x i16> %a, <i16 0, i16 0, i16 0, i16 0>1723 ret <4 x i1> %c1724}1725 1726define <8 x i1> @icmp_slt_v8i16_Zero_RHS(<8 x i16> %a) {1727; CHECK-LABEL: icmp_slt_v8i16_Zero_RHS:1728; CHECK: // %bb.0:1729; CHECK-NEXT: cmlt v0.8h, v0.8h, #01730; CHECK-NEXT: xtn v0.8b, v0.8h1731; CHECK-NEXT: ret1732 %c = icmp slt <8 x i16> %a, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>1733 ret <8 x i1> %c1734}1735 1736define <2 x i1> @icmp_slt_v2i32_Zero_RHS(<2 x i32> %a) {1737; CHECK-LABEL: icmp_slt_v2i32_Zero_RHS:1738; CHECK: // %bb.0:1739; CHECK-NEXT: cmlt v0.2s, v0.2s, #01740; CHECK-NEXT: ret1741 %c = icmp slt <2 x i32> %a, <i32 0, i32 0>1742 ret <2 x i1> %c1743}1744 1745define <4 x i1> @icmp_slt_v4i32_Zero_RHS(<4 x i32> %a) {1746; CHECK-LABEL: icmp_slt_v4i32_Zero_RHS:1747; CHECK: // %bb.0:1748; CHECK-NEXT: cmlt v0.4s, v0.4s, #01749; CHECK-NEXT: xtn v0.4h, v0.4s1750; CHECK-NEXT: ret1751 %c = icmp slt <4 x i32> %a, <i32 0, i32 0, i32 0, i32 0>1752 ret <4 x i1> %c1753}1754 1755define <2 x i1> @icmp_slt_v2i64_Zero_RHS(<2 x i64> %a) {1756; CHECK-LABEL: icmp_slt_v2i64_Zero_RHS:1757; CHECK: // %bb.0:1758; CHECK-NEXT: cmlt v0.2d, v0.2d, #01759; CHECK-NEXT: xtn v0.2s, v0.2d1760; CHECK-NEXT: ret1761 %c = icmp slt <2 x i64> %a, <i64 0, i64 0>1762 ret <2 x i1> %c1763}1764 1765; ===== ICMP Zero LHS =====1766 1767define <8 x i1> @icmp_eq_v8i8_Zero_LHS(<8 x i8> %a) {1768; CHECK-LABEL: icmp_eq_v8i8_Zero_LHS:1769; CHECK: // %bb.0:1770; CHECK-NEXT: cmeq v0.8b, v0.8b, #01771; CHECK-NEXT: ret1772 %c = icmp eq <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a1773 ret <8 x i1> %c1774}1775 1776define <16 x i1> @icmp_eq_v16i8_Zero_LHS(<16 x i8> %a) {1777; CHECK-LABEL: icmp_eq_v16i8_Zero_LHS:1778; CHECK: // %bb.0:1779; CHECK-NEXT: cmeq v0.16b, v0.16b, #01780; CHECK-NEXT: ret1781 %c = icmp eq <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a1782 ret <16 x i1> %c1783}1784 1785define <4 x i1> @icmp_eq_v4i16_Zero_LHS(<4 x i16> %a) {1786; CHECK-LABEL: icmp_eq_v4i16_Zero_LHS:1787; CHECK: // %bb.0:1788; CHECK-NEXT: cmeq v0.4h, v0.4h, #01789; CHECK-NEXT: ret1790 %c = icmp eq <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a1791 ret <4 x i1> %c1792}1793 1794define <8 x i1> @icmp_eq_v8i16_Zero_LHS(<8 x i16> %a) {1795; CHECK-LABEL: icmp_eq_v8i16_Zero_LHS:1796; CHECK: // %bb.0:1797; CHECK-NEXT: cmeq v0.8h, v0.8h, #01798; CHECK-NEXT: xtn v0.8b, v0.8h1799; CHECK-NEXT: ret1800 %c = icmp eq <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a1801 ret <8 x i1> %c1802}1803 1804define <2 x i1> @icmp_eq_v2i32_Zero_LHS(<2 x i32> %a) {1805; CHECK-LABEL: icmp_eq_v2i32_Zero_LHS:1806; CHECK: // %bb.0:1807; CHECK-NEXT: cmeq v0.2s, v0.2s, #01808; CHECK-NEXT: ret1809 %c = icmp eq <2 x i32> <i32 0, i32 0>, %a1810 ret <2 x i1> %c1811}1812 1813define <4 x i1> @icmp_eq_v4i32_Zero_LHS(<4 x i32> %a) {1814; CHECK-LABEL: icmp_eq_v4i32_Zero_LHS:1815; CHECK: // %bb.0:1816; CHECK-NEXT: cmeq v0.4s, v0.4s, #01817; CHECK-NEXT: xtn v0.4h, v0.4s1818; CHECK-NEXT: ret1819 %c = icmp eq <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a1820 ret <4 x i1> %c1821}1822 1823define <2 x i1> @icmp_eq_v2i64_Zero_LHS(<2 x i64> %a) {1824; CHECK-LABEL: icmp_eq_v2i64_Zero_LHS:1825; CHECK: // %bb.0:1826; CHECK-NEXT: cmeq v0.2d, v0.2d, #01827; CHECK-NEXT: xtn v0.2s, v0.2d1828; CHECK-NEXT: ret1829 %c = icmp eq <2 x i64> <i64 0, i64 0>, %a1830 ret <2 x i1> %c1831}1832 1833define <8 x i1> @icmp_sge_v8i8_Zero_LHS(<8 x i8> %a) {1834; CHECK-LABEL: icmp_sge_v8i8_Zero_LHS:1835; CHECK: // %bb.0:1836; CHECK-NEXT: cmle v0.8b, v0.8b, #01837; CHECK-NEXT: ret1838 %c = icmp sge <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a1839 ret <8 x i1> %c1840}1841 1842define <16 x i1> @icmp_sge_v16i8_Zero_LHS(<16 x i8> %a) {1843; CHECK-LABEL: icmp_sge_v16i8_Zero_LHS:1844; CHECK: // %bb.0:1845; CHECK-NEXT: cmle v0.16b, v0.16b, #01846; CHECK-NEXT: ret1847 %c = icmp sge <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a1848 ret <16 x i1> %c1849}1850 1851define <4 x i1> @icmp_sge_v4i16_Zero_LHS(<4 x i16> %a) {1852; CHECK-LABEL: icmp_sge_v4i16_Zero_LHS:1853; CHECK: // %bb.0:1854; CHECK-NEXT: cmle v0.4h, v0.4h, #01855; CHECK-NEXT: ret1856 %c = icmp sge <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a1857 ret <4 x i1> %c1858}1859 1860define <8 x i1> @icmp_sge_v8i16_Zero_LHS(<8 x i16> %a) {1861; CHECK-LABEL: icmp_sge_v8i16_Zero_LHS:1862; CHECK: // %bb.0:1863; CHECK-NEXT: cmle v0.8h, v0.8h, #01864; CHECK-NEXT: xtn v0.8b, v0.8h1865; CHECK-NEXT: ret1866 %c = icmp sge <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a1867 ret <8 x i1> %c1868}1869 1870define <2 x i1> @icmp_sge_v2i32_Zero_LHS(<2 x i32> %a) {1871; CHECK-LABEL: icmp_sge_v2i32_Zero_LHS:1872; CHECK: // %bb.0:1873; CHECK-NEXT: cmle v0.2s, v0.2s, #01874; CHECK-NEXT: ret1875 %c = icmp sge <2 x i32> <i32 0, i32 0>, %a1876 ret <2 x i1> %c1877}1878 1879define <4 x i1> @icmp_sge_v4i32_Zero_LHS(<4 x i32> %a) {1880; CHECK-LABEL: icmp_sge_v4i32_Zero_LHS:1881; CHECK: // %bb.0:1882; CHECK-NEXT: cmle v0.4s, v0.4s, #01883; CHECK-NEXT: xtn v0.4h, v0.4s1884; CHECK-NEXT: ret1885 %c = icmp sge <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a1886 ret <4 x i1> %c1887}1888 1889define <2 x i1> @icmp_sge_v2i64_Zero_LHS(<2 x i64> %a) {1890; CHECK-LABEL: icmp_sge_v2i64_Zero_LHS:1891; CHECK: // %bb.0:1892; CHECK-NEXT: cmle v0.2d, v0.2d, #01893; CHECK-NEXT: xtn v0.2s, v0.2d1894; CHECK-NEXT: ret1895 %c = icmp sge <2 x i64> <i64 0, i64 0>, %a1896 ret <2 x i1> %c1897}1898 1899define <8 x i1> @icmp_sgt_v8i8_Zero_LHS(<8 x i8> %a) {1900; CHECK-LABEL: icmp_sgt_v8i8_Zero_LHS:1901; CHECK: // %bb.0:1902; CHECK-NEXT: cmlt v0.8b, v0.8b, #01903; CHECK-NEXT: ret1904 %c = icmp sgt <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a1905 ret <8 x i1> %c1906}1907 1908define <16 x i1> @icmp_sgt_v16i8_Zero_LHS(<16 x i8> %a) {1909; CHECK-LABEL: icmp_sgt_v16i8_Zero_LHS:1910; CHECK: // %bb.0:1911; CHECK-NEXT: cmlt v0.16b, v0.16b, #01912; CHECK-NEXT: ret1913 %c = icmp sgt <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a1914 ret <16 x i1> %c1915}1916 1917define <4 x i1> @icmp_sgt_v4i16_Zero_LHS(<4 x i16> %a) {1918; CHECK-LABEL: icmp_sgt_v4i16_Zero_LHS:1919; CHECK: // %bb.0:1920; CHECK-NEXT: cmlt v0.4h, v0.4h, #01921; CHECK-NEXT: ret1922 %c = icmp sgt <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a1923 ret <4 x i1> %c1924}1925 1926define <8 x i1> @icmp_sgt_v8i16_Zero_LHS(<8 x i16> %a) {1927; CHECK-LABEL: icmp_sgt_v8i16_Zero_LHS:1928; CHECK: // %bb.0:1929; CHECK-NEXT: cmlt v0.8h, v0.8h, #01930; CHECK-NEXT: xtn v0.8b, v0.8h1931; CHECK-NEXT: ret1932 %c = icmp sgt <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a1933 ret <8 x i1> %c1934}1935 1936define <2 x i1> @icmp_sgt_v2i32_Zero_LHS(<2 x i32> %a) {1937; CHECK-LABEL: icmp_sgt_v2i32_Zero_LHS:1938; CHECK: // %bb.0:1939; CHECK-NEXT: cmlt v0.2s, v0.2s, #01940; CHECK-NEXT: ret1941 %c = icmp sgt <2 x i32> <i32 0, i32 0>, %a1942 ret <2 x i1> %c1943}1944 1945define <4 x i1> @icmp_sgt_v4i32_Zero_LHS(<4 x i32> %a) {1946; CHECK-LABEL: icmp_sgt_v4i32_Zero_LHS:1947; CHECK: // %bb.0:1948; CHECK-NEXT: cmlt v0.4s, v0.4s, #01949; CHECK-NEXT: xtn v0.4h, v0.4s1950; CHECK-NEXT: ret1951 %c = icmp sgt <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a1952 ret <4 x i1> %c1953}1954 1955define <2 x i1> @icmp_sgt_v2i64_Zero_LHS(<2 x i64> %a) {1956; CHECK-LABEL: icmp_sgt_v2i64_Zero_LHS:1957; CHECK: // %bb.0:1958; CHECK-NEXT: cmlt v0.2d, v0.2d, #01959; CHECK-NEXT: xtn v0.2s, v0.2d1960; CHECK-NEXT: ret1961 %c = icmp sgt <2 x i64> <i64 0, i64 0>, %a1962 ret <2 x i1> %c1963}1964 1965define <8 x i1> @icmp_sle_v8i8_Zero_LHS(<8 x i8> %a) {1966; CHECK-LABEL: icmp_sle_v8i8_Zero_LHS:1967; CHECK: // %bb.0:1968; CHECK-NEXT: cmge v0.8b, v0.8b, #01969; CHECK-NEXT: ret1970 %c = icmp sle <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a1971 ret <8 x i1> %c1972}1973 1974define <16 x i1> @icmp_sle_v16i8_Zero_LHS(<16 x i8> %a) {1975; CHECK-LABEL: icmp_sle_v16i8_Zero_LHS:1976; CHECK: // %bb.0:1977; CHECK-NEXT: cmge v0.16b, v0.16b, #01978; CHECK-NEXT: ret1979 %c = icmp sle <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a1980 ret <16 x i1> %c1981}1982 1983define <4 x i1> @icmp_sle_v4i16_Zero_LHS(<4 x i16> %a) {1984; CHECK-LABEL: icmp_sle_v4i16_Zero_LHS:1985; CHECK: // %bb.0:1986; CHECK-NEXT: cmge v0.4h, v0.4h, #01987; CHECK-NEXT: ret1988 %c = icmp sle <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a1989 ret <4 x i1> %c1990}1991 1992define <8 x i1> @icmp_sle_v8i16_Zero_LHS(<8 x i16> %a) {1993; CHECK-LABEL: icmp_sle_v8i16_Zero_LHS:1994; CHECK: // %bb.0:1995; CHECK-NEXT: cmge v0.8h, v0.8h, #01996; CHECK-NEXT: xtn v0.8b, v0.8h1997; CHECK-NEXT: ret1998 %c = icmp sle <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a1999 ret <8 x i1> %c2000}2001 2002define <2 x i1> @icmp_sle_v2i32_Zero_LHS(<2 x i32> %a) {2003; CHECK-LABEL: icmp_sle_v2i32_Zero_LHS:2004; CHECK: // %bb.0:2005; CHECK-NEXT: cmge v0.2s, v0.2s, #02006; CHECK-NEXT: ret2007 %c = icmp sle <2 x i32> <i32 0, i32 0>, %a2008 ret <2 x i1> %c2009}2010 2011define <4 x i1> @icmp_sle_v4i32_Zero_LHS(<4 x i32> %a) {2012; CHECK-LABEL: icmp_sle_v4i32_Zero_LHS:2013; CHECK: // %bb.0:2014; CHECK-NEXT: cmge v0.4s, v0.4s, #02015; CHECK-NEXT: xtn v0.4h, v0.4s2016; CHECK-NEXT: ret2017 %c = icmp sle <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a2018 ret <4 x i1> %c2019}2020 2021define <2 x i1> @icmp_sle_v2i64_Zero_LHS(<2 x i64> %a) {2022; CHECK-LABEL: icmp_sle_v2i64_Zero_LHS:2023; CHECK: // %bb.0:2024; CHECK-NEXT: cmge v0.2d, v0.2d, #02025; CHECK-NEXT: xtn v0.2s, v0.2d2026; CHECK-NEXT: ret2027 %c = icmp sle <2 x i64> <i64 0, i64 0>, %a2028 ret <2 x i1> %c2029}2030 2031define <8 x i1> @icmp_slt_v8i8_Zero_LHS(<8 x i8> %a) {2032; CHECK-LABEL: icmp_slt_v8i8_Zero_LHS:2033; CHECK: // %bb.0:2034; CHECK-NEXT: cmgt v0.8b, v0.8b, #02035; CHECK-NEXT: ret2036 %c = icmp slt <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a2037 ret <8 x i1> %c2038}2039 2040define <16 x i1> @icmp_slt_v16i8_Zero_LHS(<16 x i8> %a) {2041; CHECK-LABEL: icmp_slt_v16i8_Zero_LHS:2042; CHECK: // %bb.0:2043; CHECK-NEXT: cmgt v0.16b, v0.16b, #02044; CHECK-NEXT: ret2045 %c = icmp slt <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, %a2046 ret <16 x i1> %c2047}2048 2049define <4 x i1> @icmp_slt_v4i16_Zero_LHS(<4 x i16> %a) {2050; CHECK-LABEL: icmp_slt_v4i16_Zero_LHS:2051; CHECK: // %bb.0:2052; CHECK-NEXT: cmgt v0.4h, v0.4h, #02053; CHECK-NEXT: ret2054 %c = icmp slt <4 x i16> <i16 0, i16 0, i16 0, i16 0>, %a2055 ret <4 x i1> %c2056}2057 2058define <8 x i1> @icmp_slt_v8i16_Zero_LHS(<8 x i16> %a) {2059; CHECK-LABEL: icmp_slt_v8i16_Zero_LHS:2060; CHECK: // %bb.0:2061; CHECK-NEXT: cmgt v0.8h, v0.8h, #02062; CHECK-NEXT: xtn v0.8b, v0.8h2063; CHECK-NEXT: ret2064 %c = icmp slt <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, %a2065 ret <8 x i1> %c2066}2067 2068define <2 x i1> @icmp_slt_v2i32_Zero_LHS(<2 x i32> %a) {2069; CHECK-LABEL: icmp_slt_v2i32_Zero_LHS:2070; CHECK: // %bb.0:2071; CHECK-NEXT: cmgt v0.2s, v0.2s, #02072; CHECK-NEXT: ret2073 %c = icmp slt <2 x i32> <i32 0, i32 0>, %a2074 ret <2 x i1> %c2075}2076 2077define <4 x i1> @icmp_slt_v4i32_Zero_LHS(<4 x i32> %a) {2078; CHECK-LABEL: icmp_slt_v4i32_Zero_LHS:2079; CHECK: // %bb.0:2080; CHECK-NEXT: cmgt v0.4s, v0.4s, #02081; CHECK-NEXT: xtn v0.4h, v0.4s2082; CHECK-NEXT: ret2083 %c = icmp slt <4 x i32> <i32 0, i32 0, i32 0, i32 0>, %a2084 ret <4 x i1> %c2085}2086 2087define <2 x i1> @icmp_slt_v2i64_Zero_LHS(<2 x i64> %a) {2088; CHECK-LABEL: icmp_slt_v2i64_Zero_LHS:2089; CHECK: // %bb.0:2090; CHECK-NEXT: cmgt v0.2d, v0.2d, #02091; CHECK-NEXT: xtn v0.2s, v0.2d2092; CHECK-NEXT: ret2093 %c = icmp slt <2 x i64> <i64 0, i64 0>, %a2094 ret <2 x i1> %c2095}2096 2097; Test TST optimization for i8 sign bit testing with cross-type select2098; This tests the pattern: icmp slt i8 %val, 0; select i1 %cmp, i32 %a, i32 %b2099; The optimization should convert sxtb+cmp to tst for sign bit testing.2100 2101define i32 @i8_signbit_tst_constants(i8 %x, i8 %y) {2102; CHECK-SD-LABEL: i8_signbit_tst_constants:2103; CHECK-SD: // %bb.0:2104; CHECK-SD-NEXT: add w9, w0, w12105; CHECK-SD-NEXT: mov w8, #42 // =0x2a2106; CHECK-SD-NEXT: tst w9, #0x802107; CHECK-SD-NEXT: mov w9, #20894 // =0x519e2108; CHECK-SD-NEXT: csel w0, w9, w8, ne2109; CHECK-SD-NEXT: ret2110;2111; CHECK-GI-LABEL: i8_signbit_tst_constants:2112; CHECK-GI: // %bb.0:2113; CHECK-GI-NEXT: add w8, w0, w12114; CHECK-GI-NEXT: mov w9, #42 // =0x2a2115; CHECK-GI-NEXT: mov w10, #20894 // =0x519e2116; CHECK-GI-NEXT: sxtb w8, w82117; CHECK-GI-NEXT: cmp w8, #02118; CHECK-GI-NEXT: csel w0, w10, w9, mi2119; CHECK-GI-NEXT: ret2120 %add = add i8 %x, %y2121 %cmp = icmp slt i8 %add, 02122 %sel = select i1 %cmp, i32 20894, i32 422123 ret i32 %sel2124}2125 2126; Test i8 sign bit testing with variable select values (problematic case)2127define i32 @i8_signbit_variables(i8 %x, i8 %y, i32 %a, i32 %b) {2128; CHECK-SD-LABEL: i8_signbit_variables:2129; CHECK-SD: // %bb.0:2130; CHECK-SD-NEXT: add w8, w0, w12131; CHECK-SD-NEXT: tst w8, #0x802132; CHECK-SD-NEXT: csel w0, w2, w3, ne2133; CHECK-SD-NEXT: ret2134;2135; CHECK-GI-LABEL: i8_signbit_variables:2136; CHECK-GI: // %bb.0:2137; CHECK-GI-NEXT: add w8, w0, w12138; CHECK-GI-NEXT: sxtb w8, w82139; CHECK-GI-NEXT: cmp w8, #02140; CHECK-GI-NEXT: csel w0, w2, w3, mi2141; CHECK-GI-NEXT: ret2142 %add = add i8 %x, %y2143 %cmp = icmp slt i8 %add, 02144 %sel = select i1 %cmp, i32 %a, i32 %b2145 ret i32 %sel2146}2147