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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s3 4declare <4 x i16> @llvm.aarch64.neon.vcvtfp2hf(<4 x float>) #25declare <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8>, <8 x i8>) #26 7define <8 x half> @test1(<4 x float> noundef %a) {8; CHECK-LABEL: test1:9; CHECK: // %bb.0: // %entry10; CHECK-NEXT: fcvtn v0.4h, v0.4s11; CHECK-NEXT: ret12entry:13 %vcvt_f16_f321.i = tail call <4 x i16> @llvm.aarch64.neon.vcvtfp2hf(<4 x float> %a)14 %0 = bitcast <4 x i16> %vcvt_f16_f321.i to <4 x half>15 %shuffle.i = shufflevector <4 x half> %0, <4 x half> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>16 ret <8 x half> %shuffle.i17}18 19define <8 x i8> @test2(ptr nocapture noundef readonly %in, <8 x i8> noundef %idx) {20; CHECK-LABEL: test2:21; CHECK: // %bb.0: // %entry22; CHECK-NEXT: ldr q1, [x0]23; CHECK-NEXT: shrn v1.8b, v1.8h, #424; CHECK-NEXT: tbl v0.8b, { v1.16b }, v0.8b25; CHECK-NEXT: ret26entry:27 %0 = load <8 x i16>, ptr %in, align 228 %1 = lshr <8 x i16> %0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>29 %vshrn_n = trunc <8 x i16> %1 to <8 x i8>30 %vtbl1.i = shufflevector <8 x i8> %vshrn_n, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>31 %vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %idx)32 ret <8 x i8> %vtbl11.i33}34 35define <8 x i8> @tbl1v8i8(ptr nocapture noundef readonly %in, <8 x i8> noundef %idx) {36; CHECK-LABEL: tbl1v8i8:37; CHECK: // %bb.0: // %entry38; CHECK-NEXT: ldr q1, [x0]39; CHECK-NEXT: shrn v1.8b, v1.8h, #440; CHECK-NEXT: tbl v0.8b, { v1.16b }, v0.8b41; CHECK-NEXT: ret42entry:43 %0 = load <8 x i16>, ptr %in, align 244 %1 = lshr <8 x i16> %0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>45 %vshrn_n = trunc <8 x i16> %1 to <8 x i8>46 %vtbl1.i = shufflevector <8 x i8> %vshrn_n, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>47 %vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %idx)48 ret <8 x i8> %vtbl11.i49}50 51define <8 x i16> @addpv4i16(<4 x i16> noundef %a, <4 x i16> noundef %b) {52; CHECK-LABEL: addpv4i16:53; CHECK: // %bb.0: // %entry54; CHECK-NEXT: addp v0.4h, v0.4h, v1.4h55; CHECK-NEXT: ret56entry:57 %vpadd_v2.i = tail call <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16> %a, <4 x i16> %b)58 %shuffle.i = shufflevector <4 x i16> %vpadd_v2.i, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>59 ret <8 x i16> %shuffle.i60}61 62define <8 x i16> @addv4i16(<4 x i16> noundef %a, <4 x i16> noundef %b) {63; CHECK-LABEL: addv4i16:64; CHECK: // %bb.0: // %entry65; CHECK-NEXT: add v0.4h, v1.4h, v0.4h66; CHECK-NEXT: ret67entry:68 %add.i = add <4 x i16> %b, %a69 %shuffle.i = shufflevector <4 x i16> %add.i, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>70 ret <8 x i16> %shuffle.i71}72 73define <16 x i8> @rshrn(<8 x i16> noundef %a, <4 x i16> noundef %b) {74; CHECK-LABEL: rshrn:75; CHECK: // %bb.0: // %entry76; CHECK-NEXT: rshrn v0.8b, v0.8h, #377; CHECK-NEXT: ret78entry:79 %vrshrn_n1 = tail call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %a, i32 3)80 %shuffle.i = shufflevector <8 x i8> %vrshrn_n1, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>81 ret <16 x i8> %shuffle.i82}83 84define <16 x i8> @tbl1(<16 x i8> %a, <8 x i8> %b) {85; CHECK-LABEL: tbl1:86; CHECK: // %bb.0: // %entry87; CHECK-NEXT: tbl v0.8b, { v0.16b }, v1.8b88; CHECK-NEXT: ret89entry:90 %vtbl11 = tail call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %a, <8 x i8> %b)91 %shuffle.i = shufflevector <8 x i8> %vtbl11, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>92 ret <16 x i8> %shuffle.i93}94 95define <2 x double> @fadd(double noundef %x, double noundef %y) {96; CHECK-LABEL: fadd:97; CHECK: // %bb.0: // %entry98; CHECK-NEXT: movi v2.2d, #000000000000000099; CHECK-NEXT: fadd d0, d0, d1100; CHECK-NEXT: mov v2.d[0], v0.d[0]101; CHECK-NEXT: mov v0.16b, v2.16b102; CHECK-NEXT: ret103entry:104 %add = fadd double %x, %y105 %vecinit1 = insertelement <2 x double> poison, double %add, i64 0106 %vecinit2 = insertelement <2 x double> %vecinit1, double 0.0, i64 1107 ret <2 x double> %vecinit2108}109 110define <16 x i8> @bsl(<4 x i16> noundef %a, <4 x i16> noundef %c, <4 x i16> noundef %d, <4 x i16> noundef %b) {111; CHECK-LABEL: bsl:112; CHECK: // %bb.0: // %entry113; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b114; CHECK-NEXT: ret115entry:116 %vbsl3.i = and <4 x i16> %c, %a117 %0 = xor <4 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1>118 %vbsl4.i = and <4 x i16> %0, %d119 %vbsl5.i = or <4 x i16> %vbsl4.i, %vbsl3.i120 %1 = bitcast <4 x i16> %vbsl5.i to <8 x i8>121 %shuffle.i = shufflevector <8 x i8> %1, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>122 ret <16 x i8> %shuffle.i123}124 125define <16 x i8> @load(ptr %a, <8 x i8> %b) {126; CHECK-LABEL: load:127; CHECK: // %bb.0: // %entry128; CHECK-NEXT: ldr d0, [x0]129; CHECK-NEXT: ret130entry:131 %vtbl11 = load <8 x i8>, ptr %a132 %shuffle.i = shufflevector <8 x i8> %vtbl11, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>133 ret <16 x i8> %shuffle.i134}135 136 137define <16 x i8> @insertzero_v8i8(<8 x i8> %a) {138; CHECK-LABEL: insertzero_v8i8:139; CHECK: // %bb.0: // %entry140; CHECK-NEXT: fmov d0, d0141; CHECK-NEXT: ret142entry:143 %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>144 ret <16 x i8> %shuffle.i145}146 147define <8 x i16> @insertzero_v4i16(<4 x i16> %a) {148; CHECK-LABEL: insertzero_v4i16:149; CHECK: // %bb.0: // %entry150; CHECK-NEXT: fmov d0, d0151; CHECK-NEXT: ret152entry:153 %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>154 ret <8 x i16> %shuffle.i155}156 157define <4 x i32> @insertzero_v2i32(<2 x i32> %a) {158; CHECK-LABEL: insertzero_v2i32:159; CHECK: // %bb.0: // %entry160; CHECK-NEXT: fmov d0, d0161; CHECK-NEXT: ret162entry:163 %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>164 ret <4 x i32> %shuffle.i165}166 167define <2 x i64> @insertzero_v1i64(<1 x i64> %a) {168; CHECK-LABEL: insertzero_v1i64:169; CHECK: // %bb.0: // %entry170; CHECK-NEXT: fmov d0, d0171; CHECK-NEXT: ret172entry:173 %shuffle.i = shufflevector <1 x i64> %a, <1 x i64> zeroinitializer, <2 x i32> <i32 0, i32 1>174 ret <2 x i64> %shuffle.i175}176 177define <8 x half> @insertzero_v4f16(<4 x half> %a) {178; CHECK-LABEL: insertzero_v4f16:179; CHECK: // %bb.0: // %entry180; CHECK-NEXT: fmov d0, d0181; CHECK-NEXT: ret182entry:183 %shuffle.i = shufflevector <4 x half> %a, <4 x half> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>184 ret <8 x half> %shuffle.i185}186 187define <8 x bfloat> @insertzero_v4bf16(<4 x bfloat> %a) {188; CHECK-LABEL: insertzero_v4bf16:189; CHECK: // %bb.0: // %entry190; CHECK-NEXT: fmov d0, d0191; CHECK-NEXT: ret192entry:193 %shuffle.i = shufflevector <4 x bfloat> %a, <4 x bfloat> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>194 ret <8 x bfloat> %shuffle.i195}196 197define <4 x float> @insertzero_v2f32(<2 x float> %a) {198; CHECK-LABEL: insertzero_v2f32:199; CHECK: // %bb.0: // %entry200; CHECK-NEXT: fmov d0, d0201; CHECK-NEXT: ret202entry:203 %shuffle.i = shufflevector <2 x float> %a, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>204 ret <4 x float> %shuffle.i205}206 207define <2 x double> @insertzero_v1f64(<1 x double> %a) {208; CHECK-LABEL: insertzero_v1f64:209; CHECK: // %bb.0: // %entry210; CHECK-NEXT: fmov d0, d0211; CHECK-NEXT: ret212entry:213 %shuffle.i = shufflevector <1 x double> %a, <1 x double> zeroinitializer, <2 x i32> <i32 0, i32 1>214 ret <2 x double> %shuffle.i215}216 217 218 219declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32)220declare <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16>, <4 x i16>)221