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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s3 4; These two forms are equivalent:5; sub %y, (xor %x, -1)6; add (add %x, 1), %y7; Some targets may prefer one to the other.8 9define i8 @scalar_i8(i8 %x, i8 %y) nounwind {10; CHECK-LABEL: scalar_i8:11; CHECK: // %bb.0:12; CHECK-NEXT: add w8, w0, w113; CHECK-NEXT: add w0, w8, #114; CHECK-NEXT: ret15 %t0 = add i8 %x, 116 %t1 = add i8 %y, %t017 ret i8 %t118}19 20define i16 @scalar_i16(i16 %x, i16 %y) nounwind {21; CHECK-LABEL: scalar_i16:22; CHECK: // %bb.0:23; CHECK-NEXT: add w8, w0, w124; CHECK-NEXT: add w0, w8, #125; CHECK-NEXT: ret26 %t0 = add i16 %x, 127 %t1 = add i16 %y, %t028 ret i16 %t129}30 31define i32 @scalar_i32(i32 %x, i32 %y) nounwind {32; CHECK-LABEL: scalar_i32:33; CHECK: // %bb.0:34; CHECK-NEXT: add w8, w0, w135; CHECK-NEXT: add w0, w8, #136; CHECK-NEXT: ret37 %t0 = add i32 %x, 138 %t1 = add i32 %y, %t039 ret i32 %t140}41 42define i64 @scalar_i64(i64 %x, i64 %y) nounwind {43; CHECK-LABEL: scalar_i64:44; CHECK: // %bb.0:45; CHECK-NEXT: add x8, x0, x146; CHECK-NEXT: add x0, x8, #147; CHECK-NEXT: ret48 %t0 = add i64 %x, 149 %t1 = add i64 %y, %t050 ret i64 %t151}52 53define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {54; CHECK-LABEL: vector_i128_i8:55; CHECK: // %bb.0:56; CHECK-NEXT: mvn v0.16b, v0.16b57; CHECK-NEXT: sub v0.16b, v1.16b, v0.16b58; CHECK-NEXT: ret59 %t0 = add <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>60 %t1 = add <16 x i8> %y, %t061 ret <16 x i8> %t162}63 64define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y) nounwind {65; CHECK-LABEL: vector_i128_i16:66; CHECK: // %bb.0:67; CHECK-NEXT: mvn v0.16b, v0.16b68; CHECK-NEXT: sub v0.8h, v1.8h, v0.8h69; CHECK-NEXT: ret70 %t0 = add <8 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>71 %t1 = add <8 x i16> %y, %t072 ret <8 x i16> %t173}74 75define <4 x i32> @vector_i128_i32(<4 x i32> %x, <4 x i32> %y) nounwind {76; CHECK-LABEL: vector_i128_i32:77; CHECK: // %bb.0:78; CHECK-NEXT: mvn v0.16b, v0.16b79; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s80; CHECK-NEXT: ret81 %t0 = add <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>82 %t1 = add <4 x i32> %y, %t083 ret <4 x i32> %t184}85 86define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {87; CHECK-LABEL: vector_i128_i64:88; CHECK: // %bb.0:89; CHECK-NEXT: mvn v0.16b, v0.16b90; CHECK-NEXT: sub v0.2d, v1.2d, v0.2d91; CHECK-NEXT: ret92 %t0 = add <2 x i64> %x, <i64 1, i64 1>93 %t1 = add <2 x i64> %y, %t094 ret <2 x i64> %t195}96