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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s | FileCheck %s3 4target triple = "aarch64-unknown-linux-gnu"5 6; SCALABLE INSERTED INTO SCALABLE TESTS7 8define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_zero_i8(ptr %a, ptr %b) #0 {9; CHECK-LABEL: vec_scalable_subvec_scalable_idx_zero_i8:10; CHECK: // %bb.0:11; CHECK-NEXT: ptrue p0.h12; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]13; CHECK-NEXT: ptrue p0.s14; CHECK-NEXT: ld1b { z1.s }, p0/z, [x1]15; CHECK-NEXT: uunpkhi z0.s, z0.h16; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h17; CHECK-NEXT: ret18 %vec = load <vscale x 8 x i8>, ptr %a19 %subvec = load <vscale x 4 x i8>, ptr %b20 %ins = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> %vec, <vscale x 4 x i8> %subvec, i64 0)21 ret <vscale x 8 x i8> %ins22}23 24define <vscale x 8 x i8> @vec_scalable_subvec_scalable_idx_nonzero_i8(ptr %a, ptr %b) #0 {25; CHECK-LABEL: vec_scalable_subvec_scalable_idx_nonzero_i8:26; CHECK: // %bb.0:27; CHECK-NEXT: ptrue p0.h28; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]29; CHECK-NEXT: ptrue p0.s30; CHECK-NEXT: ld1b { z1.s }, p0/z, [x1]31; CHECK-NEXT: uunpklo z0.s, z0.h32; CHECK-NEXT: uzp1 z0.h, z0.h, z1.h33; CHECK-NEXT: ret34 %vec = load <vscale x 8 x i8>, ptr %a35 %subvec = load <vscale x 4 x i8>, ptr %b36 %ins = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8> %vec, <vscale x 4 x i8> %subvec, i64 4)37 ret <vscale x 8 x i8> %ins38}39 40define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_zero_i16(ptr %a, ptr %b) #0 {41; CHECK-LABEL: vec_scalable_subvec_scalable_idx_zero_i16:42; CHECK: // %bb.0:43; CHECK-NEXT: ptrue p0.s44; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]45; CHECK-NEXT: ptrue p0.d46; CHECK-NEXT: ld1h { z1.d }, p0/z, [x1]47; CHECK-NEXT: uunpkhi z0.d, z0.s48; CHECK-NEXT: uzp1 z0.s, z1.s, z0.s49; CHECK-NEXT: ret50 %vec = load <vscale x 4 x i16>, ptr %a51 %subvec = load <vscale x 2 x i16>, ptr %b52 %ins = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> %vec, <vscale x 2 x i16> %subvec, i64 0)53 ret <vscale x 4 x i16> %ins54}55 56define <vscale x 4 x i16> @vec_scalable_subvec_scalable_idx_nonzero_i16(ptr %a, ptr %b) #0 {57; CHECK-LABEL: vec_scalable_subvec_scalable_idx_nonzero_i16:58; CHECK: // %bb.0:59; CHECK-NEXT: ptrue p0.s60; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]61; CHECK-NEXT: ptrue p0.d62; CHECK-NEXT: ld1h { z1.d }, p0/z, [x1]63; CHECK-NEXT: uunpklo z0.d, z0.s64; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s65; CHECK-NEXT: ret66 %vec = load <vscale x 4 x i16>, ptr %a67 %subvec = load <vscale x 2 x i16>, ptr %b68 %ins = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16> %vec, <vscale x 2 x i16> %subvec, i64 2)69 ret <vscale x 4 x i16> %ins70}71 72; FIXED INSERTED INTO SCALABLE TESTS73 74define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_zero_i8(ptr %a, ptr %b) #0 {75; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i8:76; CHECK: // %bb.0:77; CHECK-NEXT: ptrue p0.h78; CHECK-NEXT: ldr d0, [x1]79; CHECK-NEXT: ld1b { z1.h }, p0/z, [x0]80; CHECK-NEXT: ushll v0.8h, v0.8b, #081; CHECK-NEXT: ptrue p0.h, vl882; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h83; CHECK-NEXT: ret84 %vec = load <vscale x 8 x i8>, ptr %a85 %subvec = load <8 x i8>, ptr %b86 %ins = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v8i8(<vscale x 8 x i8> %vec, <8 x i8> %subvec, i64 0)87 ret <vscale x 8 x i8> %ins88}89 90define <vscale x 8 x i8> @vec_scalable_subvec_fixed_idx_nonzero_i8(ptr %a, ptr %b) #0 {91; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i8:92; CHECK: // %bb.0:93; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill94; CHECK-NEXT: addvl sp, sp, #-195; CHECK-NEXT: cnth x896; CHECK-NEXT: ptrue p0.h97; CHECK-NEXT: ldr d1, [x1]98; CHECK-NEXT: sub x8, x8, #899; CHECK-NEXT: mov w9, #8 // =0x8100; CHECK-NEXT: cmp x8, #8101; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]102; CHECK-NEXT: ushll v1.8h, v1.8b, #0103; CHECK-NEXT: csel x8, x8, x9, lo104; CHECK-NEXT: mov x9, sp105; CHECK-NEXT: lsl x8, x8, #1106; CHECK-NEXT: str z0, [sp]107; CHECK-NEXT: str q1, [x9, x8]108; CHECK-NEXT: ldr z0, [sp]109; CHECK-NEXT: addvl sp, sp, #1110; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload111; CHECK-NEXT: ret112 %vec = load <vscale x 8 x i8>, ptr %a113 %subvec = load <8 x i8>, ptr %b114 %ins = call <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v8i8(<vscale x 8 x i8> %vec, <8 x i8> %subvec, i64 8)115 ret <vscale x 8 x i8> %ins116}117 118define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_zero_i16(ptr %a, ptr %b) #0 {119; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i16:120; CHECK: // %bb.0:121; CHECK-NEXT: ptrue p0.s122; CHECK-NEXT: ldr d0, [x1]123; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0]124; CHECK-NEXT: ushll v0.4s, v0.4h, #0125; CHECK-NEXT: ptrue p0.s, vl4126; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s127; CHECK-NEXT: ret128 %vec = load <vscale x 4 x i16>, ptr %a129 %subvec = load <4 x i16>, ptr %b130 %ins = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v4i16(<vscale x 4 x i16> %vec, <4 x i16> %subvec, i64 0)131 ret <vscale x 4 x i16> %ins132}133 134define <vscale x 4 x i16> @vec_scalable_subvec_fixed_idx_nonzero_i16(ptr %a, ptr %b) #0 {135; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i16:136; CHECK: // %bb.0:137; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill138; CHECK-NEXT: addvl sp, sp, #-1139; CHECK-NEXT: cntw x8140; CHECK-NEXT: ptrue p0.s141; CHECK-NEXT: ldr d1, [x1]142; CHECK-NEXT: sub x8, x8, #4143; CHECK-NEXT: mov w9, #4 // =0x4144; CHECK-NEXT: cmp x8, #4145; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]146; CHECK-NEXT: ushll v1.4s, v1.4h, #0147; CHECK-NEXT: csel x8, x8, x9, lo148; CHECK-NEXT: mov x9, sp149; CHECK-NEXT: lsl x8, x8, #2150; CHECK-NEXT: str z0, [sp]151; CHECK-NEXT: str q1, [x9, x8]152; CHECK-NEXT: ldr z0, [sp]153; CHECK-NEXT: addvl sp, sp, #1154; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload155; CHECK-NEXT: ret156 %vec = load <vscale x 4 x i16>, ptr %a157 %subvec = load <4 x i16>, ptr %b158 %ins = call <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v4i16(<vscale x 4 x i16> %vec, <4 x i16> %subvec, i64 4)159 ret <vscale x 4 x i16> %ins160}161 162define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_zero_i32(ptr %a, ptr %b) #0 {163; CHECK-LABEL: vec_scalable_subvec_fixed_idx_zero_i32:164; CHECK: // %bb.0:165; CHECK-NEXT: ptrue p0.d166; CHECK-NEXT: ldr d0, [x1]167; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0]168; CHECK-NEXT: ushll v0.2d, v0.2s, #0169; CHECK-NEXT: ptrue p0.d, vl2170; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d171; CHECK-NEXT: ret172 %vec = load <vscale x 2 x i32>, ptr %a173 %subvec = load <2 x i32>, ptr %b174 %ins = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v2i32(<vscale x 2 x i32> %vec, <2 x i32> %subvec, i64 0)175 ret <vscale x 2 x i32> %ins176}177 178define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_i32(ptr %a, ptr %b) #0 {179; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_i32:180; CHECK: // %bb.0:181; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill182; CHECK-NEXT: addvl sp, sp, #-1183; CHECK-NEXT: cntd x8184; CHECK-NEXT: ptrue p0.d185; CHECK-NEXT: ldr d1, [x1]186; CHECK-NEXT: sub x8, x8, #2187; CHECK-NEXT: mov w9, #2 // =0x2188; CHECK-NEXT: cmp x8, #2189; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]190; CHECK-NEXT: ushll v1.2d, v1.2s, #0191; CHECK-NEXT: csel x8, x8, x9, lo192; CHECK-NEXT: mov x9, sp193; CHECK-NEXT: lsl x8, x8, #3194; CHECK-NEXT: str z0, [sp]195; CHECK-NEXT: str q1, [x9, x8]196; CHECK-NEXT: ldr z0, [sp]197; CHECK-NEXT: addvl sp, sp, #1198; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload199; CHECK-NEXT: ret200 %vec = load <vscale x 2 x i32>, ptr %a201 %subvec = load <2 x i32>, ptr %b202 %ins = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v2i32(<vscale x 2 x i32> %vec, <2 x i32> %subvec, i64 2)203 ret <vscale x 2 x i32> %ins204}205 206define <vscale x 2 x i32> @vec_scalable_subvec_fixed_idx_nonzero_large_i32(ptr %a, ptr %b) #1 {207; CHECK-LABEL: vec_scalable_subvec_fixed_idx_nonzero_large_i32:208; CHECK: // %bb.0:209; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill210; CHECK-NEXT: addvl sp, sp, #-1211; CHECK-NEXT: ptrue p0.d, vl8212; CHECK-NEXT: ld1w { z0.d }, p0/z, [x1]213; CHECK-NEXT: addvl sp, sp, #1214; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload215; CHECK-NEXT: ret216 %vec = load <vscale x 2 x i32>, ptr %a217 %subvec = load <8 x i32>, ptr %b218 %ins = call <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32> %vec, <8 x i32> %subvec, i64 8)219 ret <vscale x 2 x i32> %ins220}221 222declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.nxv4i8(<vscale x 8 x i8>, <vscale x 4 x i8>, i64)223declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.nxv2i16(<vscale x 4 x i16>, <vscale x 2 x i16>, i64)224 225declare <vscale x 8 x i8> @llvm.vector.insert.nxv8i8.v8i8(<vscale x 8 x i8>, <8 x i8>, i64)226declare <vscale x 4 x i16> @llvm.vector.insert.nxv4i16.v4i16(<vscale x 4 x i16>, <4 x i16>, i64)227declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v2i32(<vscale x 2 x i32>, <2 x i32>, i64)228 229declare <vscale x 2 x i32> @llvm.vector.insert.nxv2i32.v8i32(<vscale x 2 x i32>, <8 x i32>, i64)230 231attributes #0 = { nounwind "target-features"="+sve" }232attributes #1 = { nounwind "target-features"="+sve" vscale_range(4,4) }233