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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=aarch64 < %s -o - | FileCheck %s3 4define <vscale x 16 x i1> @match_nxv16i8_v1i8(<vscale x 16 x i8> %op1, <1 x i8> %op2, <vscale x 16 x i1> %mask) #0 {5; CHECK-LABEL: match_nxv16i8_v1i8:6; CHECK: // %bb.0:7; CHECK-NEXT: // kill: def $d1 killed $d1 def $z18; CHECK-NEXT: mov z1.b, b19; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, z1.b10; CHECK-NEXT: ret11 %r = tail call <vscale x 16 x i1> @llvm.experimental.vector.match(<vscale x 16 x i8> %op1, <1 x i8> %op2, <vscale x 16 x i1> %mask)12 ret <vscale x 16 x i1> %r13}14 15define <vscale x 16 x i1> @match_nxv16i8_v2i8(<vscale x 16 x i8> %op1, <2 x i8> %op2, <vscale x 16 x i1> %mask) #0 {16; CHECK-LABEL: match_nxv16i8_v2i8:17; CHECK: // %bb.0:18; CHECK-NEXT: // kill: def $d1 killed $d1 def $q119; CHECK-NEXT: mov w8, v1.s[1]20; CHECK-NEXT: fmov w9, s121; CHECK-NEXT: ptrue p1.b22; CHECK-NEXT: mov z2.b, w923; CHECK-NEXT: mov z1.b, w824; CHECK-NEXT: cmpeq p2.b, p1/z, z0.b, z1.b25; CHECK-NEXT: cmpeq p1.b, p1/z, z0.b, z2.b26; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b27; CHECK-NEXT: and p0.b, p1/z, p1.b, p0.b28; CHECK-NEXT: ret29 %r = tail call <vscale x 16 x i1> @llvm.experimental.vector.match(<vscale x 16 x i8> %op1, <2 x i8> %op2, <vscale x 16 x i1> %mask)30 ret <vscale x 16 x i1> %r31}32 33define <vscale x 16 x i1> @match_nxv16i8_v4i8(<vscale x 16 x i8> %op1, <4 x i8> %op2, <vscale x 16 x i1> %mask) #0 {34; CHECK-LABEL: match_nxv16i8_v4i8:35; CHECK: // %bb.0:36; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill37; CHECK-NEXT: addvl sp, sp, #-138; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill39; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG40; CHECK-NEXT: .cfi_offset w29, -1641; CHECK-NEXT: // kill: def $d1 killed $d1 def $q142; CHECK-NEXT: umov w8, v1.h[1]43; CHECK-NEXT: umov w9, v1.h[0]44; CHECK-NEXT: umov w10, v1.h[2]45; CHECK-NEXT: ptrue p1.b46; CHECK-NEXT: mov z2.b, w847; CHECK-NEXT: mov z3.b, w948; CHECK-NEXT: umov w8, v1.h[3]49; CHECK-NEXT: mov z1.b, w1050; CHECK-NEXT: cmpeq p2.b, p1/z, z0.b, z2.b51; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z3.b52; CHECK-NEXT: mov z2.b, w853; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z1.b54; CHECK-NEXT: cmpeq p1.b, p1/z, z0.b, z2.b55; CHECK-NEXT: mov p2.b, p3/m, p3.b56; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b57; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload58; CHECK-NEXT: mov p1.b, p2/m, p2.b59; CHECK-NEXT: and p0.b, p1/z, p1.b, p0.b60; CHECK-NEXT: addvl sp, sp, #161; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload62; CHECK-NEXT: ret63 %r = tail call <vscale x 16 x i1> @llvm.experimental.vector.match(<vscale x 16 x i8> %op1, <4 x i8> %op2, <vscale x 16 x i1> %mask)64 ret <vscale x 16 x i1> %r65}66 67define <vscale x 16 x i1> @match_nxv16i8_v8i8(<vscale x 16 x i8> %op1, <8 x i8> %op2, <vscale x 16 x i1> %mask) #0 {68; CHECK-LABEL: match_nxv16i8_v8i8:69; CHECK: // %bb.0:70; CHECK-NEXT: // kill: def $d1 killed $d1 def $z171; CHECK-NEXT: mov z1.d, d172; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b73; CHECK-NEXT: ret74 %r = tail call <vscale x 16 x i1> @llvm.experimental.vector.match(<vscale x 16 x i8> %op1, <8 x i8> %op2, <vscale x 16 x i1> %mask)75 ret <vscale x 16 x i1> %r76}77 78define <vscale x 16 x i1> @match_nxv16i8_v16i8(<vscale x 16 x i8> %op1, <16 x i8> %op2, <vscale x 16 x i1> %mask) #0 {79; CHECK-LABEL: match_nxv16i8_v16i8:80; CHECK: // %bb.0:81; CHECK-NEXT: // kill: def $q1 killed $q1 def $z182; CHECK-NEXT: mov z1.q, q183; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b84; CHECK-NEXT: ret85 %r = tail call <vscale x 16 x i1> @llvm.experimental.vector.match(<vscale x 16 x i8> %op1, <16 x i8> %op2, <vscale x 16 x i1> %mask)86 ret <vscale x 16 x i1> %r87}88 89define <16 x i1> @match_v16i8_v1i8(<16 x i8> %op1, <1 x i8> %op2, <16 x i1> %mask) #0 {90; CHECK-LABEL: match_v16i8_v1i8:91; CHECK: // %bb.0:92; CHECK-NEXT: // kill: def $d1 killed $d1 def $q193; CHECK-NEXT: dup v1.16b, v1.b[0]94; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b95; CHECK-NEXT: and v0.16b, v0.16b, v2.16b96; CHECK-NEXT: ret97 %r = tail call <16 x i1> @llvm.experimental.vector.match(<16 x i8> %op1, <1 x i8> %op2, <16 x i1> %mask)98 ret <16 x i1> %r99}100 101define <16 x i1> @match_v16i8_v2i8(<16 x i8> %op1, <2 x i8> %op2, <16 x i1> %mask) #0 {102; CHECK-LABEL: match_v16i8_v2i8:103; CHECK: // %bb.0:104; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1105; CHECK-NEXT: dup v3.16b, v1.b[4]106; CHECK-NEXT: dup v1.16b, v1.b[0]107; CHECK-NEXT: cmeq v3.16b, v0.16b, v3.16b108; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b109; CHECK-NEXT: orr v0.16b, v0.16b, v3.16b110; CHECK-NEXT: and v0.16b, v0.16b, v2.16b111; CHECK-NEXT: ret112 %r = tail call <16 x i1> @llvm.experimental.vector.match(<16 x i8> %op1, <2 x i8> %op2, <16 x i1> %mask)113 ret <16 x i1> %r114}115 116define <16 x i1> @match_v16i8_v4i8(<16 x i8> %op1, <4 x i8> %op2, <16 x i1> %mask) #0 {117; CHECK-LABEL: match_v16i8_v4i8:118; CHECK: // %bb.0:119; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1120; CHECK-NEXT: dup v3.16b, v1.b[2]121; CHECK-NEXT: dup v4.16b, v1.b[0]122; CHECK-NEXT: dup v5.16b, v1.b[4]123; CHECK-NEXT: dup v1.16b, v1.b[6]124; CHECK-NEXT: cmeq v3.16b, v0.16b, v3.16b125; CHECK-NEXT: cmeq v4.16b, v0.16b, v4.16b126; CHECK-NEXT: cmeq v5.16b, v0.16b, v5.16b127; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b128; CHECK-NEXT: orr v1.16b, v4.16b, v3.16b129; CHECK-NEXT: orr v0.16b, v5.16b, v0.16b130; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b131; CHECK-NEXT: and v0.16b, v0.16b, v2.16b132; CHECK-NEXT: ret133 %r = tail call <16 x i1> @llvm.experimental.vector.match(<16 x i8> %op1, <4 x i8> %op2, <16 x i1> %mask)134 ret <16 x i1> %r135}136 137define <16 x i1> @match_v16i8_v8i8(<16 x i8> %op1, <8 x i8> %op2, <16 x i1> %mask) #0 {138; CHECK-LABEL: match_v16i8_v8i8:139; CHECK: // %bb.0:140; CHECK-NEXT: shl v2.16b, v2.16b, #7141; CHECK-NEXT: ptrue p0.b, vl16142; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1143; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0144; CHECK-NEXT: mov z1.d, d1145; CHECK-NEXT: cmpne p0.b, p0/z, z2.b, #0146; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b147; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff148; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0149; CHECK-NEXT: ret150 %r = tail call <16 x i1> @llvm.experimental.vector.match(<16 x i8> %op1, <8 x i8> %op2, <16 x i1> %mask)151 ret <16 x i1> %r152}153 154define <16 x i1> @match_v16i8_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask) #0 {155; CHECK-LABEL: match_v16i8_v16i8:156; CHECK: // %bb.0:157; CHECK-NEXT: shl v2.16b, v2.16b, #7158; CHECK-NEXT: ptrue p0.b, vl16159; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1160; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0161; CHECK-NEXT: cmpne p0.b, p0/z, z2.b, #0162; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b163; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff164; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0165; CHECK-NEXT: ret166 %r = tail call <16 x i1> @llvm.experimental.vector.match(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask)167 ret <16 x i1> %r168}169 170define <8 x i1> @match_v8i8_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) #0 {171; CHECK-LABEL: match_v8i8_v8i8:172; CHECK: // %bb.0:173; CHECK-NEXT: shl v2.8b, v2.8b, #7174; CHECK-NEXT: ptrue p0.b, vl8175; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1176; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0177; CHECK-NEXT: mov z1.d, d1178; CHECK-NEXT: cmpne p0.b, p0/z, z2.b, #0179; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b180; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff181; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0182; CHECK-NEXT: ret183 %r = tail call <8 x i1> @llvm.experimental.vector.match(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask)184 ret <8 x i1> %r185}186 187define <vscale x 8 x i1> @match_nxv8i16_v8i16(<vscale x 8 x i16> %op1, <8 x i16> %op2, <vscale x 8 x i1> %mask) #0 {188; CHECK-LABEL: match_nxv8i16_v8i16:189; CHECK: // %bb.0:190; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1191; CHECK-NEXT: mov z1.q, q1192; CHECK-NEXT: match p0.h, p0/z, z0.h, z1.h193; CHECK-NEXT: ret194 %r = tail call <vscale x 8 x i1> @llvm.experimental.vector.match(<vscale x 8 x i16> %op1, <8 x i16> %op2, <vscale x 8 x i1> %mask)195 ret <vscale x 8 x i1> %r196}197 198define <8 x i1> @match_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) #0 {199; CHECK-LABEL: match_v8i16:200; CHECK: // %bb.0:201; CHECK-NEXT: ushll v2.8h, v2.8b, #0202; CHECK-NEXT: ptrue p0.h, vl8203; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1204; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0205; CHECK-NEXT: shl v2.8h, v2.8h, #15206; CHECK-NEXT: cmpne p0.h, p0/z, z2.h, #0207; CHECK-NEXT: match p0.h, p0/z, z0.h, z1.h208; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff209; CHECK-NEXT: xtn v0.8b, v0.8h210; CHECK-NEXT: ret211 %r = tail call <8 x i1> @llvm.experimental.vector.match(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask)212 ret <8 x i1> %r213}214 215; Cases where op2 has more elements than op1.216 217define <8 x i1> @match_v8i8_v16i8(<8 x i8> %op1, <16 x i8> %op2, <8 x i1> %mask) #0 {218; CHECK-LABEL: match_v8i8_v16i8:219; CHECK: // %bb.0:220; CHECK-NEXT: shl v2.8b, v2.8b, #7221; CHECK-NEXT: ptrue p0.b, vl8222; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1223; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0224; CHECK-NEXT: cmpne p0.b, p0/z, z2.b, #0225; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b226; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff227; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0228; CHECK-NEXT: ret229 %r = tail call <8 x i1> @llvm.experimental.vector.match(<8 x i8> %op1, <16 x i8> %op2, <8 x i1> %mask)230 ret <8 x i1> %r231}232 233define <vscale x 16 x i1> @match_nxv16i8_v32i8(<vscale x 16 x i8> %op1, <32 x i8> %op2, <vscale x 16 x i1> %mask) #0 {234; CHECK-LABEL: match_nxv16i8_v32i8:235; CHECK: // %bb.0:236; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill237; CHECK-NEXT: addvl sp, sp, #-1238; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill239; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG240; CHECK-NEXT: .cfi_offset w29, -16241; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1242; CHECK-NEXT: mov z3.b, z1.b[1]243; CHECK-NEXT: mov z4.b, b1244; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2245; CHECK-NEXT: ptrue p1.b246; CHECK-NEXT: mov z5.b, z1.b[2]247; CHECK-NEXT: cmpeq p2.b, p1/z, z0.b, z3.b248; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z4.b249; CHECK-NEXT: mov z3.b, z1.b[3]250; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z5.b251; CHECK-NEXT: mov z4.b, z1.b[4]252; CHECK-NEXT: mov p2.b, p3/m, p3.b253; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z3.b254; CHECK-NEXT: mov z3.b, z1.b[5]255; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b256; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z4.b257; CHECK-NEXT: mov z4.b, z1.b[6]258; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b259; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z3.b260; CHECK-NEXT: mov z3.b, z1.b[7]261; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b262; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z4.b263; CHECK-NEXT: mov z4.b, z1.b[8]264; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b265; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z3.b266; CHECK-NEXT: mov z3.b, z1.b[9]267; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b268; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z4.b269; CHECK-NEXT: mov z4.b, z1.b[10]270; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b271; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z3.b272; CHECK-NEXT: mov z3.b, z1.b[11]273; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b274; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z4.b275; CHECK-NEXT: mov z4.b, z1.b[12]276; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b277; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z3.b278; CHECK-NEXT: mov z3.b, z1.b[13]279; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b280; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z4.b281; CHECK-NEXT: mov z4.b, z1.b[14]282; CHECK-NEXT: mov z1.b, z1.b[15]283; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b284; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z3.b285; CHECK-NEXT: mov z3.b, b2286; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b287; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z4.b288; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b289; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b290; CHECK-NEXT: mov z1.b, z2.b[1]291; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b292; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b293; CHECK-NEXT: mov z3.b, z2.b[2]294; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b295; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b296; CHECK-NEXT: mov z1.b, z2.b[3]297; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b298; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b299; CHECK-NEXT: mov z3.b, z2.b[4]300; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b301; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b302; CHECK-NEXT: mov z1.b, z2.b[5]303; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b304; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b305; CHECK-NEXT: mov z3.b, z2.b[6]306; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b307; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b308; CHECK-NEXT: mov z1.b, z2.b[7]309; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b310; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b311; CHECK-NEXT: mov z3.b, z2.b[8]312; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b313; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b314; CHECK-NEXT: mov z1.b, z2.b[9]315; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b316; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b317; CHECK-NEXT: mov z3.b, z2.b[10]318; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b319; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b320; CHECK-NEXT: mov z1.b, z2.b[11]321; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b322; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b323; CHECK-NEXT: mov z3.b, z2.b[12]324; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b325; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b326; CHECK-NEXT: mov z1.b, z2.b[13]327; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b328; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b329; CHECK-NEXT: mov z3.b, z2.b[14]330; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b331; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b332; CHECK-NEXT: mov z1.b, z2.b[15]333; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b334; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b335; CHECK-NEXT: cmpeq p1.b, p1/z, z0.b, z1.b336; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b337; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b338; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload339; CHECK-NEXT: mov p1.b, p2/m, p2.b340; CHECK-NEXT: and p0.b, p1/z, p1.b, p0.b341; CHECK-NEXT: addvl sp, sp, #1342; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload343; CHECK-NEXT: ret344 %r = tail call <vscale x 16 x i1> @llvm.experimental.vector.match(<vscale x 16 x i8> %op1, <32 x i8> %op2, <vscale x 16 x i1> %mask)345 ret <vscale x 16 x i1> %r346}347 348define <16 x i1> @match_v16i8_v32i8(<16 x i8> %op1, <32 x i8> %op2, <16 x i1> %mask) #0 {349; CHECK-LABEL: match_v16i8_v32i8:350; CHECK: // %bb.0:351; CHECK-NEXT: dup v4.16b, v1.b[1]352; CHECK-NEXT: dup v5.16b, v1.b[0]353; CHECK-NEXT: dup v6.16b, v1.b[2]354; CHECK-NEXT: dup v7.16b, v1.b[3]355; CHECK-NEXT: dup v16.16b, v1.b[4]356; CHECK-NEXT: dup v17.16b, v1.b[5]357; CHECK-NEXT: dup v18.16b, v1.b[6]358; CHECK-NEXT: dup v19.16b, v1.b[7]359; CHECK-NEXT: dup v20.16b, v1.b[8]360; CHECK-NEXT: cmeq v4.16b, v0.16b, v4.16b361; CHECK-NEXT: cmeq v5.16b, v0.16b, v5.16b362; CHECK-NEXT: cmeq v6.16b, v0.16b, v6.16b363; CHECK-NEXT: cmeq v7.16b, v0.16b, v7.16b364; CHECK-NEXT: cmeq v16.16b, v0.16b, v16.16b365; CHECK-NEXT: cmeq v17.16b, v0.16b, v17.16b366; CHECK-NEXT: dup v21.16b, v2.b[7]367; CHECK-NEXT: dup v22.16b, v1.b[10]368; CHECK-NEXT: orr v4.16b, v5.16b, v4.16b369; CHECK-NEXT: orr v5.16b, v6.16b, v7.16b370; CHECK-NEXT: orr v6.16b, v16.16b, v17.16b371; CHECK-NEXT: cmeq v7.16b, v0.16b, v18.16b372; CHECK-NEXT: cmeq v16.16b, v0.16b, v19.16b373; CHECK-NEXT: cmeq v17.16b, v0.16b, v20.16b374; CHECK-NEXT: dup v18.16b, v1.b[9]375; CHECK-NEXT: dup v19.16b, v1.b[11]376; CHECK-NEXT: dup v20.16b, v1.b[12]377; CHECK-NEXT: cmeq v22.16b, v0.16b, v22.16b378; CHECK-NEXT: orr v4.16b, v4.16b, v5.16b379; CHECK-NEXT: orr v5.16b, v6.16b, v7.16b380; CHECK-NEXT: orr v6.16b, v16.16b, v17.16b381; CHECK-NEXT: cmeq v7.16b, v0.16b, v18.16b382; CHECK-NEXT: dup v18.16b, v1.b[13]383; CHECK-NEXT: cmeq v16.16b, v0.16b, v19.16b384; CHECK-NEXT: cmeq v17.16b, v0.16b, v20.16b385; CHECK-NEXT: dup v19.16b, v2.b[0]386; CHECK-NEXT: dup v20.16b, v2.b[1]387; CHECK-NEXT: orr v4.16b, v4.16b, v5.16b388; CHECK-NEXT: dup v5.16b, v2.b[6]389; CHECK-NEXT: orr v6.16b, v6.16b, v7.16b390; CHECK-NEXT: orr v7.16b, v16.16b, v17.16b391; CHECK-NEXT: cmeq v16.16b, v0.16b, v18.16b392; CHECK-NEXT: cmeq v17.16b, v0.16b, v19.16b393; CHECK-NEXT: cmeq v18.16b, v0.16b, v20.16b394; CHECK-NEXT: dup v19.16b, v2.b[2]395; CHECK-NEXT: cmeq v5.16b, v0.16b, v5.16b396; CHECK-NEXT: cmeq v20.16b, v0.16b, v21.16b397; CHECK-NEXT: dup v21.16b, v2.b[8]398; CHECK-NEXT: orr v6.16b, v6.16b, v22.16b399; CHECK-NEXT: orr v7.16b, v7.16b, v16.16b400; CHECK-NEXT: dup v16.16b, v1.b[14]401; CHECK-NEXT: dup v1.16b, v1.b[15]402; CHECK-NEXT: orr v17.16b, v17.16b, v18.16b403; CHECK-NEXT: cmeq v18.16b, v0.16b, v19.16b404; CHECK-NEXT: dup v19.16b, v2.b[3]405; CHECK-NEXT: orr v5.16b, v5.16b, v20.16b406; CHECK-NEXT: cmeq v20.16b, v0.16b, v21.16b407; CHECK-NEXT: dup v21.16b, v2.b[9]408; CHECK-NEXT: cmeq v16.16b, v0.16b, v16.16b409; CHECK-NEXT: cmeq v1.16b, v0.16b, v1.16b410; CHECK-NEXT: orr v4.16b, v4.16b, v6.16b411; CHECK-NEXT: orr v17.16b, v17.16b, v18.16b412; CHECK-NEXT: cmeq v18.16b, v0.16b, v19.16b413; CHECK-NEXT: dup v19.16b, v2.b[4]414; CHECK-NEXT: orr v5.16b, v5.16b, v20.16b415; CHECK-NEXT: cmeq v20.16b, v0.16b, v21.16b416; CHECK-NEXT: dup v21.16b, v2.b[10]417; CHECK-NEXT: orr v7.16b, v7.16b, v16.16b418; CHECK-NEXT: orr v16.16b, v17.16b, v18.16b419; CHECK-NEXT: cmeq v17.16b, v0.16b, v19.16b420; CHECK-NEXT: dup v18.16b, v2.b[5]421; CHECK-NEXT: orr v5.16b, v5.16b, v20.16b422; CHECK-NEXT: cmeq v19.16b, v0.16b, v21.16b423; CHECK-NEXT: dup v20.16b, v2.b[11]424; CHECK-NEXT: orr v1.16b, v7.16b, v1.16b425; CHECK-NEXT: orr v6.16b, v16.16b, v17.16b426; CHECK-NEXT: cmeq v7.16b, v0.16b, v18.16b427; CHECK-NEXT: dup v17.16b, v2.b[12]428; CHECK-NEXT: orr v5.16b, v5.16b, v19.16b429; CHECK-NEXT: cmeq v16.16b, v0.16b, v20.16b430; CHECK-NEXT: dup v18.16b, v2.b[13]431; CHECK-NEXT: dup v19.16b, v2.b[14]432; CHECK-NEXT: orr v1.16b, v4.16b, v1.16b433; CHECK-NEXT: dup v2.16b, v2.b[15]434; CHECK-NEXT: orr v4.16b, v6.16b, v7.16b435; CHECK-NEXT: cmeq v6.16b, v0.16b, v17.16b436; CHECK-NEXT: orr v5.16b, v5.16b, v16.16b437; CHECK-NEXT: cmeq v7.16b, v0.16b, v18.16b438; CHECK-NEXT: cmeq v16.16b, v0.16b, v19.16b439; CHECK-NEXT: cmeq v0.16b, v0.16b, v2.16b440; CHECK-NEXT: orr v1.16b, v1.16b, v4.16b441; CHECK-NEXT: orr v4.16b, v5.16b, v6.16b442; CHECK-NEXT: orr v5.16b, v7.16b, v16.16b443; CHECK-NEXT: orr v1.16b, v1.16b, v4.16b444; CHECK-NEXT: orr v0.16b, v5.16b, v0.16b445; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b446; CHECK-NEXT: and v0.16b, v0.16b, v3.16b447; CHECK-NEXT: ret448 %r = tail call <16 x i1> @llvm.experimental.vector.match(<16 x i8> %op1, <32 x i8> %op2, <16 x i1> %mask)449 ret <16 x i1> %r450}451 452; Data types not supported by MATCH.453; Note: The cases for SVE could be made tighter.454 455define <vscale x 4 x i1> @match_nxv4xi32_v4i32(<vscale x 4 x i32> %op1, <4 x i32> %op2, <vscale x 4 x i1> %mask) #0 {456; CHECK-LABEL: match_nxv4xi32_v4i32:457; CHECK: // %bb.0:458; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill459; CHECK-NEXT: addvl sp, sp, #-1460; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill461; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 16 + 8 * VG462; CHECK-NEXT: .cfi_offset w29, -16463; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1464; CHECK-NEXT: mov z2.s, z1.s[1]465; CHECK-NEXT: mov z3.s, s1466; CHECK-NEXT: ptrue p1.s467; CHECK-NEXT: mov z4.s, z1.s[2]468; CHECK-NEXT: mov z1.s, z1.s[3]469; CHECK-NEXT: cmpeq p2.s, p1/z, z0.s, z2.s470; CHECK-NEXT: cmpeq p3.s, p1/z, z0.s, z3.s471; CHECK-NEXT: cmpeq p4.s, p1/z, z0.s, z4.s472; CHECK-NEXT: cmpeq p1.s, p1/z, z0.s, z1.s473; CHECK-NEXT: mov p2.b, p3/m, p3.b474; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b475; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload476; CHECK-NEXT: mov p1.b, p2/m, p2.b477; CHECK-NEXT: and p0.b, p1/z, p1.b, p0.b478; CHECK-NEXT: addvl sp, sp, #1479; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload480; CHECK-NEXT: ret481 %r = tail call <vscale x 4 x i1> @llvm.experimental.vector.match(<vscale x 4 x i32> %op1, <4 x i32> %op2, <vscale x 4 x i1> %mask)482 ret <vscale x 4 x i1> %r483}484 485define <vscale x 2 x i1> @match_nxv2xi64_v2i64(<vscale x 2 x i64> %op1, <2 x i64> %op2, <vscale x 2 x i1> %mask) #0 {486; CHECK-LABEL: match_nxv2xi64_v2i64:487; CHECK: // %bb.0:488; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1489; CHECK-NEXT: mov z2.d, z1.d[1]490; CHECK-NEXT: ptrue p1.d491; CHECK-NEXT: mov z1.d, d1492; CHECK-NEXT: cmpeq p2.d, p1/z, z0.d, z2.d493; CHECK-NEXT: cmpeq p1.d, p1/z, z0.d, z1.d494; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b495; CHECK-NEXT: and p0.b, p1/z, p1.b, p0.b496; CHECK-NEXT: ret497 %r = tail call <vscale x 2 x i1> @llvm.experimental.vector.match(<vscale x 2 x i64> %op1, <2 x i64> %op2, <vscale x 2 x i1> %mask)498 ret <vscale x 2 x i1> %r499}500 501define <4 x i1> @match_v4xi32_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) #0 {502; CHECK-LABEL: match_v4xi32_v4i32:503; CHECK: // %bb.0:504; CHECK-NEXT: dup v3.4s, v1.s[1]505; CHECK-NEXT: dup v4.4s, v1.s[0]506; CHECK-NEXT: dup v5.4s, v1.s[2]507; CHECK-NEXT: dup v1.4s, v1.s[3]508; CHECK-NEXT: cmeq v3.4s, v0.4s, v3.4s509; CHECK-NEXT: cmeq v4.4s, v0.4s, v4.4s510; CHECK-NEXT: cmeq v5.4s, v0.4s, v5.4s511; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s512; CHECK-NEXT: orr v1.16b, v4.16b, v3.16b513; CHECK-NEXT: orr v0.16b, v5.16b, v0.16b514; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b515; CHECK-NEXT: xtn v0.4h, v0.4s516; CHECK-NEXT: and v0.8b, v0.8b, v2.8b517; CHECK-NEXT: ret518 %r = tail call <4 x i1> @llvm.experimental.vector.match(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask)519 ret <4 x i1> %r520}521 522define <2 x i1> @match_v2xi64_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) #0 {523; CHECK-LABEL: match_v2xi64_v2i64:524; CHECK: // %bb.0:525; CHECK-NEXT: dup v3.2d, v1.d[1]526; CHECK-NEXT: dup v1.2d, v1.d[0]527; CHECK-NEXT: cmeq v3.2d, v0.2d, v3.2d528; CHECK-NEXT: cmeq v0.2d, v0.2d, v1.2d529; CHECK-NEXT: orr v0.16b, v0.16b, v3.16b530; CHECK-NEXT: xtn v0.2s, v0.2d531; CHECK-NEXT: and v0.8b, v0.8b, v2.8b532; CHECK-NEXT: ret533 %r = tail call <2 x i1> @llvm.experimental.vector.match(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask)534 ret <2 x i1> %r535}536 537attributes #0 = { "target-features"="+sve2" }538