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1; RUN: llc < %s -mtriple=aarch64 -O=3 | FileCheck %s2 3define void @test() {4 ; CHECK: dmb sy5 call void @llvm.aarch64.dmb(i32 15)6 ; CHECK: dmb osh7 call void @llvm.aarch64.dmb(i32 3)8 ; CHECK: dsb sy9 call void @llvm.aarch64.dsb(i32 15)10 ; CHECK: dsb ishld11 call void @llvm.aarch64.dsb(i32 9)12 ; CHECK: isb13 call void @llvm.aarch64.isb(i32 15)14 ret void15}16 17; Important point is that the compiler should not reorder memory access18; instructions around DMB.19; Failure to do so, two STRs will collapse into one STP.20define void @test_dmb_reordering(i32 %a, i32 %b, ptr %d) {21 store i32 %a, ptr %d ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}]22 23 call void @llvm.aarch64.dmb(i32 15); CHECK: dmb sy24 25 %d1 = getelementptr i32, ptr %d, i64 126 store i32 %b, ptr %d1 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4]27 28 ret void29}30 31; Similarly for DSB.32define void @test_dsb_reordering(i32 %a, i32 %b, ptr %d) {33 store i32 %a, ptr %d ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}]34 35 call void @llvm.aarch64.dsb(i32 15); CHECK: dsb sy36 37 %d1 = getelementptr i32, ptr %d, i64 138 store i32 %b, ptr %d1 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4]39 40 ret void41}42 43; And ISB.44define void @test_isb_reordering(i32 %a, i32 %b, ptr %d) {45 store i32 %a, ptr %d ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}]46 47 call void @llvm.aarch64.isb(i32 15); CHECK: isb48 49 %d1 = getelementptr i32, ptr %d, i64 150 store i32 %b, ptr %d1 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4]51 52 ret void53}54 55declare void @llvm.aarch64.dmb(i32)56declare void @llvm.aarch64.dsb(i32)57declare void @llvm.aarch64.isb(i32)58