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1; RUN: llc -no-integrated-as -verify-machineinstrs -o - %s -aarch64-min-jump-table-entries=4 -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s2; RUN: llc -no-integrated-as -code-model=large -verify-machineinstrs -o - %s -aarch64-min-jump-table-entries=4 -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-LARGE %s3; RUN: llc -no-integrated-as -code-model=large -relocation-model=pic -o - %s -aarch64-min-jump-table-entries=4 -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-PIC %s4; RUN: llc -no-integrated-as -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -relocation-model=pic -aarch64-min-jump-table-entries=4 -aarch64-enable-atomic-cfg-tidy=0 -o - %s | FileCheck --check-prefix=CHECK-PIC %s5; RUN: llc -no-integrated-as -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios -aarch64-min-jump-table-entries=4 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-IOS %s6; RUN: llc -no-integrated-as -code-model=tiny -verify-machineinstrs -o - %s -aarch64-min-jump-table-entries=4 -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-TINY %s7 8define i32 @test_jumptable(i32 %in) {9; CHECK: test_jumptable10 11 switch i32 %in, label %def [12 i32 0, label %lbl113 i32 1, label %lbl214 i32 2, label %lbl315 i32 4, label %lbl416 ]17; CHECK-LABEL: test_jumptable:18; CHECK: adrp [[JTPAGE:x[0-9]+]], .LJTI0_019; CHECK: add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI0_020; CHECK: adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]]21; CHECK: ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}]22; CHECK: add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #223; CHECK: br [[DEST]]24 25; CHECK-LARGE: movz x[[JTADDR:[0-9]+]], #:abs_g0_nc:.LJTI0_026; CHECK-LARGE: movk x[[JTADDR]], #:abs_g1_nc:.LJTI0_027; CHECK-LARGE: movk x[[JTADDR]], #:abs_g2_nc:.LJTI0_028; CHECK-LARGE: movk x[[JTADDR]], #:abs_g3:.LJTI0_029; CHECK-LARGE: adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]]30; CHECK-LARGE: ldrb w[[OFFSET:[0-9]+]], [x[[JTADDR]], {{x[0-9]+}}]31; CHECK-LARGE: add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #232; CHECK-LARGE: br [[DEST]]33 34; CHECK-PIC-LABEL: test_jumptable:35; CHECK-PIC: adrp [[JTPAGE:x[0-9]+]], .LJTI0_036; CHECK-PIC: add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI0_037; CHECK-PIC: adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]]38; CHECK-PIC: ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}]39; CHECK-PIC: add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #240; CHECK-PIC: br [[DEST]]41 42; CHECK-IOS: adrp [[JTPAGE:x[0-9]+]], LJTI0_0@PAGE43; CHECK-IOS: add x[[JT:[0-9]+]], [[JTPAGE]], LJTI0_0@PAGEOFF44; CHECK-IOS: adr [[PCBASE:x[0-9]+]], [[JTBASE:LBB[0-9]+_[0-9]+]]45; CHECK-IOS: ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}]46; CHECK-IOS: add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #247; CHECK-IOS: br [[DEST]]48 49; CHECK-TINY-LABEL: test_jumptable:50; CHECK-TINY: adr x[[JT:[0-9]+]], .LJTI0_051; CHECK-TINY: adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]]52; CHECK-TINY: ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}]53; CHECK-TINY: add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #254; CHECK-TINY: br [[DEST]]55 56 57def:58 ret i32 059 60lbl1:61 ret i32 162 63lbl2:64 ret i32 265 66lbl3:67 ret i32 468 69lbl4:70 ret i32 871 72}73 74; CHECK: .rodata75 76; CHECK: .LJTI0_0:77; CHECK-NEXT: .byte ([[JTBASE]]-[[JTBASE]])>>278; CHECK-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>279; CHECK-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>280; CHECK-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>281; CHECK-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>282 83define i32 @test_jumptable16(i32 %in) {84 85 switch i32 %in, label %def [86 i32 0, label %lbl187 i32 1, label %lbl288 i32 2, label %lbl389 i32 4, label %lbl490 ]91; CHECK-LABEL: test_jumptable16:92; CHECK: adrp [[JTPAGE:x[0-9]+]], .LJTI1_093; CHECK: add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI1_094; CHECK: adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]]95; CHECK: ldrh w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #1]96; CHECK: add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #297; CHECK: br [[DEST]]98 99def:100 ret i32 0101 102lbl1:103 ret i32 1104 105lbl2:106 call i64 @llvm.aarch64.space(i32 1024, i64 undef)107 ret i32 2108 109lbl3:110 ret i32 4111 112lbl4:113 ret i32 8114 115}116 117; CHECK: .rodata118; CHECK: .p2align 1119; CHECK: .LJTI1_0:120; CHECK-NEXT: .hword ([[JTBASE]]-[[JTBASE]])>>2121; CHECK-NEXT: .hword (.LBB{{.*}}-[[JTBASE]])>>2122; CHECK-NEXT: .hword (.LBB{{.*}}-[[JTBASE]])>>2123; CHECK-NEXT: .hword (.LBB{{.*}}-[[JTBASE]])>>2124; CHECK-NEXT: .hword (.LBB{{.*}}-[[JTBASE]])>>2125 126; CHECK-PIC-NOT: .data_region127; CHECK-PIC-NOT: .LJTI0_0128; CHECK-PIC: .LJTI0_0:129; CHECK-PIC-NEXT: .byte ([[JTBASE]]-[[JTBASE]])>>2130; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2131; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2132; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2133; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2134; CHECK-PIC-NOT: .end_data_region135 136; CHECK-IOS: .section __TEXT,__const137; CHECK-IOS-NOT: .data_region138; CHECK-IOS: LJTI0_0:139; CHECK-IOS-NEXT: .byte ([[JTBASE]]-[[JTBASE]])>>2140; CHECK-IOS-NEXT: .byte (LBB{{.*}}-[[JTBASE]])>>2141; CHECK-IOS-NEXT: .byte (LBB{{.*}}-[[JTBASE]])>>2142; CHECK-IOS-NEXT: .byte (LBB{{.*}}-[[JTBASE]])>>2143; CHECK-IOS-NEXT: .byte (LBB{{.*}}-[[JTBASE]])>>2144; CHECK-IOS-NOT: .end_data_region145 146; Compressing just the first table has the opportunity to truncate the vector of147; sizes. Make sure it doesn't.148define i32 @test_twotables(i32 %in1, i32 %in2) {149; CHECK-LABEL: test_twotables:150; CHECK: .LJTI2_0151; CHECK: .LJTI2_1152 153 switch i32 %in1, label %def [154 i32 0, label %lbl1155 i32 1, label %lbl2156 i32 2, label %lbl3157 i32 4, label %lbl4158 ]159 160def:161 ret i32 0162 163lbl1:164 ret i32 1165 166lbl2:167 ret i32 2168 169lbl3:170 ret i32 4171 172lbl4:173 switch i32 %in1, label %def [174 i32 0, label %lbl5175 i32 1, label %lbl6176 i32 2, label %lbl7177 i32 4, label %lbl8178 ]179 180lbl5:181 call i64 @llvm.aarch64.space(i32 262144, i64 undef)182 ret i32 1183 184lbl6:185 call i64 @llvm.aarch64.space(i32 262144, i64 undef)186 ret i32 2187 188lbl7:189 call i64 @llvm.aarch64.space(i32 262144, i64 undef)190 ret i32 4191lbl8:192 call i64 @llvm.aarch64.space(i32 262144, i64 undef)193 ret i32 8194 195}196 197declare i64 @llvm.aarch64.space(i32, i64)198