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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc < %s -O3 -mtriple=aarch64 | FileCheck %s3 4; From #164775, this generates a pre-index load feeding a post-index store, that5; was checking the wrong uses for post-inc. It seems quite delicate for it to6; generate this combination at the wrong point to hit the same issue.7 8@g_260 = dso_local global i16 09@g_480 = dso_local global i16 010 11define i32 @func_1(ptr %l_3253) {12; CHECK-LABEL: func_1:13; CHECK: // %bb.0: // %entry14; CHECK-NEXT: sub sp, sp, #12815; CHECK-NEXT: .cfi_def_cfa_offset 12816; CHECK-NEXT: movi v0.2d, #000000000000000017; CHECK-NEXT: mov w9, #2 // =0x218; CHECK-NEXT: mov w10, #96 // =0x6019; CHECK-NEXT: strb wzr, [x9]20; CHECK-NEXT: mov w9, #111 // =0x6f21; CHECK-NEXT: mov x8, xzr22; CHECK-NEXT: str wzr, [x9]23; CHECK-NEXT: mov w9, #80 // =0x5024; CHECK-NEXT: adrp x1, .L_MergedGlobals25; CHECK-NEXT: add x1, x1, :lo12:.L_MergedGlobals26; CHECK-NEXT: strh wzr, [x8]27; CHECK-NEXT: str q0, [x9]28; CHECK-NEXT: mov w9, #48 // =0x3029; CHECK-NEXT: str q0, [x9]30; CHECK-NEXT: mov w9, #32 // =0x2031; CHECK-NEXT: str q0, [x10]32; CHECK-NEXT: mov w10, #64 // =0x4033; CHECK-NEXT: str q0, [x9]34; CHECK-NEXT: mov w9, #16 // =0x1035; CHECK-NEXT: str q0, [x10]36; CHECK-NEXT: str q0, [x9]37; CHECK-NEXT: str q0, [x8]38; CHECK-NEXT: adrp x8, .L_MergedGlobals39; CHECK-NEXT: strb wzr, [x0, #8]40; CHECK-NEXT: strb wzr, [x0, #12]41; CHECK-NEXT: strb wzr, [x0, #16]42; CHECK-NEXT: strb wzr, [x0, #20]43; CHECK-NEXT: mov w0, wzr44; CHECK-NEXT: ldrh wzr, [x8, :lo12:.L_MergedGlobals]45; CHECK-NEXT: ldrh w8, [x1, #4]!46; CHECK-NEXT: sub w8, w8, #147; CHECK-NEXT: strh w8, [x1]48; CHECK-NEXT: add sp, sp, #12849; CHECK-NEXT: b use50entry:51 %l_32531.sroa.3 = alloca [3 x i8], align 452 %l_32531.sroa.4 = alloca [115 x i8], align 453 call void @llvm.lifetime.start.p0(ptr %l_32531.sroa.3)54 call void @llvm.lifetime.start.p0(ptr %l_32531.sroa.4)55 call void @llvm.memset.p0.i64(ptr null, i8 0, i64 3, i1 false)56 call void @llvm.memset.p0.i64(ptr null, i8 0, i64 115, i1 false)57 %0 = getelementptr inbounds i8, ptr %l_3253, i64 858 store i8 0, ptr %0, align 459 %1 = getelementptr inbounds i8, ptr %l_3253, i64 1260 store i8 0, ptr %1, align 461 %2 = getelementptr inbounds i8, ptr %l_3253, i64 1662 store i8 0, ptr %2, align 463 %3 = getelementptr inbounds i8, ptr %l_3253, i64 2064 store i8 0, ptr %3, align 465 %4 = load volatile i16, ptr @g_260, align 466 %5 = load i16, ptr @g_480, align 467 %dec.i.i = add i16 %5, -168 store i16 %dec.i.i, ptr @g_480, align 469 %call1 = tail call i32 @use(i32 0, ptr @g_480)70 ret i32 %call171}72 73declare i32 @use(i32, ptr)74