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1; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu | FileCheck %s2; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s3 4@var_8bit = global i8 05@var_16bit = global i16 06@var_32bit = global i32 07@var_64bit = global i64 08 9@var_float = global float 0.010@var_double = global double 0.011 12define void @ldst_8bit(ptr %base, i32 %off32, i64 %off64) minsize {13; CHECK-LABEL: ldst_8bit:14 15 %addr8_sxtw = getelementptr i8, ptr %base, i32 %off3216 %val8_sxtw = load volatile i8, ptr %addr8_sxtw17 %val32_signed = sext i8 %val8_sxtw to i3218 store volatile i32 %val32_signed, ptr @var_32bit19; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{[wx][0-9]+}}, sxtw]20 21 %addr_lsl = getelementptr i8, ptr %base, i64 %off6422 %val8_lsl = load volatile i8, ptr %addr_lsl23 %val32_unsigned = zext i8 %val8_lsl to i3224 store volatile i32 %val32_unsigned, ptr @var_32bit25; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]26 27 %addrint_uxtw = ptrtoint ptr %base to i6428 %offset_uxtw = zext i32 %off32 to i6429 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw30 %addr_uxtw = inttoptr i64 %addrint1_uxtw to ptr31 %val8_uxtw = load volatile i8, ptr %addr_uxtw32 %newval8 = add i8 %val8_uxtw, 133 store volatile i8 %newval8, ptr @var_8bit34; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw]35 36 ret void37}38 39 40define void @ldst_16bit(ptr %base, i32 %off32, i64 %off64) minsize {41; CHECK-LABEL: ldst_16bit:42 43 %addr8_sxtwN = getelementptr i16, ptr %base, i32 %off3244 %val8_sxtwN = load volatile i16, ptr %addr8_sxtwN45 %val32_signed = sext i16 %val8_sxtwN to i3246 store volatile i32 %val32_signed, ptr @var_32bit47; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #1]48 49 %addr_lslN = getelementptr i16, ptr %base, i64 %off6450 %val8_lslN = load volatile i16, ptr %addr_lslN51 %val32_unsigned = zext i16 %val8_lslN to i3252 store volatile i32 %val32_unsigned, ptr @var_32bit53; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #1]54 55 %addrint_uxtw = ptrtoint ptr %base to i6456 %offset_uxtw = zext i32 %off32 to i6457 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw58 %addr_uxtw = inttoptr i64 %addrint1_uxtw to ptr59 %val8_uxtw = load volatile i16, ptr %addr_uxtw60 %newval8 = add i16 %val8_uxtw, 161 store volatile i16 %newval8, ptr @var_16bit62; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw]63 64 %base_sxtw = ptrtoint ptr %base to i6465 %offset_sxtw = sext i32 %off32 to i6466 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw67 %addr_sxtw = inttoptr i64 %addrint_sxtw to ptr68 %val16_sxtw = load volatile i16, ptr %addr_sxtw69 %val64_signed = sext i16 %val16_sxtw to i6470 store volatile i64 %val64_signed, ptr @var_64bit71; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{[wx][0-9]+}}, sxtw]72 73 74 %base_lsl = ptrtoint ptr %base to i6475 %addrint_lsl = add i64 %base_lsl, %off6476 %addr_lsl = inttoptr i64 %addrint_lsl to ptr77 %val16_lsl = load volatile i16, ptr %addr_lsl78 %val64_unsigned = zext i16 %val16_lsl to i6479 store volatile i64 %val64_unsigned, ptr @var_64bit80; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]81 82 %base_uxtwN = ptrtoint ptr %base to i6483 %offset_uxtwN = zext i32 %off32 to i6484 %offset2_uxtwN = shl i64 %offset_uxtwN, 185 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN86 %addr_uxtwN = inttoptr i64 %addrint_uxtwN to ptr87 %val32 = load volatile i32, ptr @var_32bit88 %val16_trunc32 = trunc i32 %val32 to i1689 store volatile i16 %val16_trunc32, ptr %addr_uxtwN90; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #1]91 ret void92}93 94define void @ldst_32bit(ptr %base, i32 %off32, i64 %off64) minsize {95; CHECK-LABEL: ldst_32bit:96 97 %addr_sxtwN = getelementptr i32, ptr %base, i32 %off3298 %val_sxtwN = load volatile i32, ptr %addr_sxtwN99 store volatile i32 %val_sxtwN, ptr @var_32bit100; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #2]101 102 %addr_lslN = getelementptr i32, ptr %base, i64 %off64103 %val_lslN = load volatile i32, ptr %addr_lslN104 store volatile i32 %val_lslN, ptr @var_32bit105; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #2]106 107 %addrint_uxtw = ptrtoint ptr %base to i64108 %offset_uxtw = zext i32 %off32 to i64109 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw110 %addr_uxtw = inttoptr i64 %addrint1_uxtw to ptr111 %val_uxtw = load volatile i32, ptr %addr_uxtw112 %newval8 = add i32 %val_uxtw, 1113 store volatile i32 %newval8, ptr @var_32bit114; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw]115 116 117 %base_sxtw = ptrtoint ptr %base to i64118 %offset_sxtw = sext i32 %off32 to i64119 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw120 %addr_sxtw = inttoptr i64 %addrint_sxtw to ptr121 %val16_sxtw = load volatile i32, ptr %addr_sxtw122 %val64_signed = sext i32 %val16_sxtw to i64123 store volatile i64 %val64_signed, ptr @var_64bit124; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]125 126 127 %base_lsl = ptrtoint ptr %base to i64128 %addrint_lsl = add i64 %base_lsl, %off64129 %addr_lsl = inttoptr i64 %addrint_lsl to ptr130 %val16_lsl = load volatile i32, ptr %addr_lsl131 %val64_unsigned = zext i32 %val16_lsl to i64132 store volatile i64 %val64_unsigned, ptr @var_64bit133; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]134 135 %base_uxtwN = ptrtoint ptr %base to i64136 %offset_uxtwN = zext i32 %off32 to i64137 %offset2_uxtwN = shl i64 %offset_uxtwN, 2138 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN139 %addr_uxtwN = inttoptr i64 %addrint_uxtwN to ptr140 %val32 = load volatile i32, ptr @var_32bit141 store volatile i32 %val32, ptr %addr_uxtwN142; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #2]143 ret void144}145 146define void @ldst_64bit(ptr %base, i32 %off32, i64 %off64) minsize {147; CHECK-LABEL: ldst_64bit:148 149 %addr_sxtwN = getelementptr i64, ptr %base, i32 %off32150 %val_sxtwN = load volatile i64, ptr %addr_sxtwN151 store volatile i64 %val_sxtwN, ptr @var_64bit152; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #3]153 154 %addr_lslN = getelementptr i64, ptr %base, i64 %off64155 %val_lslN = load volatile i64, ptr %addr_lslN156 store volatile i64 %val_lslN, ptr @var_64bit157; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #3]158 159 %addrint_uxtw = ptrtoint ptr %base to i64160 %offset_uxtw = zext i32 %off32 to i64161 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw162 %addr_uxtw = inttoptr i64 %addrint1_uxtw to ptr163 %val8_uxtw = load volatile i64, ptr %addr_uxtw164 %newval8 = add i64 %val8_uxtw, 1165 store volatile i64 %newval8, ptr @var_64bit166; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw]167 168 %base_sxtw = ptrtoint ptr %base to i64169 %offset_sxtw = sext i32 %off32 to i64170 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw171 %addr_sxtw = inttoptr i64 %addrint_sxtw to ptr172 %val64_sxtw = load volatile i64, ptr %addr_sxtw173 store volatile i64 %val64_sxtw, ptr @var_64bit174; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]175 176 %base_lsl = ptrtoint ptr %base to i64177 %addrint_lsl = add i64 %base_lsl, %off64178 %addr_lsl = inttoptr i64 %addrint_lsl to ptr179 %val64_lsl = load volatile i64, ptr %addr_lsl180 store volatile i64 %val64_lsl, ptr @var_64bit181; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]182 183 %base_uxtwN = ptrtoint ptr %base to i64184 %offset_uxtwN = zext i32 %off32 to i64185 %offset2_uxtwN = shl i64 %offset_uxtwN, 3186 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN187 %addr_uxtwN = inttoptr i64 %addrint_uxtwN to ptr188 %val64 = load volatile i64, ptr @var_64bit189 store volatile i64 %val64, ptr %addr_uxtwN190; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #3]191 ret void192}193 194define void @ldst_float(ptr %base, i32 %off32, i64 %off64) minsize {195; CHECK-LABEL: ldst_float:196 197 %addr_sxtwN = getelementptr float, ptr %base, i32 %off32198 %val_sxtwN = load volatile float, ptr %addr_sxtwN199 store volatile float %val_sxtwN, ptr @var_float200; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #2]201; CHECK-NOFP-NOT: ldr {{s[0-9]+}},202 203 %addr_lslN = getelementptr float, ptr %base, i64 %off64204 %val_lslN = load volatile float, ptr %addr_lslN205 store volatile float %val_lslN, ptr @var_float206; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #2]207; CHECK-NOFP-NOT: ldr {{s[0-9]+}},208 209 %addrint_uxtw = ptrtoint ptr %base to i64210 %offset_uxtw = zext i32 %off32 to i64211 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw212 %addr_uxtw = inttoptr i64 %addrint1_uxtw to ptr213 %val_uxtw = load volatile float, ptr %addr_uxtw214 store volatile float %val_uxtw, ptr @var_float215; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw]216; CHECK-NOFP-NOT: ldr {{s[0-9]+}},217 218 %base_sxtw = ptrtoint ptr %base to i64219 %offset_sxtw = sext i32 %off32 to i64220 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw221 %addr_sxtw = inttoptr i64 %addrint_sxtw to ptr222 %val64_sxtw = load volatile float, ptr %addr_sxtw223 store volatile float %val64_sxtw, ptr @var_float224; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]225; CHECK-NOFP-NOT: ldr {{s[0-9]+}},226 227 %base_lsl = ptrtoint ptr %base to i64228 %addrint_lsl = add i64 %base_lsl, %off64229 %addr_lsl = inttoptr i64 %addrint_lsl to ptr230 %val64_lsl = load volatile float, ptr %addr_lsl231 store volatile float %val64_lsl, ptr @var_float232; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]233; CHECK-NOFP-NOT: ldr {{s[0-9]+}},234 235 %base_uxtwN = ptrtoint ptr %base to i64236 %offset_uxtwN = zext i32 %off32 to i64237 %offset2_uxtwN = shl i64 %offset_uxtwN, 2238 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN239 %addr_uxtwN = inttoptr i64 %addrint_uxtwN to ptr240 %val64 = load volatile float, ptr @var_float241 store volatile float %val64, ptr %addr_uxtwN242; CHECK: str {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #2]243; CHECK-NOFP-NOT: ldr {{s[0-9]+}},244 ret void245}246 247define void @ldst_double(ptr %base, i32 %off32, i64 %off64) minsize {248; CHECK-LABEL: ldst_double:249 250 %addr_sxtwN = getelementptr double, ptr %base, i32 %off32251 %val_sxtwN = load volatile double, ptr %addr_sxtwN252 store volatile double %val_sxtwN, ptr @var_double253; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #3]254; CHECK-NOFP-NOT: ldr {{d[0-9]+}},255 256 %addr_lslN = getelementptr double, ptr %base, i64 %off64257 %val_lslN = load volatile double, ptr %addr_lslN258 store volatile double %val_lslN, ptr @var_double259; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #3]260; CHECK-NOFP-NOT: ldr {{d[0-9]+}},261 262 %addrint_uxtw = ptrtoint ptr %base to i64263 %offset_uxtw = zext i32 %off32 to i64264 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw265 %addr_uxtw = inttoptr i64 %addrint1_uxtw to ptr266 %val_uxtw = load volatile double, ptr %addr_uxtw267 store volatile double %val_uxtw, ptr @var_double268; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw]269; CHECK-NOFP-NOT: ldr {{d[0-9]+}},270 271 %base_sxtw = ptrtoint ptr %base to i64272 %offset_sxtw = sext i32 %off32 to i64273 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw274 %addr_sxtw = inttoptr i64 %addrint_sxtw to ptr275 %val64_sxtw = load volatile double, ptr %addr_sxtw276 store volatile double %val64_sxtw, ptr @var_double277; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]278; CHECK-NOFP-NOT: ldr {{d[0-9]+}},279 280 %base_lsl = ptrtoint ptr %base to i64281 %addrint_lsl = add i64 %base_lsl, %off64282 %addr_lsl = inttoptr i64 %addrint_lsl to ptr283 %val64_lsl = load volatile double, ptr %addr_lsl284 store volatile double %val64_lsl, ptr @var_double285; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]286; CHECK-NOFP-NOT: ldr {{d[0-9]+}},287 288 %base_uxtwN = ptrtoint ptr %base to i64289 %offset_uxtwN = zext i32 %off32 to i64290 %offset2_uxtwN = shl i64 %offset_uxtwN, 3291 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN292 %addr_uxtwN = inttoptr i64 %addrint_uxtwN to ptr293 %val64 = load volatile double, ptr @var_double294 store volatile double %val64, ptr %addr_uxtwN295; CHECK: str {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #3]296; CHECK-NOFP-NOT: ldr {{d[0-9]+}},297 ret void298}299 300 301define void @ldst_128bit(ptr %base, i32 %off32, i64 %off64) minsize {302; CHECK-LABEL: ldst_128bit:303 304 %addr_sxtwN = getelementptr fp128, ptr %base, i32 %off32305 %val_sxtwN = load volatile fp128, ptr %addr_sxtwN306 store volatile fp128 %val_sxtwN, ptr %base307; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4]308; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4]309 310 %addr_lslN = getelementptr fp128, ptr %base, i64 %off64311 %val_lslN = load volatile fp128, ptr %addr_lslN312 store volatile fp128 %val_lslN, ptr %base313; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #4]314; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4]315 316 %addrint_uxtw = ptrtoint ptr %base to i64317 %offset_uxtw = zext i32 %off32 to i64318 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw319 %addr_uxtw = inttoptr i64 %addrint1_uxtw to ptr320 %val_uxtw = load volatile fp128, ptr %addr_uxtw321 store volatile fp128 %val_uxtw, ptr %base322; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw]323; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4]324 325 %base_sxtw = ptrtoint ptr %base to i64326 %offset_sxtw = sext i32 %off32 to i64327 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw328 %addr_sxtw = inttoptr i64 %addrint_sxtw to ptr329 %val64_sxtw = load volatile fp128, ptr %addr_sxtw330 store volatile fp128 %val64_sxtw, ptr %base331; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]332; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4]333 334 %base_lsl = ptrtoint ptr %base to i64335 %addrint_lsl = add i64 %base_lsl, %off64336 %addr_lsl = inttoptr i64 %addrint_lsl to ptr337 %val64_lsl = load volatile fp128, ptr %addr_lsl338 store volatile fp128 %val64_lsl, ptr %base339; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}]340; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4]341 342 %base_uxtwN = ptrtoint ptr %base to i64343 %offset_uxtwN = zext i32 %off32 to i64344 %offset2_uxtwN = shl i64 %offset_uxtwN, 4345 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN346 %addr_uxtwN = inttoptr i64 %addrint_uxtwN to ptr347 %val64 = load volatile fp128, ptr %base348 store volatile fp128 %val64, ptr %addr_uxtwN349; CHECK: str {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #4]350; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4]351 ret void352}353