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1; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s2; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s3 4@var_8bit = dso_local global i8 05@var_16bit = dso_local global i16 06@var_32bit = dso_local global i32 07@var_64bit = dso_local global i64 08 9@var_float = dso_local global float 0.010@var_double = dso_local global double 0.011 12@varptr = dso_local global ptr null13 14define dso_local void @ldst_8bit() {15; CHECK-LABEL: ldst_8bit:16 17; No architectural support for loads to 16-bit or 8-bit since we18; promote i8 during lowering.19 %addr_8bit = load ptr, ptr @varptr20 21; match a sign-extending load 8-bit -> 32-bit22 %addr_sext32 = getelementptr i8, ptr %addr_8bit, i64 -25623 %val8_sext32 = load volatile i8, ptr %addr_sext3224 %val32_signed = sext i8 %val8_sext32 to i3225 store volatile i32 %val32_signed, ptr @var_32bit26; CHECK: ldursb {{w[0-9]+}}, [{{x[0-9]+}}, #-256]27 28; match a zero-extending load volatile 8-bit -> 32-bit29 %addr_zext32 = getelementptr i8, ptr %addr_8bit, i64 -1230 %val8_zext32 = load volatile i8, ptr %addr_zext3231 %val32_unsigned = zext i8 %val8_zext32 to i3232 store volatile i32 %val32_unsigned, ptr @var_32bit33; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-12]34 35; match an any-extending load volatile 8-bit -> 32-bit36 %addr_anyext = getelementptr i8, ptr %addr_8bit, i64 -137 %val8_anyext = load volatile i8, ptr %addr_anyext38 %newval8 = add i8 %val8_anyext, 139 store volatile i8 %newval8, ptr @var_8bit40; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-1]41 42; match a sign-extending load volatile 8-bit -> 64-bit43 %addr_sext64 = getelementptr i8, ptr %addr_8bit, i64 -544 %val8_sext64 = load volatile i8, ptr %addr_sext6445 %val64_signed = sext i8 %val8_sext64 to i6446 store volatile i64 %val64_signed, ptr @var_64bit47; CHECK: ldursb {{x[0-9]+}}, [{{x[0-9]+}}, #-5]48 49; match a zero-extending load volatile 8-bit -> 64-bit.50; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits51; of x0 so it's identical to load volatileing to 32-bits.52 %addr_zext64 = getelementptr i8, ptr %addr_8bit, i64 -953 %val8_zext64 = load volatile i8, ptr %addr_zext6454 %val64_unsigned = zext i8 %val8_zext64 to i6455 store volatile i64 %val64_unsigned, ptr @var_64bit56; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-9]57 58; truncating store volatile 32-bits to 8-bits59 %addr_trunc32 = getelementptr i8, ptr %addr_8bit, i64 -25660 %val32 = load volatile i32, ptr @var_32bit61 %val8_trunc32 = trunc i32 %val32 to i862 store volatile i8 %val8_trunc32, ptr %addr_trunc3263; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-256]64 65; truncating store volatile 64-bits to 8-bits66 %addr_trunc64 = getelementptr i8, ptr %addr_8bit, i64 -167 %val64 = load volatile i64, ptr @var_64bit68 %val8_trunc64 = trunc i64 %val64 to i869 store volatile i8 %val8_trunc64, ptr %addr_trunc6470; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-1]71 72 ret void73}74 75define dso_local void @ldst_16bit() {76; CHECK-LABEL: ldst_16bit:77 78; No architectural support for loads to 16-bit or 16-bit since we79; promote i16 during lowering.80 %addr_8bit = load ptr, ptr @varptr81 82; match a sign-extending load 16-bit -> 32-bit83 %addr8_sext32 = getelementptr i8, ptr %addr_8bit, i64 -25684 %val16_sext32 = load volatile i16, ptr %addr8_sext3285 %val32_signed = sext i16 %val16_sext32 to i3286 store volatile i32 %val32_signed, ptr @var_32bit87; CHECK: ldursh {{w[0-9]+}}, [{{x[0-9]+}}, #-256]88 89; match a zero-extending load volatile 16-bit -> 32-bit. With offset that would be unaligned.90 %addr8_zext32 = getelementptr i8, ptr %addr_8bit, i64 1591 %val16_zext32 = load volatile i16, ptr %addr8_zext3292 %val32_unsigned = zext i16 %val16_zext32 to i3293 store volatile i32 %val32_unsigned, ptr @var_32bit94; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #15]95 96; match an any-extending load volatile 16-bit -> 32-bit97 %addr8_anyext = getelementptr i8, ptr %addr_8bit, i64 -198 %val16_anyext = load volatile i16, ptr %addr8_anyext99 %newval16 = add i16 %val16_anyext, 1100 store volatile i16 %newval16, ptr @var_16bit101; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-1]102 103; match a sign-extending load volatile 16-bit -> 64-bit104 %addr8_sext64 = getelementptr i8, ptr %addr_8bit, i64 -5105 %val16_sext64 = load volatile i16, ptr %addr8_sext64106 %val64_signed = sext i16 %val16_sext64 to i64107 store volatile i64 %val64_signed, ptr @var_64bit108; CHECK: ldursh {{x[0-9]+}}, [{{x[0-9]+}}, #-5]109 110; match a zero-extending load volatile 16-bit -> 64-bit.111; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits112; of x0 so it's identical to load volatileing to 32-bits.113 %addr8_zext64 = getelementptr i8, ptr %addr_8bit, i64 9114 %val16_zext64 = load volatile i16, ptr %addr8_zext64115 %val64_unsigned = zext i16 %val16_zext64 to i64116 store volatile i64 %val64_unsigned, ptr @var_64bit117; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #9]118 119; truncating store volatile 32-bits to 16-bits120 %addr8_trunc32 = getelementptr i8, ptr %addr_8bit, i64 -256121 %val32 = load volatile i32, ptr @var_32bit122 %val16_trunc32 = trunc i32 %val32 to i16123 store volatile i16 %val16_trunc32, ptr %addr8_trunc32124; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-256]125 126; truncating store volatile 64-bits to 16-bits127 %addr8_trunc64 = getelementptr i8, ptr %addr_8bit, i64 -1128 %val64 = load volatile i64, ptr @var_64bit129 %val16_trunc64 = trunc i64 %val64 to i16130 store volatile i16 %val16_trunc64, ptr %addr8_trunc64131; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-1]132 133 ret void134}135 136define dso_local void @ldst_32bit() {137; CHECK-LABEL: ldst_32bit:138 139 %addr_8bit = load ptr, ptr @varptr140 141; Straight 32-bit load/store142 %addr32_8_noext = getelementptr i8, ptr %addr_8bit, i64 1143 %val32_noext = load volatile i32, ptr %addr32_8_noext144 store volatile i32 %val32_noext, ptr %addr32_8_noext145; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #1]146; CHECK: stur {{w[0-9]+}}, [{{x[0-9]+}}, #1]147 148; Zero-extension to 64-bits149 %addr32_8_zext = getelementptr i8, ptr %addr_8bit, i64 -256150 %val32_zext = load volatile i32, ptr %addr32_8_zext151 %val64_unsigned = zext i32 %val32_zext to i64152 store volatile i64 %val64_unsigned, ptr @var_64bit153; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #-256]154; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]155 156; Sign-extension to 64-bits157 %addr32_8_sext = getelementptr i8, ptr %addr_8bit, i64 -12158 %val32_sext = load volatile i32, ptr %addr32_8_sext159 %val64_signed = sext i32 %val32_sext to i64160 store volatile i64 %val64_signed, ptr @var_64bit161; CHECK: ldursw {{x[0-9]+}}, [{{x[0-9]+}}, #-12]162; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]163 164; Truncation from 64-bits165 %addr64_8_trunc = getelementptr i8, ptr %addr_8bit, i64 255166 %addr32_8_trunc = getelementptr i8, ptr %addr_8bit, i64 -20167 168 %val64_trunc = load volatile i64, ptr %addr64_8_trunc169 %val32_trunc = trunc i64 %val64_trunc to i32170 store volatile i32 %val32_trunc, ptr %addr32_8_trunc171; CHECK: ldur {{x[0-9]+}}, [{{x[0-9]+}}, #255]172; CHECK: stur {{w[0-9]+}}, [{{x[0-9]+}}, #-20]173 174 ret void175}176 177define dso_local void @ldst_float() {178; CHECK-LABEL: ldst_float:179 180 %addr_8bit = load ptr, ptr @varptr181 %addrfp_8 = getelementptr i8, ptr %addr_8bit, i64 -5182 183 %valfp = load volatile float, ptr %addrfp_8184; CHECK: ldur {{s[0-9]+}}, [{{x[0-9]+}}, #-5]185; CHECK-NOFP-NOT: ldur {{s[0-9]+}},186 187 store volatile float %valfp, ptr %addrfp_8188; CHECK: stur {{s[0-9]+}}, [{{x[0-9]+}}, #-5]189; CHECK-NOFP-NOT: stur {{s[0-9]+}},190 191 ret void192}193 194define dso_local void @ldst_double() {195; CHECK-LABEL: ldst_double:196 197 %addr_8bit = load ptr, ptr @varptr198 %addrfp_8 = getelementptr i8, ptr %addr_8bit, i64 4199 200 %valfp = load volatile double, ptr %addrfp_8201; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #4]202; CHECK-NOFP-NOT: ldur {{d[0-9]+}},203 204 store volatile double %valfp, ptr %addrfp_8205; CHECK: stur {{d[0-9]+}}, [{{x[0-9]+}}, #4]206; CHECK-NOFP-NOT: stur {{d[0-9]+}},207 208 ret void209}210