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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu | FileCheck --check-prefixes=CHECK,CHECK-FP %s3; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefixes=CHECK,CHECK-NOFP %s4 5@var_8bit = dso_local global i8 06@var_16bit = dso_local global i16 07@var_32bit = dso_local global i32 08@var_64bit = dso_local global i64 09 10@var_float = dso_local global float 0.011@var_double = dso_local global double 0.012 13define i32 @ld_s8_32() {14; CHECK-LABEL: ld_s8_32:15; CHECK: // %bb.0:16; CHECK-NEXT: adrp x8, var_8bit17; CHECK-NEXT: ldrsb w0, [x8, :lo12:var_8bit]18; CHECK-NEXT: ret19 %val8_sext32 = load i8, ptr @var_8bit20 %val32_signed = sext i8 %val8_sext32 to i3221 ret i32 %val32_signed22}23 24define i32 @ld_u8_32() {25; CHECK-LABEL: ld_u8_32:26; CHECK: // %bb.0:27; CHECK-NEXT: adrp x8, var_8bit28; CHECK-NEXT: ldrb w0, [x8, :lo12:var_8bit]29; CHECK-NEXT: ret30 %val8_zext32 = load i8, ptr @var_8bit31 %val32_unsigned = zext i8 %val8_zext32 to i3232 ret i32 %val32_unsigned33}34 35define i64 @ld_s8_64() {36; CHECK-LABEL: ld_s8_64:37; CHECK: // %bb.0:38; CHECK-NEXT: adrp x8, var_8bit39; CHECK-NEXT: ldrsb x0, [x8, :lo12:var_8bit]40; CHECK-NEXT: ret41 %val8_sext64 = load i8, ptr @var_8bit42 %val64_signed = sext i8 %val8_sext64 to i6443 ret i64 %val64_signed44}45 46define i64 @ld_u8_64() {47; CHECK-LABEL: ld_u8_64:48; CHECK: // %bb.0:49; CHECK-NEXT: adrp x8, var_8bit50; CHECK-NEXT: ldrb w0, [x8, :lo12:var_8bit]51; CHECK-NEXT: ret52 %val8_zext64 = load i8, ptr @var_8bit53 %val64_unsigned = zext i8 %val8_zext64 to i6454 ret i64 %val64_unsigned55}56 57define i8 @ld_a8_8() {58; CHECK-LABEL: ld_a8_8:59; CHECK: // %bb.0:60; CHECK-NEXT: adrp x8, var_8bit61; CHECK-NEXT: ldrb w8, [x8, :lo12:var_8bit]62; CHECK-NEXT: add w0, w8, #163; CHECK-NEXT: ret64 %val8_anyext = load i8, ptr @var_8bit65 %newval8 = add i8 %val8_anyext, 166 ret i8 %newval867}68 69define void @st_i32_8(i32 %val32) {70; CHECK-LABEL: st_i32_8:71; CHECK: // %bb.0:72; CHECK-NEXT: adrp x8, var_8bit73; CHECK-NEXT: strb w0, [x8, :lo12:var_8bit]74; CHECK-NEXT: ret75 %val8_trunc32 = trunc i32 %val32 to i876 store i8 %val8_trunc32, ptr @var_8bit77 ret void78}79 80define void @st_i64_8(i64 %val64) {81; CHECK-LABEL: st_i64_8:82; CHECK: // %bb.0:83; CHECK-NEXT: adrp x8, var_8bit84; CHECK-NEXT: strb w0, [x8, :lo12:var_8bit]85; CHECK-NEXT: ret86 %val8_trunc64 = trunc i64 %val64 to i887 store i8 %val8_trunc64, ptr @var_8bit88 ret void89}90 91 92define i32 @ld_s16_32() {93; CHECK-LABEL: ld_s16_32:94; CHECK: // %bb.0:95; CHECK-NEXT: adrp x8, var_16bit96; CHECK-NEXT: ldrsh w0, [x8, :lo12:var_16bit]97; CHECK-NEXT: ret98 %val16_sext32 = load i16, ptr @var_16bit99 %val32_signed = sext i16 %val16_sext32 to i32100 ret i32 %val32_signed101}102 103define i32 @ld_u16_32() {104; CHECK-LABEL: ld_u16_32:105; CHECK: // %bb.0:106; CHECK-NEXT: adrp x8, var_16bit107; CHECK-NEXT: ldrh w0, [x8, :lo12:var_16bit]108; CHECK-NEXT: ret109 %val16_zext32 = load i16, ptr @var_16bit110 %val32_unsigned = zext i16 %val16_zext32 to i32111 ret i32 %val32_unsigned112}113 114define i64 @ld_s16_64() {115; CHECK-LABEL: ld_s16_64:116; CHECK: // %bb.0:117; CHECK-NEXT: adrp x8, var_16bit118; CHECK-NEXT: ldrsh x0, [x8, :lo12:var_16bit]119; CHECK-NEXT: ret120 %val16_sext64 = load i16, ptr @var_16bit121 %val64_signed = sext i16 %val16_sext64 to i64122 ret i64 %val64_signed123}124 125define i64 @ld_u16_64() {126; CHECK-LABEL: ld_u16_64:127; CHECK: // %bb.0:128; CHECK-NEXT: adrp x8, var_16bit129; CHECK-NEXT: ldrh w0, [x8, :lo12:var_16bit]130; CHECK-NEXT: ret131 %val16_zext64 = load i16, ptr @var_16bit132 %val64_unsigned = zext i16 %val16_zext64 to i64133 ret i64 %val64_unsigned134}135 136define i16 @ld_a16_16() {137; CHECK-LABEL: ld_a16_16:138; CHECK: // %bb.0:139; CHECK-NEXT: adrp x8, var_16bit140; CHECK-NEXT: ldrh w8, [x8, :lo12:var_16bit]141; CHECK-NEXT: add w0, w8, #1142; CHECK-NEXT: ret143 %val16_anyext = load i16, ptr @var_16bit144 %newval16 = add i16 %val16_anyext, 1145 ret i16 %newval16146}147 148define void @st_i32_16(i32 %val32) {149; CHECK-LABEL: st_i32_16:150; CHECK: // %bb.0:151; CHECK-NEXT: adrp x8, var_16bit152; CHECK-NEXT: strh w0, [x8, :lo12:var_16bit]153; CHECK-NEXT: ret154 %val16_trunc32 = trunc i32 %val32 to i16155 store i16 %val16_trunc32, ptr @var_16bit156 ret void157}158 159define void @st_i64_16(i64 %val64) {160; CHECK-LABEL: st_i64_16:161; CHECK: // %bb.0:162; CHECK-NEXT: adrp x8, var_16bit163; CHECK-NEXT: strh w0, [x8, :lo12:var_16bit]164; CHECK-NEXT: ret165 %val16_trunc64 = trunc i64 %val64 to i16166 store i16 %val16_trunc64, ptr @var_16bit167 ret void168}169 170 171define i64 @ld_s32_64() {172; CHECK-LABEL: ld_s32_64:173; CHECK: // %bb.0:174; CHECK-NEXT: adrp x8, var_32bit175; CHECK-NEXT: ldrsw x0, [x8, :lo12:var_32bit]176; CHECK-NEXT: ret177 %val32_sext64 = load i32, ptr @var_32bit178 %val64_signed = sext i32 %val32_sext64 to i64179 ret i64 %val64_signed180}181 182define i64 @ld_u32_64() {183; CHECK-LABEL: ld_u32_64:184; CHECK: // %bb.0:185; CHECK-NEXT: adrp x8, var_32bit186; CHECK-NEXT: ldr w0, [x8, :lo12:var_32bit]187; CHECK-NEXT: ret188 %val32_zext64 = load i32, ptr @var_32bit189 %val64_unsigned = zext i32 %val32_zext64 to i64190 ret i64 %val64_unsigned191}192 193define i32 @ld_a32_32() {194; CHECK-LABEL: ld_a32_32:195; CHECK: // %bb.0:196; CHECK-NEXT: adrp x8, var_32bit197; CHECK-NEXT: ldr w8, [x8, :lo12:var_32bit]198; CHECK-NEXT: add w0, w8, #1199; CHECK-NEXT: ret200 %val32_anyext = load i32, ptr @var_32bit201 %newval32 = add i32 %val32_anyext, 1202 ret i32 %newval32203}204 205define void @st_i64_32(i64 %val64) {206; CHECK-LABEL: st_i64_32:207; CHECK: // %bb.0:208; CHECK-NEXT: adrp x8, var_32bit209; CHECK-NEXT: str w0, [x8, :lo12:var_32bit]210; CHECK-NEXT: ret211 %val32_trunc64 = trunc i64 %val64 to i32212 store i32 %val32_trunc64, ptr @var_32bit213 ret void214}215 216 217@arr8 = dso_local global ptr null218@arr16 = dso_local global ptr null219@arr32 = dso_local global ptr null220@arr64 = dso_local global ptr null221 222; Now check that our selection copes with accesses more complex than a223; single symbol. Permitted offsets should be folded into the loads and224; stores. Since all forms use the same Operand it's only necessary to225; check the various access-sizes involved.226 227define i8 @ld_i8_1(ptr %arr8_addr) {228; CHECK-LABEL: ld_i8_1:229; CHECK: // %bb.0:230; CHECK-NEXT: ldrb w0, [x0, #1]231; CHECK-NEXT: ret232 %arr8_sub1_addr = getelementptr i8, ptr %arr8_addr, i64 1233 %arr8_sub1 = load volatile i8, ptr %arr8_sub1_addr234 ret i8 %arr8_sub1235}236 237define i8 @ld_i8_4095(ptr %arr8_addr) {238; CHECK-LABEL: ld_i8_4095:239; CHECK: // %bb.0:240; CHECK-NEXT: ldrb w0, [x0, #4095]241; CHECK-NEXT: ret242 %arr8_sub4095_addr = getelementptr i8, ptr %arr8_addr, i64 4095243 %arr8_sub4095 = load volatile i8, ptr %arr8_sub4095_addr244 ret i8 %arr8_sub4095245}246 247define i16 @ld_i16_1(ptr %arr16_addr) {248; CHECK-LABEL: ld_i16_1:249; CHECK: // %bb.0:250; CHECK-NEXT: ldrh w0, [x0, #2]251; CHECK-NEXT: ret252 %arr16_sub1_addr = getelementptr i16, ptr %arr16_addr, i64 1253 %arr16_sub1 = load volatile i16, ptr %arr16_sub1_addr254 ret i16 %arr16_sub1255}256 257define i16 @ld_i16_4095(ptr %arr16_addr) {258; CHECK-LABEL: ld_i16_4095:259; CHECK: // %bb.0:260; CHECK-NEXT: ldrh w0, [x0, #8190]261; CHECK-NEXT: ret262 %arr16_sub4095_addr = getelementptr i16, ptr %arr16_addr, i64 4095263 %arr16_sub4095 = load volatile i16, ptr %arr16_sub4095_addr264 ret i16 %arr16_sub4095265}266 267define i32 @ld_i32_1(ptr %arr32_addr) {268; CHECK-LABEL: ld_i32_1:269; CHECK: // %bb.0:270; CHECK-NEXT: ldr w0, [x0, #4]271; CHECK-NEXT: ret272 %arr32_sub1_addr = getelementptr i32, ptr %arr32_addr, i64 1273 %arr32_sub1 = load volatile i32, ptr %arr32_sub1_addr274 ret i32 %arr32_sub1275}276 277define i32 @ld_i32_4095(ptr %arr32_addr) {278; CHECK-LABEL: ld_i32_4095:279; CHECK: // %bb.0:280; CHECK-NEXT: ldr w0, [x0, #16380]281; CHECK-NEXT: ret282 %arr32_sub4095_addr = getelementptr i32, ptr %arr32_addr, i64 4095283 %arr32_sub4095 = load volatile i32, ptr %arr32_sub4095_addr284 ret i32 %arr32_sub4095285}286 287define i64 @ld_i64_1(ptr %arr64_addr) {288; CHECK-LABEL: ld_i64_1:289; CHECK: // %bb.0:290; CHECK-NEXT: ldr x0, [x0, #8]291; CHECK-NEXT: ret292 %arr64_sub1_addr = getelementptr i64, ptr %arr64_addr, i64 1293 %arr64_sub1 = load volatile i64, ptr %arr64_sub1_addr294 ret i64 %arr64_sub1295}296 297define i64 @ld_i64_4095(ptr %arr64_addr) {298; CHECK-LABEL: ld_i64_4095:299; CHECK: // %bb.0:300; CHECK-NEXT: ldr x0, [x0, #32760]301; CHECK-NEXT: ret302 %arr64_sub4095_addr = getelementptr i64, ptr %arr64_addr, i64 4095303 %arr64_sub4095 = load volatile i64, ptr %arr64_sub4095_addr304 ret i64 %arr64_sub4095305}306 307define dso_local void @ldst_float() {308; CHECK-FP-LABEL: ldst_float:309; CHECK-FP: // %bb.0:310; CHECK-FP-NEXT: adrp x8, var_float311; CHECK-FP-NEXT: ldr s0, [x8, :lo12:var_float]312; CHECK-FP-NEXT: str s0, [x8, :lo12:var_float]313; CHECK-FP-NEXT: ret314;315; CHECK-NOFP-LABEL: ldst_float:316; CHECK-NOFP: // %bb.0:317; CHECK-NOFP-NEXT: adrp x8, var_float318; CHECK-NOFP-NEXT: ldr w9, [x8, :lo12:var_float]319; CHECK-NOFP-NEXT: str w9, [x8, :lo12:var_float]320; CHECK-NOFP-NEXT: ret321 %valfp = load volatile float, ptr @var_float322 store volatile float %valfp, ptr @var_float323 ret void324}325 326define dso_local void @ldst_double() {327; CHECK-FP-LABEL: ldst_double:328; CHECK-FP: // %bb.0:329; CHECK-FP-NEXT: adrp x8, var_double330; CHECK-FP-NEXT: ldr d0, [x8, :lo12:var_double]331; CHECK-FP-NEXT: str d0, [x8, :lo12:var_double]332; CHECK-FP-NEXT: ret333;334; CHECK-NOFP-LABEL: ldst_double:335; CHECK-NOFP: // %bb.0:336; CHECK-NOFP-NEXT: adrp x8, var_double337; CHECK-NOFP-NEXT: ldr x9, [x8, :lo12:var_double]338; CHECK-NOFP-NEXT: str x9, [x8, :lo12:var_double]339; CHECK-NOFP-NEXT: ret340 %valfp = load volatile double, ptr @var_double341 store volatile double %valfp, ptr @var_double342 ret void343}344