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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK-NOFP163; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-FP164; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK-NOFP165; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK-FP166 7define i16 @testmhhs(half %x) {8; CHECK-NOFP16-LABEL: testmhhs:9; CHECK-NOFP16: // %bb.0: // %entry10; CHECK-NOFP16-NEXT: fcvt s0, h011; CHECK-NOFP16-NEXT: frintx s0, s012; CHECK-NOFP16-NEXT: fcvtzs x0, s013; CHECK-NOFP16-NEXT: // kill: def $w0 killed $w0 killed $x014; CHECK-NOFP16-NEXT: ret15;16; CHECK-FP16-LABEL: testmhhs:17; CHECK-FP16: // %bb.0: // %entry18; CHECK-FP16-NEXT: frintx h0, h019; CHECK-FP16-NEXT: fcvtzs x0, h020; CHECK-FP16-NEXT: // kill: def $w0 killed $w0 killed $x021; CHECK-FP16-NEXT: ret22entry:23 %0 = tail call i64 @llvm.llrint.i64.f16(half %x)24 %conv = trunc i64 %0 to i1625 ret i16 %conv26}27 28define i32 @testmhws(half %x) {29; CHECK-NOFP16-LABEL: testmhws:30; CHECK-NOFP16: // %bb.0: // %entry31; CHECK-NOFP16-NEXT: fcvt s0, h032; CHECK-NOFP16-NEXT: frintx s0, s033; CHECK-NOFP16-NEXT: fcvtzs x0, s034; CHECK-NOFP16-NEXT: // kill: def $w0 killed $w0 killed $x035; CHECK-NOFP16-NEXT: ret36;37; CHECK-FP16-LABEL: testmhws:38; CHECK-FP16: // %bb.0: // %entry39; CHECK-FP16-NEXT: frintx h0, h040; CHECK-FP16-NEXT: fcvtzs x0, h041; CHECK-FP16-NEXT: // kill: def $w0 killed $w0 killed $x042; CHECK-FP16-NEXT: ret43entry:44 %0 = tail call i64 @llvm.llrint.i64.f16(half %x)45 %conv = trunc i64 %0 to i3246 ret i32 %conv47}48 49define i64 @testmhxs(half %x) {50; CHECK-NOFP16-LABEL: testmhxs:51; CHECK-NOFP16: // %bb.0: // %entry52; CHECK-NOFP16-NEXT: fcvt s0, h053; CHECK-NOFP16-NEXT: frintx s0, s054; CHECK-NOFP16-NEXT: fcvtzs x0, s055; CHECK-NOFP16-NEXT: ret56;57; CHECK-FP16-LABEL: testmhxs:58; CHECK-FP16: // %bb.0: // %entry59; CHECK-FP16-NEXT: frintx h0, h060; CHECK-FP16-NEXT: fcvtzs x0, h061; CHECK-FP16-NEXT: ret62entry:63 %0 = tail call i64 @llvm.llrint.i64.f16(half %x)64 ret i64 %065}66 67declare i64 @llvm.llrint.i64.f16(half) nounwind readnone68