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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s3 4;5; SDIV6;7 8define <vscale x 16 x i8> @sdiv_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {9; CHECK-LABEL: sdiv_i8:10; CHECK: // %bb.0:11; CHECK-NEXT: sunpkhi z2.h, z1.b12; CHECK-NEXT: sunpkhi z3.h, z0.b13; CHECK-NEXT: sunpklo z1.h, z1.b14; CHECK-NEXT: sunpklo z0.h, z0.b15; CHECK-NEXT: ptrue p0.s16; CHECK-NEXT: sunpkhi z4.s, z2.h17; CHECK-NEXT: sunpkhi z5.s, z3.h18; CHECK-NEXT: sunpklo z2.s, z2.h19; CHECK-NEXT: sunpklo z3.s, z3.h20; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s21; CHECK-NEXT: sunpkhi z5.s, z0.h22; CHECK-NEXT: sunpklo z0.s, z0.h23; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s24; CHECK-NEXT: sunpkhi z3.s, z1.h25; CHECK-NEXT: sunpklo z1.s, z1.h26; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z5.s27; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s28; CHECK-NEXT: uzp1 z1.h, z2.h, z4.h29; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h30; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b31; CHECK-NEXT: ret32 %div = sdiv <vscale x 16 x i8> %a, %b33 ret <vscale x 16 x i8> %div34}35 36define <vscale x 8 x i16> @sdiv_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {37; CHECK-LABEL: sdiv_i16:38; CHECK: // %bb.0:39; CHECK-NEXT: sunpkhi z2.s, z1.h40; CHECK-NEXT: sunpkhi z3.s, z0.h41; CHECK-NEXT: sunpklo z1.s, z1.h42; CHECK-NEXT: sunpklo z0.s, z0.h43; CHECK-NEXT: ptrue p0.s44; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s45; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s46; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h47; CHECK-NEXT: ret48 %div = sdiv <vscale x 8 x i16> %a, %b49 ret <vscale x 8 x i16> %div50}51 52define <vscale x 4 x i32> @sdiv_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {53; CHECK-LABEL: sdiv_i32:54; CHECK: // %bb.0:55; CHECK-NEXT: ptrue p0.s56; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s57; CHECK-NEXT: ret58 %div = sdiv <vscale x 4 x i32> %a, %b59 ret <vscale x 4 x i32> %div60}61 62define <vscale x 2 x i64> @sdiv_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {63; CHECK-LABEL: sdiv_i64:64; CHECK: // %bb.0:65; CHECK-NEXT: ptrue p0.d66; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d67; CHECK-NEXT: ret68 %div = sdiv <vscale x 2 x i64> %a, %b69 ret <vscale x 2 x i64> %div70}71 72define <vscale x 8 x i32> @sdiv_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {73; CHECK-LABEL: sdiv_split_i32:74; CHECK: // %bb.0:75; CHECK-NEXT: ptrue p0.s76; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z2.s77; CHECK-NEXT: sdiv z1.s, p0/m, z1.s, z3.s78; CHECK-NEXT: ret79 %div = sdiv <vscale x 8 x i32> %a, %b80 ret <vscale x 8 x i32> %div81}82 83define <vscale x 2 x i32> @sdiv_widen_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {84; CHECK-LABEL: sdiv_widen_i32:85; CHECK: // %bb.0:86; CHECK-NEXT: ptrue p0.d87; CHECK-NEXT: sxtw z1.d, p0/m, z1.d88; CHECK-NEXT: sxtw z0.d, p0/m, z0.d89; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d90; CHECK-NEXT: ret91 %div = sdiv <vscale x 2 x i32> %a, %b92 ret <vscale x 2 x i32> %div93}94 95define <vscale x 4 x i64> @sdiv_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {96; CHECK-LABEL: sdiv_split_i64:97; CHECK: // %bb.0:98; CHECK-NEXT: ptrue p0.d99; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z2.d100; CHECK-NEXT: sdiv z1.d, p0/m, z1.d, z3.d101; CHECK-NEXT: ret102 %div = sdiv <vscale x 4 x i64> %a, %b103 ret <vscale x 4 x i64> %div104}105 106;107; SREM108;109 110define <vscale x 16 x i8> @srem_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {111; CHECK-LABEL: srem_i8:112; CHECK: // %bb.0:113; CHECK-NEXT: sunpkhi z2.h, z1.b114; CHECK-NEXT: sunpkhi z3.h, z0.b115; CHECK-NEXT: ptrue p0.s116; CHECK-NEXT: sunpkhi z4.s, z2.h117; CHECK-NEXT: sunpkhi z5.s, z3.h118; CHECK-NEXT: sunpklo z2.s, z2.h119; CHECK-NEXT: sunpklo z3.s, z3.h120; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s121; CHECK-NEXT: sunpklo z5.h, z0.b122; CHECK-NEXT: sunpkhi z7.s, z5.h123; CHECK-NEXT: sunpklo z5.s, z5.h124; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s125; CHECK-NEXT: sunpklo z3.h, z1.b126; CHECK-NEXT: sunpkhi z6.s, z3.h127; CHECK-NEXT: sunpklo z3.s, z3.h128; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z7.s129; CHECK-NEXT: uzp1 z2.h, z2.h, z4.h130; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z5.s131; CHECK-NEXT: ptrue p0.b132; CHECK-NEXT: uzp1 z3.h, z3.h, z6.h133; CHECK-NEXT: uzp1 z2.b, z3.b, z2.b134; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b135; CHECK-NEXT: ret136 %div = srem <vscale x 16 x i8> %a, %b137 ret <vscale x 16 x i8> %div138}139 140define <vscale x 8 x i16> @srem_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {141; CHECK-LABEL: srem_i16:142; CHECK: // %bb.0:143; CHECK-NEXT: sunpkhi z2.s, z1.h144; CHECK-NEXT: sunpkhi z3.s, z0.h145; CHECK-NEXT: ptrue p0.s146; CHECK-NEXT: sunpklo z4.s, z0.h147; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s148; CHECK-NEXT: sunpklo z3.s, z1.h149; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s150; CHECK-NEXT: ptrue p0.h151; CHECK-NEXT: uzp1 z2.h, z3.h, z2.h152; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h153; CHECK-NEXT: ret154 %div = srem <vscale x 8 x i16> %a, %b155 ret <vscale x 8 x i16> %div156}157 158define <vscale x 4 x i32> @srem_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {159; CHECK-LABEL: srem_i32:160; CHECK: // %bb.0:161; CHECK-NEXT: ptrue p0.s162; CHECK-NEXT: movprfx z2, z0163; CHECK-NEXT: sdiv z2.s, p0/m, z2.s, z1.s164; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s165; CHECK-NEXT: ret166 %div = srem <vscale x 4 x i32> %a, %b167 ret <vscale x 4 x i32> %div168}169 170define <vscale x 2 x i64> @srem_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {171; CHECK-LABEL: srem_i64:172; CHECK: // %bb.0:173; CHECK-NEXT: ptrue p0.d174; CHECK-NEXT: movprfx z2, z0175; CHECK-NEXT: sdiv z2.d, p0/m, z2.d, z1.d176; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d177; CHECK-NEXT: ret178 %div = srem <vscale x 2 x i64> %a, %b179 ret <vscale x 2 x i64> %div180}181 182;183; UDIV184;185 186define <vscale x 16 x i8> @udiv_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {187; CHECK-LABEL: udiv_i8:188; CHECK: // %bb.0:189; CHECK-NEXT: uunpkhi z2.h, z1.b190; CHECK-NEXT: uunpkhi z3.h, z0.b191; CHECK-NEXT: uunpklo z1.h, z1.b192; CHECK-NEXT: uunpklo z0.h, z0.b193; CHECK-NEXT: ptrue p0.s194; CHECK-NEXT: uunpkhi z4.s, z2.h195; CHECK-NEXT: uunpkhi z5.s, z3.h196; CHECK-NEXT: uunpklo z2.s, z2.h197; CHECK-NEXT: uunpklo z3.s, z3.h198; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s199; CHECK-NEXT: uunpkhi z5.s, z0.h200; CHECK-NEXT: uunpklo z0.s, z0.h201; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s202; CHECK-NEXT: uunpkhi z3.s, z1.h203; CHECK-NEXT: uunpklo z1.s, z1.h204; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z5.s205; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s206; CHECK-NEXT: uzp1 z1.h, z2.h, z4.h207; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h208; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b209; CHECK-NEXT: ret210 %div = udiv <vscale x 16 x i8> %a, %b211 ret <vscale x 16 x i8> %div212}213 214define <vscale x 8 x i16> @udiv_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {215; CHECK-LABEL: udiv_i16:216; CHECK: // %bb.0:217; CHECK-NEXT: uunpkhi z2.s, z1.h218; CHECK-NEXT: uunpkhi z3.s, z0.h219; CHECK-NEXT: uunpklo z1.s, z1.h220; CHECK-NEXT: uunpklo z0.s, z0.h221; CHECK-NEXT: ptrue p0.s222; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s223; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s224; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h225; CHECK-NEXT: ret226 %div = udiv <vscale x 8 x i16> %a, %b227 ret <vscale x 8 x i16> %div228}229 230define <vscale x 4 x i32> @udiv_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {231; CHECK-LABEL: udiv_i32:232; CHECK: // %bb.0:233; CHECK-NEXT: ptrue p0.s234; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s235; CHECK-NEXT: ret236 %div = udiv <vscale x 4 x i32> %a, %b237 ret <vscale x 4 x i32> %div238}239 240define <vscale x 2 x i64> @udiv_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {241; CHECK-LABEL: udiv_i64:242; CHECK: // %bb.0:243; CHECK-NEXT: ptrue p0.d244; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d245; CHECK-NEXT: ret246 %div = udiv <vscale x 2 x i64> %a, %b247 ret <vscale x 2 x i64> %div248}249 250define <vscale x 8 x i32> @udiv_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {251; CHECK-LABEL: udiv_split_i32:252; CHECK: // %bb.0:253; CHECK-NEXT: ptrue p0.s254; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z2.s255; CHECK-NEXT: udiv z1.s, p0/m, z1.s, z3.s256; CHECK-NEXT: ret257 %div = udiv <vscale x 8 x i32> %a, %b258 ret <vscale x 8 x i32> %div259}260 261define <vscale x 2 x i32> @udiv_widen_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {262; CHECK-LABEL: udiv_widen_i32:263; CHECK: // %bb.0:264; CHECK-NEXT: and z1.d, z1.d, #0xffffffff265; CHECK-NEXT: and z0.d, z0.d, #0xffffffff266; CHECK-NEXT: ptrue p0.d267; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d268; CHECK-NEXT: ret269 %div = udiv <vscale x 2 x i32> %a, %b270 ret <vscale x 2 x i32> %div271}272 273define <vscale x 4 x i64> @udiv_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {274; CHECK-LABEL: udiv_split_i64:275; CHECK: // %bb.0:276; CHECK-NEXT: ptrue p0.d277; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z2.d278; CHECK-NEXT: udiv z1.d, p0/m, z1.d, z3.d279; CHECK-NEXT: ret280 %div = udiv <vscale x 4 x i64> %a, %b281 ret <vscale x 4 x i64> %div282}283 284 285;286; UREM287;288 289define <vscale x 16 x i8> @urem_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {290; CHECK-LABEL: urem_i8:291; CHECK: // %bb.0:292; CHECK-NEXT: uunpkhi z2.h, z1.b293; CHECK-NEXT: uunpkhi z3.h, z0.b294; CHECK-NEXT: ptrue p0.s295; CHECK-NEXT: uunpkhi z4.s, z2.h296; CHECK-NEXT: uunpkhi z5.s, z3.h297; CHECK-NEXT: uunpklo z2.s, z2.h298; CHECK-NEXT: uunpklo z3.s, z3.h299; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s300; CHECK-NEXT: uunpklo z5.h, z0.b301; CHECK-NEXT: uunpkhi z7.s, z5.h302; CHECK-NEXT: uunpklo z5.s, z5.h303; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s304; CHECK-NEXT: uunpklo z3.h, z1.b305; CHECK-NEXT: uunpkhi z6.s, z3.h306; CHECK-NEXT: uunpklo z3.s, z3.h307; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z7.s308; CHECK-NEXT: uzp1 z2.h, z2.h, z4.h309; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z5.s310; CHECK-NEXT: ptrue p0.b311; CHECK-NEXT: uzp1 z3.h, z3.h, z6.h312; CHECK-NEXT: uzp1 z2.b, z3.b, z2.b313; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b314; CHECK-NEXT: ret315 %div = urem <vscale x 16 x i8> %a, %b316 ret <vscale x 16 x i8> %div317}318 319define <vscale x 8 x i16> @urem_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {320; CHECK-LABEL: urem_i16:321; CHECK: // %bb.0:322; CHECK-NEXT: uunpkhi z2.s, z1.h323; CHECK-NEXT: uunpkhi z3.s, z0.h324; CHECK-NEXT: ptrue p0.s325; CHECK-NEXT: uunpklo z4.s, z0.h326; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s327; CHECK-NEXT: uunpklo z3.s, z1.h328; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s329; CHECK-NEXT: ptrue p0.h330; CHECK-NEXT: uzp1 z2.h, z3.h, z2.h331; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h332; CHECK-NEXT: ret333 %div = urem <vscale x 8 x i16> %a, %b334 ret <vscale x 8 x i16> %div335}336 337define <vscale x 4 x i32> @urem_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {338; CHECK-LABEL: urem_i32:339; CHECK: // %bb.0:340; CHECK-NEXT: ptrue p0.s341; CHECK-NEXT: movprfx z2, z0342; CHECK-NEXT: udiv z2.s, p0/m, z2.s, z1.s343; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s344; CHECK-NEXT: ret345 %div = urem <vscale x 4 x i32> %a, %b346 ret <vscale x 4 x i32> %div347}348 349define <vscale x 2 x i64> @urem_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {350; CHECK-LABEL: urem_i64:351; CHECK: // %bb.0:352; CHECK-NEXT: ptrue p0.d353; CHECK-NEXT: movprfx z2, z0354; CHECK-NEXT: udiv z2.d, p0/m, z2.d, z1.d355; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d356; CHECK-NEXT: ret357 %div = urem <vscale x 2 x i64> %a, %b358 ret <vscale x 2 x i64> %div359}360 361;362; SMIN363;364 365define <vscale x 16 x i8> @smin_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {366; CHECK-LABEL: smin_i8:367; CHECK: // %bb.0:368; CHECK-NEXT: ptrue p0.b369; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b370; CHECK-NEXT: ret371 %cmp = icmp slt <vscale x 16 x i8> %a, %b372 %min = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b373 ret <vscale x 16 x i8> %min374}375 376define <vscale x 8 x i16> @smin_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {377; CHECK-LABEL: smin_i16:378; CHECK: // %bb.0:379; CHECK-NEXT: ptrue p0.h380; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h381; CHECK-NEXT: ret382 %cmp = icmp slt <vscale x 8 x i16> %a, %b383 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b384 ret <vscale x 8 x i16> %min385}386 387define <vscale x 4 x i32> @smin_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {388; CHECK-LABEL: smin_i32:389; CHECK: // %bb.0:390; CHECK-NEXT: ptrue p0.s391; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s392; CHECK-NEXT: ret393 %cmp = icmp slt <vscale x 4 x i32> %a, %b394 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b395 ret <vscale x 4 x i32> %min396}397 398define <vscale x 2 x i64> @smin_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {399; CHECK-LABEL: smin_i64:400; CHECK: // %bb.0:401; CHECK-NEXT: ptrue p0.d402; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d403; CHECK-NEXT: ret404 %cmp = icmp slt <vscale x 2 x i64> %a, %b405 %min = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b406 ret <vscale x 2 x i64> %min407}408 409define <vscale x 32 x i8> @smin_split_i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) {410; CHECK-LABEL: smin_split_i8:411; CHECK: // %bb.0:412; CHECK-NEXT: ptrue p0.b413; CHECK-NEXT: smin z0.b, p0/m, z0.b, z2.b414; CHECK-NEXT: smin z1.b, p0/m, z1.b, z3.b415; CHECK-NEXT: ret416 %cmp = icmp slt <vscale x 32 x i8> %a, %b417 %min = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b418 ret <vscale x 32 x i8> %min419}420 421define <vscale x 32 x i16> @smin_split_i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) {422; CHECK-LABEL: smin_split_i16:423; CHECK: // %bb.0:424; CHECK-NEXT: ptrue p0.h425; CHECK-NEXT: smin z0.h, p0/m, z0.h, z4.h426; CHECK-NEXT: smin z1.h, p0/m, z1.h, z5.h427; CHECK-NEXT: smin z2.h, p0/m, z2.h, z6.h428; CHECK-NEXT: smin z3.h, p0/m, z3.h, z7.h429; CHECK-NEXT: ret430 %cmp = icmp slt <vscale x 32 x i16> %a, %b431 %min = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b432 ret <vscale x 32 x i16> %min433}434 435define <vscale x 8 x i32> @smin_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {436; CHECK-LABEL: smin_split_i32:437; CHECK: // %bb.0:438; CHECK-NEXT: ptrue p0.s439; CHECK-NEXT: smin z0.s, p0/m, z0.s, z2.s440; CHECK-NEXT: smin z1.s, p0/m, z1.s, z3.s441; CHECK-NEXT: ret442 %cmp = icmp slt <vscale x 8 x i32> %a, %b443 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b444 ret <vscale x 8 x i32> %min445}446 447define <vscale x 4 x i64> @smin_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {448; CHECK-LABEL: smin_split_i64:449; CHECK: // %bb.0:450; CHECK-NEXT: ptrue p0.d451; CHECK-NEXT: smin z0.d, p0/m, z0.d, z2.d452; CHECK-NEXT: smin z1.d, p0/m, z1.d, z3.d453; CHECK-NEXT: ret454 %cmp = icmp slt <vscale x 4 x i64> %a, %b455 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b456 ret <vscale x 4 x i64> %min457}458 459define <vscale x 8 x i8> @smin_promote_i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {460; CHECK-LABEL: smin_promote_i8:461; CHECK: // %bb.0:462; CHECK-NEXT: ptrue p0.h463; CHECK-NEXT: sxtb z1.h, p0/m, z1.h464; CHECK-NEXT: sxtb z0.h, p0/m, z0.h465; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h466; CHECK-NEXT: ret467 %cmp = icmp slt <vscale x 8 x i8> %a, %b468 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b469 ret <vscale x 8 x i8> %min470}471 472define <vscale x 4 x i16> @smin_promote_i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {473; CHECK-LABEL: smin_promote_i16:474; CHECK: // %bb.0:475; CHECK-NEXT: ptrue p0.s476; CHECK-NEXT: sxth z1.s, p0/m, z1.s477; CHECK-NEXT: sxth z0.s, p0/m, z0.s478; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s479; CHECK-NEXT: ret480 %cmp = icmp slt <vscale x 4 x i16> %a, %b481 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b482 ret <vscale x 4 x i16> %min483}484 485define <vscale x 2 x i32> @smin_promote_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {486; CHECK-LABEL: smin_promote_i32:487; CHECK: // %bb.0:488; CHECK-NEXT: ptrue p0.d489; CHECK-NEXT: sxtw z1.d, p0/m, z1.d490; CHECK-NEXT: sxtw z0.d, p0/m, z0.d491; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d492; CHECK-NEXT: ret493 %cmp = icmp slt <vscale x 2 x i32> %a, %b494 %min = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b495 ret <vscale x 2 x i32> %min496}497 498;499; UMIN500;501 502define <vscale x 16 x i8> @umin_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {503; CHECK-LABEL: umin_i8:504; CHECK: // %bb.0:505; CHECK-NEXT: ptrue p0.b506; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b507; CHECK-NEXT: ret508 %cmp = icmp ult <vscale x 16 x i8> %a, %b509 %min = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b510 ret <vscale x 16 x i8> %min511}512 513define <vscale x 8 x i16> @umin_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {514; CHECK-LABEL: umin_i16:515; CHECK: // %bb.0:516; CHECK-NEXT: ptrue p0.h517; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h518; CHECK-NEXT: ret519 %cmp = icmp ult <vscale x 8 x i16> %a, %b520 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b521 ret <vscale x 8 x i16> %min522}523 524define <vscale x 4 x i32> @umin_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {525; CHECK-LABEL: umin_i32:526; CHECK: // %bb.0:527; CHECK-NEXT: ptrue p0.s528; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s529; CHECK-NEXT: ret530 %cmp = icmp ult <vscale x 4 x i32> %a, %b531 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b532 ret <vscale x 4 x i32> %min533}534 535define <vscale x 2 x i64> @umin_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {536; CHECK-LABEL: umin_i64:537; CHECK: // %bb.0:538; CHECK-NEXT: ptrue p0.d539; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d540; CHECK-NEXT: ret541 %cmp = icmp ult <vscale x 2 x i64> %a, %b542 %min = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b543 ret <vscale x 2 x i64> %min544}545 546define <vscale x 4 x i64> @umin_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {547; CHECK-LABEL: umin_split_i64:548; CHECK: // %bb.0:549; CHECK-NEXT: ptrue p0.d550; CHECK-NEXT: umin z0.d, p0/m, z0.d, z2.d551; CHECK-NEXT: umin z1.d, p0/m, z1.d, z3.d552; CHECK-NEXT: ret553 %cmp = icmp ult <vscale x 4 x i64> %a, %b554 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b555 ret <vscale x 4 x i64> %min556}557 558define <vscale x 8 x i8> @umin_promote_i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {559; CHECK-LABEL: umin_promote_i8:560; CHECK: // %bb.0:561; CHECK-NEXT: and z1.h, z1.h, #0xff562; CHECK-NEXT: and z0.h, z0.h, #0xff563; CHECK-NEXT: ptrue p0.h564; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h565; CHECK-NEXT: ret566 %cmp = icmp ult <vscale x 8 x i8> %a, %b567 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b568 ret <vscale x 8 x i8> %min569}570 571;572; SMAX573;574 575define <vscale x 16 x i8> @smax_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {576; CHECK-LABEL: smax_i8:577; CHECK: // %bb.0:578; CHECK-NEXT: ptrue p0.b579; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b580; CHECK-NEXT: ret581 %cmp = icmp sgt <vscale x 16 x i8> %a, %b582 %max = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b583 ret <vscale x 16 x i8> %max584}585 586define <vscale x 8 x i16> @smax_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {587; CHECK-LABEL: smax_i16:588; CHECK: // %bb.0:589; CHECK-NEXT: ptrue p0.h590; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h591; CHECK-NEXT: ret592 %cmp = icmp sgt <vscale x 8 x i16> %a, %b593 %max = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b594 ret <vscale x 8 x i16> %max595}596 597define <vscale x 4 x i32> @smax_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {598; CHECK-LABEL: smax_i32:599; CHECK: // %bb.0:600; CHECK-NEXT: ptrue p0.s601; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s602; CHECK-NEXT: ret603 %cmp = icmp sgt <vscale x 4 x i32> %a, %b604 %max = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b605 ret <vscale x 4 x i32> %max606}607 608define <vscale x 2 x i64> @smax_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {609; CHECK-LABEL: smax_i64:610; CHECK: // %bb.0:611; CHECK-NEXT: ptrue p0.d612; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d613; CHECK-NEXT: ret614 %cmp = icmp sgt <vscale x 2 x i64> %a, %b615 %max = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b616 ret <vscale x 2 x i64> %max617}618 619define <vscale x 8 x i32> @smax_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {620; CHECK-LABEL: smax_split_i32:621; CHECK: // %bb.0:622; CHECK-NEXT: ptrue p0.s623; CHECK-NEXT: smax z0.s, p0/m, z0.s, z2.s624; CHECK-NEXT: smax z1.s, p0/m, z1.s, z3.s625; CHECK-NEXT: ret626 %cmp = icmp sgt <vscale x 8 x i32> %a, %b627 %max = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b628 ret <vscale x 8 x i32> %max629}630 631define <vscale x 4 x i16> @smax_promote_i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {632; CHECK-LABEL: smax_promote_i16:633; CHECK: // %bb.0:634; CHECK-NEXT: ptrue p0.s635; CHECK-NEXT: sxth z1.s, p0/m, z1.s636; CHECK-NEXT: sxth z0.s, p0/m, z0.s637; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s638; CHECK-NEXT: ret639 %cmp = icmp sgt <vscale x 4 x i16> %a, %b640 %max = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b641 ret <vscale x 4 x i16> %max642}643 644;645; UMAX646;647 648define <vscale x 16 x i8> @umax_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {649; CHECK-LABEL: umax_i8:650; CHECK: // %bb.0:651; CHECK-NEXT: ptrue p0.b652; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b653; CHECK-NEXT: ret654 %cmp = icmp ugt <vscale x 16 x i8> %a, %b655 %max = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b656 ret <vscale x 16 x i8> %max657}658 659define <vscale x 8 x i16> @umax_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {660; CHECK-LABEL: umax_i16:661; CHECK: // %bb.0:662; CHECK-NEXT: ptrue p0.h663; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h664; CHECK-NEXT: ret665 %cmp = icmp ugt <vscale x 8 x i16> %a, %b666 %max = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b667 ret <vscale x 8 x i16> %max668}669 670define <vscale x 4 x i32> @umax_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {671; CHECK-LABEL: umax_i32:672; CHECK: // %bb.0:673; CHECK-NEXT: ptrue p0.s674; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s675; CHECK-NEXT: ret676 %cmp = icmp ugt <vscale x 4 x i32> %a, %b677 %max = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b678 ret <vscale x 4 x i32> %max679}680 681define <vscale x 2 x i64> @umax_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {682; CHECK-LABEL: umax_i64:683; CHECK: // %bb.0:684; CHECK-NEXT: ptrue p0.d685; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d686; CHECK-NEXT: ret687 %cmp = icmp ugt <vscale x 2 x i64> %a, %b688 %max = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b689 ret <vscale x 2 x i64> %max690}691 692define <vscale x 16 x i16> @umax_split_i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {693; CHECK-LABEL: umax_split_i16:694; CHECK: // %bb.0:695; CHECK-NEXT: ptrue p0.h696; CHECK-NEXT: umax z0.h, p0/m, z0.h, z2.h697; CHECK-NEXT: umax z1.h, p0/m, z1.h, z3.h698; CHECK-NEXT: ret699 %cmp = icmp ugt <vscale x 16 x i16> %a, %b700 %max = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b701 ret <vscale x 16 x i16> %max702}703 704define <vscale x 2 x i32> @umax_promote_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {705; CHECK-LABEL: umax_promote_i32:706; CHECK: // %bb.0:707; CHECK-NEXT: and z1.d, z1.d, #0xffffffff708; CHECK-NEXT: and z0.d, z0.d, #0xffffffff709; CHECK-NEXT: ptrue p0.d710; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d711; CHECK-NEXT: ret712 %cmp = icmp ugt <vscale x 2 x i32> %a, %b713 %max = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b714 ret <vscale x 2 x i32> %max715}716 717;718; ASR719;720 721define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){722; CHECK-LABEL: asr_i8:723; CHECK: // %bb.0:724; CHECK-NEXT: ptrue p0.b725; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b726; CHECK-NEXT: ret727 %shr = ashr <vscale x 16 x i8> %a, %b728 ret <vscale x 16 x i8> %shr729}730 731define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){732; CHECK-LABEL: asr_i16:733; CHECK: // %bb.0:734; CHECK-NEXT: ptrue p0.h735; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h736; CHECK-NEXT: ret737 %shr = ashr <vscale x 8 x i16> %a, %b738 ret <vscale x 8 x i16> %shr739}740 741define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){742; CHECK-LABEL: asr_i32:743; CHECK: // %bb.0:744; CHECK-NEXT: ptrue p0.s745; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s746; CHECK-NEXT: ret747 %shr = ashr <vscale x 4 x i32> %a, %b748 ret <vscale x 4 x i32> %shr749}750 751define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){752; CHECK-LABEL: asr_i64:753; CHECK: // %bb.0:754; CHECK-NEXT: ptrue p0.d755; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d756; CHECK-NEXT: ret757 %shr = ashr <vscale x 2 x i64> %a, %b758 ret <vscale x 2 x i64> %shr759}760 761define <vscale x 16 x i16> @asr_split_i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b){762; CHECK-LABEL: asr_split_i16:763; CHECK: // %bb.0:764; CHECK-NEXT: ptrue p0.h765; CHECK-NEXT: asr z0.h, p0/m, z0.h, z2.h766; CHECK-NEXT: asr z1.h, p0/m, z1.h, z3.h767; CHECK-NEXT: ret768 %shr = ashr <vscale x 16 x i16> %a, %b769 ret <vscale x 16 x i16> %shr770}771 772define <vscale x 2 x i32> @asr_promote_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b){773; CHECK-LABEL: asr_promote_i32:774; CHECK: // %bb.0:775; CHECK-NEXT: ptrue p0.d776; CHECK-NEXT: and z1.d, z1.d, #0xffffffff777; CHECK-NEXT: sxtw z0.d, p0/m, z0.d778; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d779; CHECK-NEXT: ret780 %shr = ashr <vscale x 2 x i32> %a, %b781 ret <vscale x 2 x i32> %shr782}783 784;785; ASRR786;787 788define <vscale x 16 x i8> @asrr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){789; CHECK-LABEL: asrr_i8:790; CHECK: // %bb.0:791; CHECK-NEXT: ptrue p0.b792; CHECK-NEXT: asrr z0.b, p0/m, z0.b, z1.b793; CHECK-NEXT: ret794 %shr = ashr <vscale x 16 x i8> %b, %a795 ret <vscale x 16 x i8> %shr796}797 798define <vscale x 8 x i16> @asrr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){799; CHECK-LABEL: asrr_i16:800; CHECK: // %bb.0:801; CHECK-NEXT: ptrue p0.h802; CHECK-NEXT: asrr z0.h, p0/m, z0.h, z1.h803; CHECK-NEXT: ret804 %shr = ashr <vscale x 8 x i16> %b, %a805 ret <vscale x 8 x i16> %shr806}807 808define <vscale x 4 x i32> @asrr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){809; CHECK-LABEL: asrr_i32:810; CHECK: // %bb.0:811; CHECK-NEXT: ptrue p0.s812; CHECK-NEXT: asrr z0.s, p0/m, z0.s, z1.s813; CHECK-NEXT: ret814 %shr = ashr <vscale x 4 x i32> %b, %a815 ret <vscale x 4 x i32> %shr816}817 818define <vscale x 2 x i64> @asrr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){819; CHECK-LABEL: asrr_i64:820; CHECK: // %bb.0:821; CHECK-NEXT: ptrue p0.d822; CHECK-NEXT: asrr z0.d, p0/m, z0.d, z1.d823; CHECK-NEXT: ret824 %shr = ashr <vscale x 2 x i64> %b, %a825 ret <vscale x 2 x i64> %shr826}827 828;829; LSL830;831 832define <vscale x 16 x i8> @lsl_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){833; CHECK-LABEL: lsl_i8:834; CHECK: // %bb.0:835; CHECK-NEXT: ptrue p0.b836; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b837; CHECK-NEXT: ret838 %shl = shl <vscale x 16 x i8> %a, %b839 ret <vscale x 16 x i8> %shl840}841 842define <vscale x 8 x i16> @lsl_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){843; CHECK-LABEL: lsl_i16:844; CHECK: // %bb.0:845; CHECK-NEXT: ptrue p0.h846; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h847; CHECK-NEXT: ret848 %shl = shl <vscale x 8 x i16> %a, %b849 ret <vscale x 8 x i16> %shl850}851 852define <vscale x 4 x i32> @lsl_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){853; CHECK-LABEL: lsl_i32:854; CHECK: // %bb.0:855; CHECK-NEXT: ptrue p0.s856; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s857; CHECK-NEXT: ret858 %shl = shl <vscale x 4 x i32> %a, %b859 ret <vscale x 4 x i32> %shl860}861 862define <vscale x 2 x i64> @lsl_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){863; CHECK-LABEL: lsl_i64:864; CHECK: // %bb.0:865; CHECK-NEXT: ptrue p0.d866; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d867; CHECK-NEXT: ret868 %shl = shl <vscale x 2 x i64> %a, %b869 ret <vscale x 2 x i64> %shl870}871 872define <vscale x 4 x i64> @lsl_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b){873; CHECK-LABEL: lsl_split_i64:874; CHECK: // %bb.0:875; CHECK-NEXT: ptrue p0.d876; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z2.d877; CHECK-NEXT: lsl z1.d, p0/m, z1.d, z3.d878; CHECK-NEXT: ret879 %shl = shl <vscale x 4 x i64> %a, %b880 ret <vscale x 4 x i64> %shl881}882 883define <vscale x 4 x i16> @lsl_promote_i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b){884; CHECK-LABEL: lsl_promote_i16:885; CHECK: // %bb.0:886; CHECK-NEXT: and z1.s, z1.s, #0xffff887; CHECK-NEXT: ptrue p0.s888; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s889; CHECK-NEXT: ret890 %shl = shl <vscale x 4 x i16> %a, %b891 ret <vscale x 4 x i16> %shl892}893 894;895; LSLR896;897 898define <vscale x 16 x i8> @lslr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){899; CHECK-LABEL: lslr_i8:900; CHECK: // %bb.0:901; CHECK-NEXT: ptrue p0.b902; CHECK-NEXT: lslr z0.b, p0/m, z0.b, z1.b903; CHECK-NEXT: ret904 %shl = shl <vscale x 16 x i8> %b, %a905 ret <vscale x 16 x i8> %shl906}907 908define <vscale x 8 x i16> @lslr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){909; CHECK-LABEL: lslr_i16:910; CHECK: // %bb.0:911; CHECK-NEXT: ptrue p0.h912; CHECK-NEXT: lslr z0.h, p0/m, z0.h, z1.h913; CHECK-NEXT: ret914 %shl = shl <vscale x 8 x i16> %b, %a915 ret <vscale x 8 x i16> %shl916}917 918define <vscale x 4 x i32> @lslr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){919; CHECK-LABEL: lslr_i32:920; CHECK: // %bb.0:921; CHECK-NEXT: ptrue p0.s922; CHECK-NEXT: lslr z0.s, p0/m, z0.s, z1.s923; CHECK-NEXT: ret924 %shl = shl <vscale x 4 x i32> %b, %a925 ret <vscale x 4 x i32> %shl926}927 928define <vscale x 2 x i64> @lslr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){929; CHECK-LABEL: lslr_i64:930; CHECK: // %bb.0:931; CHECK-NEXT: ptrue p0.d932; CHECK-NEXT: lslr z0.d, p0/m, z0.d, z1.d933; CHECK-NEXT: ret934 %shl = shl <vscale x 2 x i64> %b, %a935 ret <vscale x 2 x i64> %shl936}937 938;939; LSR940;941 942define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){943; CHECK-LABEL: lsr_i8:944; CHECK: // %bb.0:945; CHECK-NEXT: ptrue p0.b946; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b947; CHECK-NEXT: ret948 %shr = lshr <vscale x 16 x i8> %a, %b949 ret <vscale x 16 x i8> %shr950}951 952define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){953; CHECK-LABEL: lsr_i16:954; CHECK: // %bb.0:955; CHECK-NEXT: ptrue p0.h956; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h957; CHECK-NEXT: ret958 %shr = lshr <vscale x 8 x i16> %a, %b959 ret <vscale x 8 x i16> %shr960}961 962define <vscale x 4 x i32> @lsr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){963; CHECK-LABEL: lsr_i32:964; CHECK: // %bb.0:965; CHECK-NEXT: ptrue p0.s966; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s967; CHECK-NEXT: ret968 %shr = lshr <vscale x 4 x i32> %a, %b969 ret <vscale x 4 x i32> %shr970}971 972define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){973; CHECK-LABEL: lsr_i64:974; CHECK: // %bb.0:975; CHECK-NEXT: ptrue p0.d976; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d977; CHECK-NEXT: ret978 %shr = lshr <vscale x 2 x i64> %a, %b979 ret <vscale x 2 x i64> %shr980}981 982define <vscale x 8 x i8> @lsr_promote_i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b){983; CHECK-LABEL: lsr_promote_i8:984; CHECK: // %bb.0:985; CHECK-NEXT: and z1.h, z1.h, #0xff986; CHECK-NEXT: and z0.h, z0.h, #0xff987; CHECK-NEXT: ptrue p0.h988; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h989; CHECK-NEXT: ret990 %shr = lshr <vscale x 8 x i8> %a, %b991 ret <vscale x 8 x i8> %shr992}993 994define <vscale x 8 x i32> @lsr_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b){995; CHECK-LABEL: lsr_split_i32:996; CHECK: // %bb.0:997; CHECK-NEXT: ptrue p0.s998; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z2.s999; CHECK-NEXT: lsr z1.s, p0/m, z1.s, z3.s1000; CHECK-NEXT: ret1001 %shr = lshr <vscale x 8 x i32> %a, %b1002 ret <vscale x 8 x i32> %shr1003}1004 1005;1006; LSRR1007;1008 1009define <vscale x 16 x i8> @lsrr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){1010; CHECK-LABEL: lsrr_i8:1011; CHECK: // %bb.0:1012; CHECK-NEXT: ptrue p0.b1013; CHECK-NEXT: lsrr z0.b, p0/m, z0.b, z1.b1014; CHECK-NEXT: ret1015 %shr = lshr <vscale x 16 x i8> %b, %a1016 ret <vscale x 16 x i8> %shr1017}1018 1019define <vscale x 8 x i16> @lsrr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){1020; CHECK-LABEL: lsrr_i16:1021; CHECK: // %bb.0:1022; CHECK-NEXT: ptrue p0.h1023; CHECK-NEXT: lsrr z0.h, p0/m, z0.h, z1.h1024; CHECK-NEXT: ret1025 %shr = lshr <vscale x 8 x i16> %b, %a1026 ret <vscale x 8 x i16> %shr1027}1028 1029define <vscale x 4 x i32> @lsrr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){1030; CHECK-LABEL: lsrr_i32:1031; CHECK: // %bb.0:1032; CHECK-NEXT: ptrue p0.s1033; CHECK-NEXT: lsrr z0.s, p0/m, z0.s, z1.s1034; CHECK-NEXT: ret1035 %shr = lshr <vscale x 4 x i32> %b, %a1036 ret <vscale x 4 x i32> %shr1037}1038 1039define <vscale x 2 x i64> @lsrr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){1040; CHECK-LABEL: lsrr_i64:1041; CHECK: // %bb.0:1042; CHECK-NEXT: ptrue p0.d1043; CHECK-NEXT: lsrr z0.d, p0/m, z0.d, z1.d1044; CHECK-NEXT: ret1045 %shr = lshr <vscale x 2 x i64> %b, %a1046 ret <vscale x 2 x i64> %shr1047}1048 1049;1050; CMP1051;1052 1053define <vscale x 32 x i1> @cmp_split_32(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) {1054; CHECK-LABEL: cmp_split_32:1055; CHECK: // %bb.0:1056; CHECK-NEXT: ptrue p1.b1057; CHECK-NEXT: cmpgt p0.b, p1/z, z2.b, z0.b1058; CHECK-NEXT: cmpgt p1.b, p1/z, z3.b, z1.b1059; CHECK-NEXT: ret1060 %cmp = icmp slt <vscale x 32 x i8> %a, %b1061 ret <vscale x 32 x i1> %cmp1062}1063 1064define <vscale x 64 x i1> @cmp_split_64(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) {1065; CHECK-LABEL: cmp_split_64:1066; CHECK: // %bb.0:1067; CHECK-NEXT: ptrue p3.b1068; CHECK-NEXT: cmpgt p0.b, p3/z, z0.b, z4.b1069; CHECK-NEXT: cmpgt p1.b, p3/z, z1.b, z5.b1070; CHECK-NEXT: cmpgt p2.b, p3/z, z2.b, z6.b1071; CHECK-NEXT: cmpgt p3.b, p3/z, z3.b, z7.b1072; CHECK-NEXT: ret1073 %cmp = icmp sgt <vscale x 64 x i8> %a, %b1074 ret <vscale x 64 x i1> %cmp1075}1076 1077; Funnel shifts1078declare <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)1079declare <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>)1080declare <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)1081define <vscale x 2 x i64> @fshl_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c){1082; CHECK-LABEL: fshl_i64:1083; CHECK: // %bb.0:1084; CHECK-NEXT: mov z3.d, #63 // =0x3f1085; CHECK-NEXT: mov z4.d, z2.d1086; CHECK-NEXT: lsr z1.d, z1.d, #11087; CHECK-NEXT: ptrue p0.d1088; CHECK-NEXT: bic z2.d, z3.d, z2.d1089; CHECK-NEXT: and z4.d, z4.d, #0x3f1090; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z4.d1091; CHECK-NEXT: lsr z1.d, p0/m, z1.d, z2.d1092; CHECK-NEXT: orr z0.d, z0.d, z1.d1093; CHECK-NEXT: ret1094 %fshl = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)1095 ret <vscale x 2 x i64> %fshl1096}1097 1098define <vscale x 4 x i64> @fshl_illegal_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c){1099; CHECK-LABEL: fshl_illegal_i64:1100; CHECK: // %bb.0:1101; CHECK-NEXT: mov z6.d, #63 // =0x3f1102; CHECK-NEXT: lsr z2.d, z2.d, #11103; CHECK-NEXT: lsr z3.d, z3.d, #11104; CHECK-NEXT: ptrue p0.d1105; CHECK-NEXT: bic z7.d, z6.d, z4.d1106; CHECK-NEXT: and z4.d, z4.d, #0x3f1107; CHECK-NEXT: bic z6.d, z6.d, z5.d1108; CHECK-NEXT: and z5.d, z5.d, #0x3f1109; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z4.d1110; CHECK-NEXT: lsr z2.d, p0/m, z2.d, z7.d1111; CHECK-NEXT: lsr z3.d, p0/m, z3.d, z6.d1112; CHECK-NEXT: lsl z1.d, p0/m, z1.d, z5.d1113; CHECK-NEXT: orr z0.d, z0.d, z2.d1114; CHECK-NEXT: orr z1.d, z1.d, z3.d1115; CHECK-NEXT: ret1116 %fshl = call <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c)1117 ret <vscale x 4 x i64> %fshl1118}1119 1120define <vscale x 2 x i64> @fshl_rot_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){1121; CHECK-LABEL: fshl_rot_i64:1122; CHECK: // %bb.0:1123; CHECK-NEXT: mov z2.d, z1.d1124; CHECK-NEXT: subr z1.d, z1.d, #0 // =0x01125; CHECK-NEXT: ptrue p0.d1126; CHECK-NEXT: and z2.d, z2.d, #0x3f1127; CHECK-NEXT: and z1.d, z1.d, #0x3f1128; CHECK-NEXT: lslr z2.d, p0/m, z2.d, z0.d1129; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d1130; CHECK-NEXT: orr z0.d, z2.d, z0.d1131; CHECK-NEXT: ret1132 %fshl = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b)1133 ret <vscale x 2 x i64> %fshl1134}1135 1136 1137define <vscale x 4 x i64> @fshl_rot_illegal_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b){1138; CHECK-LABEL: fshl_rot_illegal_i64:1139; CHECK: // %bb.0:1140; CHECK-NEXT: mov z4.d, z2.d1141; CHECK-NEXT: subr z2.d, z2.d, #0 // =0x01142; CHECK-NEXT: mov z5.d, z3.d1143; CHECK-NEXT: subr z3.d, z3.d, #0 // =0x01144; CHECK-NEXT: ptrue p0.d1145; CHECK-NEXT: and z4.d, z4.d, #0x3f1146; CHECK-NEXT: and z2.d, z2.d, #0x3f1147; CHECK-NEXT: and z5.d, z5.d, #0x3f1148; CHECK-NEXT: and z3.d, z3.d, #0x3f1149; CHECK-NEXT: lslr z4.d, p0/m, z4.d, z0.d1150; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z2.d1151; CHECK-NEXT: lslr z5.d, p0/m, z5.d, z1.d1152; CHECK-NEXT: lsr z1.d, p0/m, z1.d, z3.d1153; CHECK-NEXT: orr z0.d, z4.d, z0.d1154; CHECK-NEXT: orr z1.d, z5.d, z1.d1155; CHECK-NEXT: ret1156 %fshl = call <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b)1157 ret <vscale x 4 x i64> %fshl1158}1159 1160define <vscale x 2 x i64> @fshl_rot_const_i64(<vscale x 2 x i64> %a){1161; CHECK-LABEL: fshl_rot_const_i64:1162; CHECK: // %bb.0:1163; CHECK-NEXT: lsr z1.d, z0.d, #611164; CHECK-NEXT: lsl z0.d, z0.d, #31165; CHECK-NEXT: orr z0.d, z0.d, z1.d1166; CHECK-NEXT: ret1167 %fshl = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 3))1168 ret <vscale x 2 x i64> %fshl1169}1170 1171define <vscale x 2 x i64> @fshr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c){1172; CHECK-LABEL: fshr_i64:1173; CHECK: // %bb.0:1174; CHECK-NEXT: mov z3.d, #63 // =0x3f1175; CHECK-NEXT: mov z4.d, z2.d1176; CHECK-NEXT: lsl z0.d, z0.d, #11177; CHECK-NEXT: ptrue p0.d1178; CHECK-NEXT: bic z2.d, z3.d, z2.d1179; CHECK-NEXT: and z4.d, z4.d, #0x3f1180; CHECK-NEXT: lsr z1.d, p0/m, z1.d, z4.d1181; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z2.d1182; CHECK-NEXT: orr z0.d, z0.d, z1.d1183; CHECK-NEXT: ret1184 %fshr = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)1185 ret <vscale x 2 x i64> %fshr1186}1187 1188define <vscale x 2 x i64> @fshr_rot_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){1189; CHECK-LABEL: fshr_rot_i64:1190; CHECK: // %bb.0:1191; CHECK-NEXT: mov z2.d, z1.d1192; CHECK-NEXT: subr z1.d, z1.d, #0 // =0x01193; CHECK-NEXT: ptrue p0.d1194; CHECK-NEXT: and z2.d, z2.d, #0x3f1195; CHECK-NEXT: and z1.d, z1.d, #0x3f1196; CHECK-NEXT: lsrr z2.d, p0/m, z2.d, z0.d1197; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d1198; CHECK-NEXT: orr z0.d, z2.d, z0.d1199; CHECK-NEXT: ret1200 %fshr = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b)1201 ret <vscale x 2 x i64> %fshr1202}1203