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1; RUN: opt -mtriple=aarch64-linux-gnu -mattr=+sve -passes=scalarize-masked-mem-intrin -S < %s | FileCheck %s2 3; Testing that masked gathers operating on scalable vectors that are4; packed in SVE registers are not scalarized.5 6; CHECK-LABEL: @masked_gather_nxv4i32(7; CHECK: call <vscale x 4 x i32> @llvm.masked.gather.nxv4i328define <vscale x 4 x i32> @masked_gather_nxv4i32(<vscale x 4 x ptr> %ld, <vscale x 4 x i1> %masks, <vscale x 4 x i32> %passthru) {9 %res = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32(<vscale x 4 x ptr> %ld, i32 0, <vscale x 4 x i1> %masks, <vscale x 4 x i32> %passthru)10 ret <vscale x 4 x i32> %res11}12 13; Testing that masked gathers operating on scalable vectors of FP data14; that is packed in SVE registers are not scalarized.15 16; CHECK-LABEL: @masked_gather_nxv2f64(17; CHECK: call <vscale x 2 x double> @llvm.masked.gather.nxv2f6418define <vscale x 2 x double> @masked_gather_nxv2f64(<vscale x 2 x ptr> %ld, <vscale x 2 x i1> %masks, <vscale x 2 x double> %passthru) {19 %res = call <vscale x 2 x double> @llvm.masked.gather.nxv2f64(<vscale x 2 x ptr> %ld, i32 0, <vscale x 2 x i1> %masks, <vscale x 2 x double> %passthru)20 ret <vscale x 2 x double> %res21}22 23; Testing that masked gathers operating on scalable vectors of FP data24; that is unpacked in SVE registers are not scalarized.25 26; CHECK-LABEL: @masked_gather_nxv2f16(27; CHECK: call <vscale x 2 x half> @llvm.masked.gather.nxv2f1628define <vscale x 2 x half> @masked_gather_nxv2f16(<vscale x 2 x ptr> %ld, <vscale x 2 x i1> %masks, <vscale x 2 x half> %passthru) {29 %res = call <vscale x 2 x half> @llvm.masked.gather.nxv2f16(<vscale x 2 x ptr> %ld, i32 0, <vscale x 2 x i1> %masks, <vscale x 2 x half> %passthru)30 ret <vscale x 2 x half> %res31}32 33; Testing that masked gathers operating on 64-bit fixed vectors are34; scalarized because NEON doesn't have support for masked gather35; instructions.36 37; CHECK-LABEL: @masked_gather_v2f32(38; CHECK-NOT: @llvm.masked.gather.v2f32(39define <2 x float> @masked_gather_v2f32(<2 x ptr> %ld, <2 x i1> %masks, <2 x float> %passthru) {40 %res = call <2 x float> @llvm.masked.gather.v2f32(<2 x ptr> %ld, i32 0, <2 x i1> %masks, <2 x float> %passthru)41 ret <2 x float> %res42}43 44; Testing that masked gathers operating on 128-bit fixed vectors are45; scalarized because NEON doesn't have support for masked gather46; instructions and because we are not targeting fixed width SVE.47 48; CHECK-LABEL: @masked_gather_v4i32(49; CHECK-NOT: @llvm.masked.gather.v4i32(50define <4 x i32> @masked_gather_v4i32(<4 x ptr> %ld, <4 x i1> %masks, <4 x i32> %passthru) {51 %res = call <4 x i32> @llvm.masked.gather.v4i32(<4 x ptr> %ld, i32 0, <4 x i1> %masks, <4 x i32> %passthru)52 ret <4 x i32> %res53}54 55declare <vscale x 4 x i32> @llvm.masked.gather.nxv4i32(<vscale x 4 x ptr> %ptrs, i32 %align, <vscale x 4 x i1> %masks, <vscale x 4 x i32> %passthru)56declare <vscale x 2 x double> @llvm.masked.gather.nxv2f64(<vscale x 2 x ptr> %ptrs, i32 %align, <vscale x 2 x i1> %masks, <vscale x 2 x double> %passthru)57declare <vscale x 2 x half> @llvm.masked.gather.nxv2f16(<vscale x 2 x ptr> %ptrs, i32 %align, <vscale x 2 x i1> %masks, <vscale x 2 x half> %passthru)58declare <2 x float> @llvm.masked.gather.v2f32(<2 x ptr> %ptrs, i32 %align, <2 x i1> %masks, <2 x float> %passthru)59declare <4 x i32> @llvm.masked.gather.v4i32(<4 x ptr> %ptrs, i32 %align, <4 x i1> %masks, <4 x i32> %passthru)60