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1; RUN: opt -mtriple=aarch64-linux-gnu -mattr=+sve -passes=scalarize-masked-mem-intrin -S < %s | FileCheck %s2 3; Testing that masked scatters operating on scalable vectors that are4; packed in SVE registers are not scalarized.5 6; CHECK-LABEL: @masked_scatter_nxv4i32(7; CHECK: call void @llvm.masked.scatter.nxv4i328define void @masked_scatter_nxv4i32(<vscale x 4 x i32> %data, <vscale x 4 x ptr> %ptrs, <vscale x 4 x i1> %masks) {9 call void @llvm.masked.scatter.nxv4i32(<vscale x 4 x i32> %data, <vscale x 4 x ptr> %ptrs, i32 0, <vscale x 4 x i1> %masks)10 ret void11}12 13; Testing that masked scatters operating on scalable vectors of FP14; data that is packed in SVE registers are not scalarized.15 16; CHECK-LABEL: @masked_scatter_nxv2f64(17; CHECK: call void @llvm.masked.scatter.nxv2f6418define void @masked_scatter_nxv2f64(<vscale x 2 x double> %data, <vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> %masks) {19 call void @llvm.masked.scatter.nxv2f64(<vscale x 2 x double> %data, <vscale x 2 x ptr> %ptrs, i32 0, <vscale x 2 x i1> %masks)20 ret void21}22 23; Testing that masked scatters operating on scalable vectors of FP24; data that is unpacked in SVE registers are not scalarized.25 26; CHECK-LABEL: @masked_scatter_nxv2f16(27; CHECK: call void @llvm.masked.scatter.nxv2f1628define void @masked_scatter_nxv2f16(<vscale x 2 x half> %data, <vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> %masks) {29 call void @llvm.masked.scatter.nxv2f16(<vscale x 2 x half> %data, <vscale x 2 x ptr> %ptrs, i32 0, <vscale x 2 x i1> %masks)30 ret void31}32 33; Testing that masked scatters operating on 64-bit fixed vectors are34; scalarized because NEON doesn't have support for masked scatter35; instructions.36 37; CHECK-LABEL: @masked_scatter_v2f32(38; CHECK-NOT: @llvm.masked.scatter.v2f32(39define void @masked_scatter_v2f32(<2 x float> %data, <2 x ptr> %ptrs, <2 x i1> %masks) {40 call void @llvm.masked.scatter.v2f32(<2 x float> %data, <2 x ptr> %ptrs, i32 0, <2 x i1> %masks)41 ret void42}43 44; Testing that masked scatters operating on 128-bit fixed vectors are45; scalarized because NEON doesn't have support for masked scatter46; instructions and because we are not targeting fixed width SVE.47 48; CHECK-LABEL: @masked_scatter_v4i32(49; CHECK-NOT: @llvm.masked.scatter.v4i32(50define void @masked_scatter_v4i32(<4 x i32> %data, <4 x ptr> %ptrs, <4 x i1> %masks) {51 call void @llvm.masked.scatter.v4i32(<4 x i32> %data, <4 x ptr> %ptrs, i32 0, <4 x i1> %masks)52 ret void53}54 55declare void @llvm.masked.scatter.nxv4i32(<vscale x 4 x i32> %data, <vscale x 4 x ptr> %ptrs, i32 %align, <vscale x 4 x i1> %masks)56declare void @llvm.masked.scatter.nxv2f64(<vscale x 2 x double> %data, <vscale x 2 x ptr> %ptrs, i32 %align, <vscale x 2 x i1> %masks)57declare void @llvm.masked.scatter.nxv2f16(<vscale x 2 x half> %data, <vscale x 2 x ptr> %ptrs, i32 %align, <vscale x 2 x i1> %masks)58declare void @llvm.masked.scatter.v2f32(<2 x float> %data, <2 x ptr> %ptrs, i32 %align, <2 x i1> %masks)59declare void @llvm.masked.scatter.v4i32(<4 x i32> %data, <4 x ptr> %ptrs, i32 %align, <4 x i1> %masks)60