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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; ===== Legal Scalars =====6 7define i8 @load_i8(ptr %ptr) {8; CHECK-LABEL: load_i8:9; CHECK: // %bb.0:10; CHECK-NEXT: ldrb w0, [x0]11; CHECK-NEXT: ret12 %a = load i8, ptr %ptr13 ret i8 %a14}15 16define i16 @load_i8_s16(ptr %ptr) {17; CHECK-LABEL: load_i8_s16:18; CHECK: // %bb.0:19; CHECK-NEXT: ldrsb w0, [x0]20; CHECK-NEXT: ret21 %a = load i8, ptr %ptr22 %s = sext i8 %a to i1623 ret i16 %s24}25 26define i16 @load_i8_u16(ptr %ptr) {27; CHECK-LABEL: load_i8_u16:28; CHECK: // %bb.0:29; CHECK-NEXT: ldrb w0, [x0]30; CHECK-NEXT: ret31 %a = load i8, ptr %ptr32 %s = zext i8 %a to i1633 ret i16 %s34}35 36define i32 @load_i8_s32(ptr %ptr) {37; CHECK-LABEL: load_i8_s32:38; CHECK: // %bb.0:39; CHECK-NEXT: ldrsb w0, [x0]40; CHECK-NEXT: ret41 %a = load i8, ptr %ptr42 %s = sext i8 %a to i3243 ret i32 %s44}45 46define i32 @load_i8_u32(ptr %ptr) {47; CHECK-LABEL: load_i8_u32:48; CHECK: // %bb.0:49; CHECK-NEXT: ldrb w0, [x0]50; CHECK-NEXT: ret51 %a = load i8, ptr %ptr52 %s = zext i8 %a to i3253 ret i32 %s54}55 56define i64 @load_i8_s64(ptr %ptr) {57; CHECK-LABEL: load_i8_s64:58; CHECK: // %bb.0:59; CHECK-NEXT: ldrsb x0, [x0]60; CHECK-NEXT: ret61 %a = load i8, ptr %ptr62 %s = sext i8 %a to i6463 ret i64 %s64}65 66define i64 @load_i8_u64(ptr %ptr) {67; CHECK-LABEL: load_i8_u64:68; CHECK: // %bb.0:69; CHECK-NEXT: ldrb w0, [x0]70; CHECK-NEXT: ret71 %a = load i8, ptr %ptr72 %s = zext i8 %a to i6473 ret i64 %s74}75 76define i16 @load_i16(ptr %ptr) {77; CHECK-LABEL: load_i16:78; CHECK: // %bb.0:79; CHECK-NEXT: ldrh w0, [x0]80; CHECK-NEXT: ret81 %a = load i16, ptr %ptr82 ret i16 %a83}84 85define i32 @load_i16_s32(ptr %ptr) {86; CHECK-LABEL: load_i16_s32:87; CHECK: // %bb.0:88; CHECK-NEXT: ldrsh w0, [x0]89; CHECK-NEXT: ret90 %a = load i16, ptr %ptr91 %s = sext i16 %a to i3292 ret i32 %s93}94 95define i32 @load_i16_u32(ptr %ptr) {96; CHECK-LABEL: load_i16_u32:97; CHECK: // %bb.0:98; CHECK-NEXT: ldrh w0, [x0]99; CHECK-NEXT: ret100 %a = load i16, ptr %ptr101 %s = zext i16 %a to i32102 ret i32 %s103}104 105define i64 @load_i16_s64(ptr %ptr) {106; CHECK-LABEL: load_i16_s64:107; CHECK: // %bb.0:108; CHECK-NEXT: ldrsh x0, [x0]109; CHECK-NEXT: ret110 %a = load i16, ptr %ptr111 %s = sext i16 %a to i64112 ret i64 %s113}114 115define i64 @load_i16_u64(ptr %ptr) {116; CHECK-LABEL: load_i16_u64:117; CHECK: // %bb.0:118; CHECK-NEXT: ldrh w0, [x0]119; CHECK-NEXT: ret120 %a = load i16, ptr %ptr121 %s = zext i16 %a to i64122 ret i64 %s123}124 125define i32 @load_i32(ptr %ptr) {126; CHECK-LABEL: load_i32:127; CHECK: // %bb.0:128; CHECK-NEXT: ldr w0, [x0]129; CHECK-NEXT: ret130 %a = load i32, ptr %ptr131 ret i32 %a132}133 134define i64 @load_i32_s64(ptr %ptr) {135; CHECK-LABEL: load_i32_s64:136; CHECK: // %bb.0:137; CHECK-NEXT: ldrsw x0, [x0]138; CHECK-NEXT: ret139 %a = load i32, ptr %ptr140 %s = sext i32 %a to i64141 ret i64 %s142}143 144define i64 @load_i32_u64(ptr %ptr) {145; CHECK-LABEL: load_i32_u64:146; CHECK: // %bb.0:147; CHECK-NEXT: ldr w0, [x0]148; CHECK-NEXT: ret149 %a = load i32, ptr %ptr150 %s = zext i32 %a to i64151 ret i64 %s152}153 154define i64 @load_i64(ptr %ptr) {155; CHECK-LABEL: load_i64:156; CHECK: // %bb.0:157; CHECK-NEXT: ldr x0, [x0]158; CHECK-NEXT: ret159 %a = load i64, ptr %ptr160 ret i64 %a161}162 163; ===== Legal Vector Types =====164 165define <8 x i8> @load_v8i8(ptr %ptr) {166; CHECK-LABEL: load_v8i8:167; CHECK: // %bb.0:168; CHECK-NEXT: ldr d0, [x0]169; CHECK-NEXT: ret170 %a = load <8 x i8>, ptr %ptr171 ret <8 x i8> %a172}173 174define <16 x i8> @load_v16i8(ptr %ptr) {175; CHECK-LABEL: load_v16i8:176; CHECK: // %bb.0:177; CHECK-NEXT: ldr q0, [x0]178; CHECK-NEXT: ret179 %a = load <16 x i8>, ptr %ptr180 ret <16 x i8> %a181}182 183define <4 x i16> @load_v4i16(ptr %ptr) {184; CHECK-LABEL: load_v4i16:185; CHECK: // %bb.0:186; CHECK-NEXT: ldr d0, [x0]187; CHECK-NEXT: ret188 %a = load <4 x i16>, ptr %ptr189 ret <4 x i16> %a190}191 192define <8 x i16> @load_v8i16(ptr %ptr) {193; CHECK-LABEL: load_v8i16:194; CHECK: // %bb.0:195; CHECK-NEXT: ldr q0, [x0]196; CHECK-NEXT: ret197 %a = load <8 x i16>, ptr %ptr198 ret <8 x i16> %a199}200 201define <2 x i32> @load_v2i32(ptr %ptr) {202; CHECK-LABEL: load_v2i32:203; CHECK: // %bb.0:204; CHECK-NEXT: ldr d0, [x0]205; CHECK-NEXT: ret206 %a = load <2 x i32>, ptr %ptr207 ret <2 x i32> %a208}209 210define <4 x i32> @load_v4i32(ptr %ptr) {211; CHECK-LABEL: load_v4i32:212; CHECK: // %bb.0:213; CHECK-NEXT: ldr q0, [x0]214; CHECK-NEXT: ret215 %a = load <4 x i32>, ptr %ptr216 ret <4 x i32> %a217}218 219define <2 x i64> @load_v2i64(ptr %ptr) {220; CHECK-LABEL: load_v2i64:221; CHECK: // %bb.0:222; CHECK-NEXT: ldr q0, [x0]223; CHECK-NEXT: ret224 %a = load <2 x i64>, ptr %ptr225 ret <2 x i64> %a226}227 228; ===== Smaller/Larger Width Vectors with Legal Element Sizes =====229 230define <2 x i8> @load_v2i8(ptr %ptr, <2 x i8> %b) {231; CHECK-SD-LABEL: load_v2i8:232; CHECK-SD: // %bb.0:233; CHECK-SD-NEXT: ldr h0, [x0]234; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0235; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0236; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0237; CHECK-SD-NEXT: ret238;239; CHECK-GI-LABEL: load_v2i8:240; CHECK-GI: // %bb.0:241; CHECK-GI-NEXT: ld1 { v0.b }[0], [x0]242; CHECK-GI-NEXT: ldr b1, [x0, #1]243; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]244; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0245; CHECK-GI-NEXT: ret246 %a = load <2 x i8>, ptr %ptr247 ret <2 x i8> %a248}249 250define i32 @load_v4i8(ptr %ptr, <4 x i8> %b) {251; CHECK-LABEL: load_v4i8:252; CHECK: // %bb.0:253; CHECK-NEXT: ldr w0, [x0]254; CHECK-NEXT: ret255 %a = load <4 x i8>, ptr %ptr256 %c = bitcast <4 x i8> %a to i32257 ret i32 %c258}259 260define <32 x i8> @load_v32i8(ptr %ptr) {261; CHECK-LABEL: load_v32i8:262; CHECK: // %bb.0:263; CHECK-NEXT: ldp q0, q1, [x0]264; CHECK-NEXT: ret265 %a = load <32 x i8>, ptr %ptr266 ret <32 x i8> %a267}268 269define <2 x i16> @load_v2i16(ptr %ptr) {270; CHECK-SD-LABEL: load_v2i16:271; CHECK-SD: // %bb.0:272; CHECK-SD-NEXT: ldr s0, [x0]273; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0274; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0275; CHECK-SD-NEXT: ret276;277; CHECK-GI-LABEL: load_v2i16:278; CHECK-GI: // %bb.0:279; CHECK-GI-NEXT: ld1 { v0.h }[0], [x0]280; CHECK-GI-NEXT: ldr h1, [x0, #2]281; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]282; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0283; CHECK-GI-NEXT: ret284 %a = load <2 x i16>, ptr %ptr285 ret <2 x i16> %a286}287 288define <16 x i16> @load_v16i16(ptr %ptr) {289; CHECK-LABEL: load_v16i16:290; CHECK: // %bb.0:291; CHECK-NEXT: ldp q0, q1, [x0]292; CHECK-NEXT: ret293 %a = load <16 x i16>, ptr %ptr294 ret <16 x i16> %a295}296 297define <1 x i32> @load_v1i32(ptr %ptr) {298; CHECK-LABEL: load_v1i32:299; CHECK: // %bb.0:300; CHECK-NEXT: ldr s0, [x0]301; CHECK-NEXT: ret302 %a = load <1 x i32>, ptr %ptr303 ret <1 x i32> %a304}305 306define <8 x i32> @load_v8i32(ptr %ptr) {307; CHECK-LABEL: load_v8i32:308; CHECK: // %bb.0:309; CHECK-NEXT: ldp q0, q1, [x0]310; CHECK-NEXT: ret311 %a = load <8 x i32>, ptr %ptr312 ret <8 x i32> %a313}314 315define <4 x i64> @load_v4i64(ptr %ptr) {316; CHECK-LABEL: load_v4i64:317; CHECK: // %bb.0:318; CHECK-NEXT: ldp q0, q1, [x0]319; CHECK-NEXT: ret320 %a = load <4 x i64>, ptr %ptr321 ret <4 x i64> %a322}323 324; ===== Vectors with Non-Pow 2 Widths =====325 326define <3 x i8> @load_v3i8(ptr %ptr) {327; CHECK-SD-LABEL: load_v3i8:328; CHECK-SD: // %bb.0:329; CHECK-SD-NEXT: ldr s0, [x0]330; CHECK-SD-NEXT: umov w0, v0.b[0]331; CHECK-SD-NEXT: umov w1, v0.b[1]332; CHECK-SD-NEXT: umov w2, v0.b[2]333; CHECK-SD-NEXT: ret334;335; CHECK-GI-LABEL: load_v3i8:336; CHECK-GI: // %bb.0:337; CHECK-GI-NEXT: ldr w8, [x0]338; CHECK-GI-NEXT: fmov s0, w8339; CHECK-GI-NEXT: mov b1, v0.b[1]340; CHECK-GI-NEXT: mov b2, v0.b[2]341; CHECK-GI-NEXT: fmov w0, s0342; CHECK-GI-NEXT: fmov w1, s1343; CHECK-GI-NEXT: fmov w2, s2344; CHECK-GI-NEXT: ret345 %a = load <3 x i8>, ptr %ptr346 ret <3 x i8> %a347}348 349define <7 x i8> @load_v7i8(ptr %ptr) {350; CHECK-LABEL: load_v7i8:351; CHECK: // %bb.0:352; CHECK-NEXT: ldr d0, [x0]353; CHECK-NEXT: ret354 %a = load <7 x i8>, ptr %ptr355 ret <7 x i8> %a356}357 358define <3 x i16> @load_v3i16(ptr %ptr) {359; CHECK-LABEL: load_v3i16:360; CHECK: // %bb.0:361; CHECK-NEXT: ldr d0, [x0]362; CHECK-NEXT: ret363 %a = load <3 x i16>, ptr %ptr364 ret <3 x i16> %a365}366 367define <7 x i16> @load_v7i16(ptr %ptr) {368; CHECK-LABEL: load_v7i16:369; CHECK: // %bb.0:370; CHECK-NEXT: ldr q0, [x0]371; CHECK-NEXT: ret372 %a = load <7 x i16>, ptr %ptr373 ret <7 x i16> %a374}375 376define <3 x i32> @load_v3i32(ptr %ptr) {377; CHECK-LABEL: load_v3i32:378; CHECK: // %bb.0:379; CHECK-NEXT: ldr q0, [x0]380; CHECK-NEXT: ret381 %a = load <3 x i32>, ptr %ptr382 ret <3 x i32> %a383}384 385define <2 x i128> @load_v2i128(ptr %p) {386; CHECK-SD-LABEL: load_v2i128:387; CHECK-SD: // %bb.0:388; CHECK-SD-NEXT: ldp x8, x1, [x0]389; CHECK-SD-NEXT: ldp x2, x3, [x0, #16]390; CHECK-SD-NEXT: mov x0, x8391; CHECK-SD-NEXT: ret392;393; CHECK-GI-LABEL: load_v2i128:394; CHECK-GI: // %bb.0:395; CHECK-GI-NEXT: ldp q0, q1, [x0]396; CHECK-GI-NEXT: mov d2, v0.d[1]397; CHECK-GI-NEXT: mov d3, v1.d[1]398; CHECK-GI-NEXT: fmov x0, d0399; CHECK-GI-NEXT: fmov x2, d1400; CHECK-GI-NEXT: fmov x1, d2401; CHECK-GI-NEXT: fmov x3, d3402; CHECK-GI-NEXT: ret403 %a = load <2 x i128>, ptr %p404 ret <2 x i128> %a405}406 407define <2 x fp128> @load_v2f128(ptr %p) {408; CHECK-LABEL: load_v2f128:409; CHECK: // %bb.0:410; CHECK-NEXT: ldp q0, q1, [x0]411; CHECK-NEXT: ret412 %a = load <2 x fp128>, ptr %p413 ret <2 x fp128> %a414}415 416define i32 @load_i8_s16_extrasuse(ptr %ptr, ptr %ptr2) {417; CHECK-LABEL: load_i8_s16_extrasuse:418; CHECK: // %bb.0:419; CHECK-NEXT: ldr w8, [x0]420; CHECK-NEXT: sxtb w0, w8421; CHECK-NEXT: str w8, [x1]422; CHECK-NEXT: ret423 %a = load i32, ptr %ptr424 %s = shl i32 %a, 24425 %b = ashr i32 %s, 24426 store i32 %a, ptr %ptr2427 ret i32 %b428}429