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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -O3 -mtriple arm64-linux -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-ASM3; This test checks that nomerge correctly prevents the traps from being merged4; in the compiled code.5; Prior to ae6dc64ec670891cb15049277e43133d4df7fb4b, this test showed that6; nomerge did not work correctly.7 8@B = dso_local global [10 x i8] zeroinitializer, align 19@B2 = dso_local global [10 x i8] zeroinitializer, align 110 11; Function Attrs: noinline nounwind uwtable12define dso_local void @f8(i32 noundef %i, i32 noundef %k) #0 {13; CHECK-ASM-LABEL: f8:14; CHECK-ASM: // %bb.0: // %entry15; CHECK-ASM-NEXT: sub sp, sp, #1616; CHECK-ASM-NEXT: .cfi_def_cfa_offset 1617; CHECK-ASM-NEXT: .cfi_remember_state18; CHECK-ASM-NEXT: // kill: def $w0 killed $w0 def $x019; CHECK-ASM-NEXT: sxtw x8, w020; CHECK-ASM-NEXT: stp w1, w0, [sp, #8]21; CHECK-ASM-NEXT: cmp x8, #1022; CHECK-ASM-NEXT: b.hi .LBB0_523; CHECK-ASM-NEXT: // %bb.1: // %entry24; CHECK-ASM-NEXT: mov w9, #10 // =0xa25; CHECK-ASM-NEXT: sub x9, x9, x826; CHECK-ASM-NEXT: cbz x9, .LBB0_527; CHECK-ASM-NEXT: // %bb.2:28; CHECK-ASM-NEXT: ldrsw x9, [sp, #8]29; CHECK-ASM-NEXT: adrp x10, .L_MergedGlobals30; CHECK-ASM-NEXT: add x10, x10, :lo12:.L_MergedGlobals31; CHECK-ASM-NEXT: strb wzr, [x10, x8]32; CHECK-ASM-NEXT: cmp x9, #1033; CHECK-ASM-NEXT: b.hi .LBB0_634; CHECK-ASM-NEXT: // %bb.3:35; CHECK-ASM-NEXT: mov w8, #10 // =0xa36; CHECK-ASM-NEXT: sub x8, x8, x937; CHECK-ASM-NEXT: cbz x8, .LBB0_638; CHECK-ASM-NEXT: // %bb.4:39; CHECK-ASM-NEXT: add x8, x10, x940; CHECK-ASM-NEXT: strb wzr, [x8, #10]41; CHECK-ASM-NEXT: add sp, sp, #1642; CHECK-ASM-NEXT: .cfi_def_cfa_offset 043; CHECK-ASM-NEXT: ret44; CHECK-ASM-NEXT: .LBB0_5: // %trap45; CHECK-ASM-NEXT: .cfi_restore_state46; CHECK-ASM-NEXT: brk #0x147; CHECK-ASM-NEXT: .LBB0_6: // %trap348; CHECK-ASM-NEXT: brk #0x149entry:50 %i.addr = alloca i32, align 451 %k.addr = alloca i32, align 452 store i32 %i, ptr %i.addr, align 453 store i32 %k, ptr %k.addr, align 454 %0 = load i32, ptr %i.addr, align 455 %idxprom = sext i32 %0 to i6456 %1 = add i64 0, %idxprom57 %arrayidx = getelementptr inbounds [10 x i8], ptr @B, i64 0, i64 %idxprom58 %2 = sub i64 10, %159 %3 = icmp ult i64 10, %160 %4 = icmp ult i64 %2, 161 %5 = or i1 %3, %462 br i1 %5, label %trap, label %663 646: ; preds = %entry65 store i8 0, ptr %arrayidx, align 166 %7 = load i32, ptr %k.addr, align 467 %idxprom1 = sext i32 %7 to i6468 %8 = add i64 0, %idxprom169 %arrayidx2 = getelementptr inbounds [10 x i8], ptr @B2, i64 0, i64 %idxprom170 %9 = sub i64 10, %871 %10 = icmp ult i64 10, %872 %11 = icmp ult i64 %9, 173 %12 = or i1 %10, %1174 br i1 %12, label %trap3, label %1375 7613: ; preds = %677 store i8 0, ptr %arrayidx2, align 178 ret void79 80trap: ; preds = %entry81 call void @llvm.trap() #282 unreachable83 84trap3: ; preds = %685 call void @llvm.trap() #286 unreachable87}88 89; Function Attrs: cold noreturn nounwind memory(inaccessiblemem: write)90declare void @llvm.trap() #191 92attributes #0 = { noinline nounwind uwtable }93attributes #1 = { cold noreturn nounwind memory(inaccessiblemem: write) }94attributes #2 = { noreturn nounwind nomerge }95