239 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s3 4define i64 @and_bic(i64 %0, i64 %1) {5; CHECK-LABEL: and_bic:6; CHECK: // %bb.0:7; CHECK-NEXT: mvn w8, w08; CHECK-NEXT: orr x8, x8, #0xffffffffffff00ff9; CHECK-NEXT: and x0, x8, x110; CHECK-NEXT: ret11 %3 = and i64 %0, 6528012 %4 = xor i64 %3, -113 %5 = and i64 %4, %114 ret i64 %515}16 17define i64 @and_bic2(i32 %0, i64 %1) {18; CHECK-LABEL: and_bic2:19; CHECK: // %bb.0:20; CHECK-NEXT: mvn w8, w021; CHECK-NEXT: orr w8, w8, #0xffff00ff22; CHECK-NEXT: and x0, x8, x123; CHECK-NEXT: ret24 %3 = and i32 %0, 6528025 %4 = xor i32 %3, -126 %5 = zext i32 %4 to i6427 %6 = and i64 %5, %128 ret i64 %629}30 31define i32 @and_bic3(i32 %0, i32 %1) {32; CHECK-LABEL: and_bic3:33; CHECK: // %bb.0:34; CHECK-NEXT: mvn w8, w035; CHECK-NEXT: orr w8, w8, #0xffff00ff36; CHECK-NEXT: and w0, w8, w137; CHECK-NEXT: ret38 %3 = and i32 %0, 6528039 %4 = xor i32 %3, -140 %5 = and i32 %4, %141 ret i32 %542}43 44define i64 @and_eon(i64 %0, i64 %1) {45; CHECK-LABEL: and_eon:46; CHECK: // %bb.0:47; CHECK-NEXT: and x8, x0, #0xff0048; CHECK-NEXT: eon x0, x8, x149; CHECK-NEXT: ret50 %3 = and i64 %0, 6528051 %4 = xor i64 %3, %152 %5 = xor i64 %4, -153 ret i64 %554}55 56define i64 @and_eon2(i32 %0, i64 %1) {57; CHECK-LABEL: and_eon2:58; CHECK: // %bb.0:59; CHECK-NEXT: mvn w8, w060; CHECK-NEXT: orr w8, w8, #0xffff00ff61; CHECK-NEXT: eor x0, x8, x162; CHECK-NEXT: ret63 %3 = and i32 %0, 6528064 %4 = xor i32 %3, -165 %5 = zext i32 %4 to i6466 %6 = xor i64 %5, %167 ret i64 %668}69 70define i32 @and_eon3(i32 %0, i32 %1) {71; CHECK-LABEL: and_eon3:72; CHECK: // %bb.0:73; CHECK-NEXT: and w8, w0, #0xff0074; CHECK-NEXT: eon w0, w8, w175; CHECK-NEXT: ret76 %3 = and i32 %0, 6528077 %4 = xor i32 %3, %178 %5 = xor i32 %4, -179 ret i32 %580}81 82define i64 @and_orn(i64 %0, i64 %1) {83; CHECK-LABEL: and_orn:84; CHECK: // %bb.0:85; CHECK-NEXT: orn w8, w1, w086; CHECK-NEXT: orr x0, x8, #0xffffffffffff00ff87; CHECK-NEXT: ret88 %3 = and i64 %0, 6528089 %4 = xor i64 %3, -190 %5 = or i64 %4, %191 ret i64 %592}93 94define i64 @and_orn2(i32 %0, i64 %1) {95; CHECK-LABEL: and_orn2:96; CHECK: // %bb.0:97; CHECK-NEXT: mvn w8, w098; CHECK-NEXT: orr w8, w8, #0xffff00ff99; CHECK-NEXT: orr x0, x8, x1100; CHECK-NEXT: ret101 %3 = and i32 %0, 65280102 %4 = xor i32 %3, -1103 %5 = zext i32 %4 to i64104 %6 = or i64 %5, %1105 ret i64 %6106}107 108define i32 @and_orn3(i32 %0, i32 %1) {109; CHECK-LABEL: and_orn3:110; CHECK: // %bb.0:111; CHECK-NEXT: orn w8, w1, w0112; CHECK-NEXT: orr w0, w8, #0xffff00ff113; CHECK-NEXT: ret114 %3 = and i32 %0, 65280115 %4 = xor i32 %3, -1116 %5 = or i32 %4, %1117 ret i32 %5118}119 120define i64 @_Z6or_bic(i64 %0, i64 %1) {121; CHECK-LABEL: _Z6or_bic:122; CHECK: // %bb.0:123; CHECK-NEXT: bic x8, x1, x0124; CHECK-NEXT: and x0, x8, #0xffffffffffff00ff125; CHECK-NEXT: ret126 %3 = and i64 %0, -65281127 %4 = xor i64 %3, -65281128 %5 = and i64 %4, %1129 ret i64 %5130}131 132define i64 @or_bic2(i32 %0, i64 %1) {133; CHECK-LABEL: or_bic2:134; CHECK: // %bb.0:135; CHECK-NEXT: mov w8, #-65281136; CHECK-NEXT: bic w8, w8, w0137; CHECK-NEXT: and x0, x8, x1138; CHECK-NEXT: ret139 %3 = and i32 %0, -65281140 %4 = xor i32 %3, -65281141 %5 = zext i32 %4 to i64142 %6 = and i64 %5, %1143 ret i64 %6144}145 146define i32 @or_bic3(i32 %0, i32 %1) {147; CHECK-LABEL: or_bic3:148; CHECK: // %bb.0:149; CHECK-NEXT: bic w8, w1, w0150; CHECK-NEXT: and w0, w8, #0xfffff000151; CHECK-NEXT: ret152 %3 = and i32 %0, -4096153 %4 = xor i32 %3, -4096154 %5 = and i32 %4, %1155 ret i32 %5156}157 158define i64 @_Z6or_orn(i64 %0, i64 %1) {159; CHECK-LABEL: _Z6or_orn:160; CHECK: // %bb.0:161; CHECK-NEXT: mov x8, #-4096162; CHECK-NEXT: bic x8, x8, x0163; CHECK-NEXT: orr x0, x8, x1164; CHECK-NEXT: ret165 %3 = and i64 %0, -4096166 %4 = xor i64 %3, -4096167 %5 = or i64 %4, %1168 ret i64 %5169}170 171define i64 @or_orn2(i32 %0, i64 %1) {172; CHECK-LABEL: or_orn2:173; CHECK: // %bb.0:174; CHECK-NEXT: mov w8, #-4096175; CHECK-NEXT: bic w8, w8, w0176; CHECK-NEXT: orr x0, x8, x1177; CHECK-NEXT: ret178 %3 = and i32 %0, -4096179 %4 = xor i32 %3, -4096180 %5 = zext i32 %4 to i64181 %6 = or i64 %5, %1182 ret i64 %6183}184 185define i64 @or_orn3(i32 %0, i64 %1) {186; CHECK-LABEL: or_orn3:187; CHECK: // %bb.0:188; CHECK-NEXT: mov w8, #-4096189; CHECK-NEXT: bic w8, w8, w0190; CHECK-NEXT: orr x0, x8, x1191; CHECK-NEXT: ret192 %3 = and i32 %0, -4096193 %4 = xor i32 %3, -4096194 %5 = zext i32 %4 to i64195 %6 = or i64 %5, %1196 ret i64 %6197}198 199define i64 @_Z6or_eon(i64 %0, i64 %1) {200; CHECK-LABEL: _Z6or_eon:201; CHECK: // %bb.0:202; CHECK-NEXT: and x8, x0, #0xfffffffffffff000203; CHECK-NEXT: eor x8, x8, x1204; CHECK-NEXT: eor x0, x8, #0xfffffffffffff000205; CHECK-NEXT: ret206 %3 = and i64 %0, -4096207 %4 = xor i64 %3, %1208 %5 = xor i64 %4, -4096209 ret i64 %5210}211 212define i64 @or_eon2(i32 %0, i64 %1) {213; CHECK-LABEL: or_eon2:214; CHECK: // %bb.0:215; CHECK-NEXT: mov w8, #-4096216; CHECK-NEXT: bic w8, w8, w0217; CHECK-NEXT: eor x0, x8, x1218; CHECK-NEXT: ret219 %3 = and i32 %0, -4096220 %4 = xor i32 %3, -4096221 %5 = zext i32 %4 to i64222 %6 = xor i64 %5, %1223 ret i64 %6224}225 226define i64 @or_eon3(i32 %0, i64 %1) {227; CHECK-LABEL: or_eon3:228; CHECK: // %bb.0:229; CHECK-NEXT: mov w8, #-4096230; CHECK-NEXT: bic w8, w8, w0231; CHECK-NEXT: eor x0, x8, x1232; CHECK-NEXT: ret233 %3 = and i32 %0, -4096234 %4 = xor i32 %3, -4096235 %5 = zext i32 %4 to i64236 %6 = xor i64 %5, %1237 ret i64 %6238}239