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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 -mattr=+ls64 -verify-machineinstrs -o - %s | FileCheck %s3 4define void @load(ptr %output, ptr %addr) {5; CHECK-LABEL: load:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: //APP8; CHECK-NEXT: ld64b x2, [x1]9; CHECK-NEXT: //NO_APP10; CHECK-NEXT: stp x8, x9, [x0, #48]11; CHECK-NEXT: stp x6, x7, [x0, #32]12; CHECK-NEXT: stp x4, x5, [x0, #16]13; CHECK-NEXT: stp x2, x3, [x0]14; CHECK-NEXT: ret15entry:16 %val = call i512 asm sideeffect "ld64b $0,[$1]", "=r,r,~{memory}"(ptr %addr)17 store i512 %val, ptr %output, align 818 ret void19}20 21define void @store(ptr %input, ptr %addr) {22; CHECK-LABEL: store:23; CHECK: // %bb.0: // %entry24; CHECK-NEXT: ldp x8, x9, [x0, #48]25; CHECK-NEXT: ldp x6, x7, [x0, #32]26; CHECK-NEXT: ldp x4, x5, [x0, #16]27; CHECK-NEXT: ldp x2, x3, [x0]28; CHECK-NEXT: //APP29; CHECK-NEXT: st64b x2, [x1]30; CHECK-NEXT: //NO_APP31; CHECK-NEXT: ret32entry:33 %val = load i512, ptr %input, align 834 call void asm sideeffect "st64b $0,[$1]", "r,r,~{memory}"(i512 %val, ptr %addr)35 ret void36}37 38define void @store2(ptr %in, ptr %addr) {39; CHECK-LABEL: store2:40; CHECK: // %bb.0: // %entry41; CHECK-NEXT: sub sp, sp, #6442; CHECK-NEXT: .cfi_def_cfa_offset 6443; CHECK-NEXT: ldpsw x2, x3, [x0]44; CHECK-NEXT: ldrsw x4, [x0, #16]45; CHECK-NEXT: ldrsw x5, [x0, #64]46; CHECK-NEXT: ldrsw x6, [x0, #100]47; CHECK-NEXT: ldrsw x7, [x0, #144]48; CHECK-NEXT: ldrsw x8, [x0, #196]49; CHECK-NEXT: ldrsw x9, [x0, #256]50; CHECK-NEXT: //APP51; CHECK-NEXT: st64b x2, [x1]52; CHECK-NEXT: //NO_APP53; CHECK-NEXT: add sp, sp, #6454; CHECK-NEXT: ret55entry:56 %0 = load i32, ptr %in, align 457 %conv = sext i32 %0 to i6458 %arrayidx1 = getelementptr inbounds i32, ptr %in, i64 159 %1 = load i32, ptr %arrayidx1, align 460 %conv2 = sext i32 %1 to i6461 %arrayidx4 = getelementptr inbounds i32, ptr %in, i64 462 %2 = load i32, ptr %arrayidx4, align 463 %conv5 = sext i32 %2 to i6464 %arrayidx7 = getelementptr inbounds i32, ptr %in, i64 1665 %3 = load i32, ptr %arrayidx7, align 466 %conv8 = sext i32 %3 to i6467 %arrayidx10 = getelementptr inbounds i32, ptr %in, i64 2568 %4 = load i32, ptr %arrayidx10, align 469 %conv11 = sext i32 %4 to i6470 %arrayidx13 = getelementptr inbounds i32, ptr %in, i64 3671 %5 = load i32, ptr %arrayidx13, align 472 %conv14 = sext i32 %5 to i6473 %arrayidx16 = getelementptr inbounds i32, ptr %in, i64 4974 %6 = load i32, ptr %arrayidx16, align 475 %conv17 = sext i32 %6 to i6476 %arrayidx19 = getelementptr inbounds i32, ptr %in, i64 6477 %7 = load i32, ptr %arrayidx19, align 478 %conv20 = sext i32 %7 to i6479 %s.sroa.10.0.insert.ext = zext i64 %conv20 to i51280 %s.sroa.10.0.insert.shift = shl nuw i512 %s.sroa.10.0.insert.ext, 44881 %s.sroa.9.0.insert.ext = zext i64 %conv17 to i51282 %s.sroa.9.0.insert.shift = shl nuw nsw i512 %s.sroa.9.0.insert.ext, 38483 %s.sroa.9.0.insert.insert = or i512 %s.sroa.10.0.insert.shift, %s.sroa.9.0.insert.shift84 %s.sroa.8.0.insert.ext = zext i64 %conv14 to i51285 %s.sroa.8.0.insert.shift = shl nuw nsw i512 %s.sroa.8.0.insert.ext, 32086 %s.sroa.8.0.insert.insert = or i512 %s.sroa.9.0.insert.insert, %s.sroa.8.0.insert.shift87 %s.sroa.7.0.insert.ext = zext i64 %conv11 to i51288 %s.sroa.7.0.insert.shift = shl nuw nsw i512 %s.sroa.7.0.insert.ext, 25689 %s.sroa.7.0.insert.insert = or i512 %s.sroa.8.0.insert.insert, %s.sroa.7.0.insert.shift90 %s.sroa.6.0.insert.ext = zext i64 %conv8 to i51291 %s.sroa.6.0.insert.shift = shl nuw nsw i512 %s.sroa.6.0.insert.ext, 19292 %s.sroa.6.0.insert.insert = or i512 %s.sroa.7.0.insert.insert, %s.sroa.6.0.insert.shift93 %s.sroa.5.0.insert.ext = zext i64 %conv5 to i51294 %s.sroa.5.0.insert.shift = shl nuw nsw i512 %s.sroa.5.0.insert.ext, 12895 %s.sroa.4.0.insert.ext = zext i64 %conv2 to i51296 %s.sroa.4.0.insert.shift = shl nuw nsw i512 %s.sroa.4.0.insert.ext, 6497 %s.sroa.4.0.insert.mask = or i512 %s.sroa.6.0.insert.insert, %s.sroa.5.0.insert.shift98 %s.sroa.0.0.insert.ext = zext i64 %conv to i51299 %s.sroa.0.0.insert.mask = or i512 %s.sroa.4.0.insert.mask, %s.sroa.4.0.insert.shift100 %s.sroa.0.0.insert.insert = or i512 %s.sroa.0.0.insert.mask, %s.sroa.0.0.insert.ext101 call void asm sideeffect "st64b $0,[$1]", "r,r,~{memory}"(i512 %s.sroa.0.0.insert.insert, ptr %addr)102 ret void103}104 105define void @multi_output(ptr %addr) {106; CHECK-LABEL: multi_output:107; CHECK: // %bb.0: // %entry108; CHECK-NEXT: //APP109; CHECK-NEXT: ld64b x0, [x0]110; CHECK-NEXT: mov x8, x0111; CHECK-NEXT: //NO_APP112; CHECK-NEXT: stp x6, x7, [x8, #48]113; CHECK-NEXT: stp x4, x5, [x8, #32]114; CHECK-NEXT: stp x2, x3, [x8, #16]115; CHECK-NEXT: stp x0, x1, [x8]116; CHECK-NEXT: ret117entry:118 %val = call { i512, ptr } asm sideeffect "ld64b $0, [$2]; mov $1, $2", "=r,=r,r,~{memory}"(ptr %addr)119 %val0 = extractvalue { i512, ptr } %val, 0120 %val1 = extractvalue { i512, ptr } %val, 1121 store i512 %val0, ptr %val1, align 8122 ret void123}124 125; FIXME: This case still crashes in RegsForValue::AddInlineAsmOperands without126; additional changes. I believe this is a bug in target-independent code, that127; is worked around in the RISC-V and SystemZ backends, but should almost128; certainly be fixed instead.129; define void @tied_constraints(ptr %addr) {130; entry:131; %in = load i512, ptr %addr, align 8132; %val = call { i512, ptr } asm sideeffect "nop", "=r,=r,0,1,~{memory}"(i512 %in, ptr %addr)133; %val0 = extractvalue { i512, ptr } %val, 0134; %val1 = extractvalue { i512, ptr } %val, 1135; store i512 %val0, ptr %val1, align 8136; ret void137; }138