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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 -mattr=+ls64 -verify-machineinstrs -o - %s | FileCheck %s3; RUN: llc -mtriple=aarch64_be -mattr=+ls64 -verify-machineinstrs -o - %s | FileCheck %s4 5define void @test_ld64b(ptr %out, ptr %addr) {6; CHECK-LABEL: test_ld64b:7; CHECK: // %bb.0: // %entry8; CHECK-NEXT: ld64b x2, [x1]9; CHECK-NEXT: stp x8, x9, [x0, #48]10; CHECK-NEXT: stp x6, x7, [x0, #32]11; CHECK-NEXT: stp x4, x5, [x0, #16]12; CHECK-NEXT: stp x2, x3, [x0]13; CHECK-NEXT: ret14entry:15 %val = tail call { i64, i64, i64, i64, i64, i64, i64, i64 } @llvm.aarch64.ld64b(ptr %addr)16 store { i64, i64, i64, i64, i64, i64, i64, i64 } %val, ptr %out, align 817 ret void18}19 20define void @test_st64b(ptr %in, ptr %addr) {21; CHECK-LABEL: test_st64b:22; CHECK: // %bb.0: // %entry23; CHECK-NEXT: ldp x8, x9, [x0, #48]24; CHECK-NEXT: ldp x6, x7, [x0, #32]25; CHECK-NEXT: ldp x4, x5, [x0, #16]26; CHECK-NEXT: ldp x2, x3, [x0]27; CHECK-NEXT: st64b x2, [x1]28; CHECK-NEXT: ret29entry:30 %val = load { i64, i64, i64, i64, i64, i64, i64, i64 }, ptr %in, align 831 %v0 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 032 %v1 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 133 %v2 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 234 %v3 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 335 %v4 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 436 %v5 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 537 %v6 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 638 %v7 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 739 tail call void @llvm.aarch64.st64b(ptr %addr, i64 %v0, i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7)40 ret void41}42 43define i64 @test_st64bv(ptr %in, ptr %addr) {44; CHECK-LABEL: test_st64bv:45; CHECK: // %bb.0: // %entry46; CHECK-NEXT: ldp x8, x9, [x0, #48]47; CHECK-NEXT: ldp x6, x7, [x0, #32]48; CHECK-NEXT: ldp x4, x5, [x0, #16]49; CHECK-NEXT: ldp x2, x3, [x0]50; CHECK-NEXT: st64bv x0, x2, [x1]51; CHECK-NEXT: ret52entry:53 %val = load { i64, i64, i64, i64, i64, i64, i64, i64 }, ptr %in, align 854 %v0 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 055 %v1 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 156 %v2 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 257 %v3 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 358 %v4 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 459 %v5 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 560 %v6 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 661 %v7 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 762 %status = tail call i64 @llvm.aarch64.st64bv(ptr %addr, i64 %v0, i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7)63 ret i64 %status64}65 66define i64 @test_st64bv0(ptr %in, ptr %addr) {67; CHECK-LABEL: test_st64bv0:68; CHECK: // %bb.0: // %entry69; CHECK-NEXT: ldp x8, x9, [x0, #48]70; CHECK-NEXT: ldp x6, x7, [x0, #32]71; CHECK-NEXT: ldp x4, x5, [x0, #16]72; CHECK-NEXT: ldp x2, x3, [x0]73; CHECK-NEXT: st64bv0 x0, x2, [x1]74; CHECK-NEXT: ret75entry:76 %val = load { i64, i64, i64, i64, i64, i64, i64, i64 }, ptr %in, align 877 %v0 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 078 %v1 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 179 %v2 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 280 %v3 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 381 %v4 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 482 %v5 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 583 %v6 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 684 %v7 = extractvalue { i64, i64, i64, i64, i64, i64, i64, i64 } %val, 785 %status = tail call i64 @llvm.aarch64.st64bv0(ptr %addr, i64 %v0, i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7)86 ret i64 %status87}88 89declare { i64, i64, i64, i64, i64, i64, i64, i64 } @llvm.aarch64.ld64b(ptr)90declare void @llvm.aarch64.st64b(ptr, i64, i64, i64, i64, i64, i64, i64, i64)91declare i64 @llvm.aarch64.st64bv(ptr, i64, i64, i64, i64, i64, i64, i64, i64)92declare i64 @llvm.aarch64.st64bv0(ptr, i64, i64, i64, i64, i64, i64, i64, i64)93